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[93.42.70.190]) by smtp.googlemail.com with ESMTPSA id t21-20020a05640203d500b0043573c59ea0sm9747593edw.90.2022.06.28.11.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 11:49:40 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Jens Axboe , Greg Kroah-Hartman , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v3 1/4] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Tue, 28 Jun 2022 20:41:34 +0200 Message-Id: <20220628184137.21678-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628184137.21678-1-ansuelsmth@gmail.com> References: <20220628184137.21678-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert qcom,krait-cc to yaml Documentation. Signed-off-by: Christian Marangi Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../bindings/clock/qcom,krait-cc.txt | 34 ----------- .../bindings/clock/qcom,krait-cc.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..8caa5a677394 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Christian Marangi + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: acpu0_aux + - const: acpu1_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&hfpll0>, <&hfpll1>, + <&acpu0_aux>, <&acpu1_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", + "acpu0_aux", "acpu1_aux", "qsb"; + #clock-cells = <1>; + }; +... From patchwork Tue Jun 28 18:41:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 586620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 164CFCCA483 for ; Tue, 28 Jun 2022 18:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233753AbiF1Stq (ORCPT ); Tue, 28 Jun 2022 14:49:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232025AbiF1Stp (ORCPT ); Tue, 28 Jun 2022 14:49:45 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 445FC248C0; Tue, 28 Jun 2022 11:49:44 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id fi2so27600352ejb.9; Tue, 28 Jun 2022 11:49:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BN3pbuhnuoIeVzm5arwXPVQQxY2/EuygWAa9khU6QiA=; b=StJaUVY/vPbqpAy4976AzxuoTZPKFFBt5JrrYPexeR07vTYMHaNYwrCf6DevenS9JH 6JCa0sysuzBxNayjn4Uh86xTIPBzMoYQnmhtZo3okw5n3UCAYiQ+LzeCTV29Ti5Xx83F /1qbvN5kGjGr4u69cTYXaaF6o9NAMcdBdcV+06g/ZY6XNPT4fH1LAd3X1nq8pSegsQ56 xBpSmaRcujF5PTSi5oK+JITOROJWMkaMbKKPqnZAoEUJLKJWnyfkvjMl32qe3GVCHeBM czmZ6jSl/4FxUdGTlDwngrtM+Ocj1Hr1RWxU+PUUaY5B2FkeE947ugcjMhDWPW3bsgcC I0ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BN3pbuhnuoIeVzm5arwXPVQQxY2/EuygWAa9khU6QiA=; b=BXdk2kUAZi5B9C6mDYss8r833ykLVp6lZA9Np8jSQKPDf0cXLoh3TQ5sSLeH3K2asp jkjRdesnWq3F7GTqyIk67h/EsOyV1aKBUoq0adYQgfFwsNL1O/Qqhg7vTTV6HN5F0DDp +e8FRkvXXF20fPTAgvxPiIrSMgETWMJF4dD+V5EvdeyrPyW5fdy7puuFH3e2FftuTwVx mzwgHJS0OVxH98hVjInp71ilqpKmPpRAlvahiD9ZZQodSYmdJT47Watr2ZUmetgNJ1nY BtHar7rj+RV4bI6oYTlZNErHQEqFvGcurKPOv5JGDcq0uDXZUYucfGcntDJvI5LNZ3ET bEQQ== X-Gm-Message-State: AJIora/eWHlnLKqq3T4cw9xfckR0oXtlXnfE8Ekye0JUuYYNd9F75Z59 UIwMsYGihYOB+BjHRv3+O+rYed/6G6g= X-Google-Smtp-Source: AGRyM1tkR58uHVPRsAI+apnkZREZui66SkuJJyeuRxz203IXo+sUeXi8ZyO/J+lCwtgTT/f1mMjfuQ== X-Received: by 2002:a17:907:6294:b0:6e1:ea4:74a3 with SMTP id nd20-20020a170907629400b006e10ea474a3mr19603049ejc.168.1656442182479; Tue, 28 Jun 2022 11:49:42 -0700 (PDT) Received: from localhost.localdomain (93-42-70-190.ip85.fastwebnet.it. [93.42.70.190]) by smtp.googlemail.com with ESMTPSA id t21-20020a05640203d500b0043573c59ea0sm9747593edw.90.2022.06.28.11.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 11:49:42 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Jens Axboe , Greg Kroah-Hartman , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 2/4] dt-bindings: arm: msm: Convert kpss-acc driver Documentation to yaml Date: Tue, 28 Jun 2022 20:41:35 +0200 Message-Id: <20220628184137.21678-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628184137.21678-1-ansuelsmth@gmail.com> References: <20220628184137.21678-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, limit all the additional bindings (clocks, clock-names, clock-output-names and #clock-cells) to v1 and also flag that these bindings should NOT be used for v2. Signed-off-by: Christian Marangi Reviewed-by: Krzysztof Kozlowski --- .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ---------- .../bindings/arm/msm/qcom,kpss-acc.yaml | 94 +++++++++++++++++++ 2 files changed, 94 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 7f696362a4a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: optional - Value type: - Definition: Name of the output clock. Typically acpuX_aux where X is a - CPU number starting at 0. - -Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml new file mode 100644 index 000000000000..3e7de44e7c74 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-acc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +maintainers: + - Christian Marangi + +description: | + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. + +properties: + compatible: + enum: + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,kpss-acc-v1 + then: + required: + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + else: + properties: + clocks: false + clock-names: false + clock-output-names: false + '#clock-cells': false + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + - | + clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; +... 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[93.42.70.190]) by smtp.googlemail.com with ESMTPSA id t21-20020a05640203d500b0043573c59ea0sm9747593edw.90.2022.06.28.11.49.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 11:49:43 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Jens Axboe , Greg Kroah-Hartman , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: arm: msm: Rework kpss-gcc driver Documentation to yaml Date: Tue, 28 Jun 2022 20:41:36 +0200 Message-Id: <20220628184137.21678-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628184137.21678-1-ansuelsmth@gmail.com> References: <20220628184137.21678-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework kpss-gcc driver Documentation to yaml Documentation. The current kpss-gcc Documentation have major problems and can't be converted directly. Introduce various changes to the original Documentation. Add #clock-cells additional binding as this clock outputs a static clk named acpu_l2_aux with supported compatible. Only some compatible require and outputs a clock, for the others, set only the reg as a required binding to correctly export the kpss-gcc registers. As the reg is shared also add the required syscon compatible. Signed-off-by: Christian Marangi --- .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 --------- .../bindings/arm/msm/qcom,kpss-gcc.yaml | 89 +++++++++++++++++++ 2 files changed, 89 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..04db9aca5ca3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Christian Marangi + +description: | + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation) and provide access + to the kpss-gcc registers. + +properties: + compatible: + items: + - enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 + - qcom,kpss-gcc-msm8660 + - qcom,kpss-gcc-mdm9615 + - const: qcom,kpss-gcc + - const: syscon + + reg: + maxItems: 1 + + clocks: + items: + - description: phandle to pll8_vote + - description: phandle to pxo_board + + clock-names: + items: + - const: pll8_vote + - const: pxo + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 +then: + required: + - clocks + - clock-names + - '#clock-cells' +else: + properties: + clock: false + clock-names: false + '#clock-cells': false + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + - | + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + }; +... + From patchwork Tue Jun 28 18:41:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 586619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB2C9CCA47E for ; Tue, 28 Jun 2022 18:49:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234134AbiF1St6 (ORCPT ); Tue, 28 Jun 2022 14:49:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233853AbiF1Str (ORCPT ); Tue, 28 Jun 2022 14:49:47 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DCCC2494B; Tue, 28 Jun 2022 11:49:46 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id sb34so27571562ejc.11; Tue, 28 Jun 2022 11:49:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3hs1h6z81DTKF28gSkM1hmpoN1hgElxYH3buRnm51V4=; b=Rz6A0UYLrFVNp59roNRJ/OoDCj8CZW2aTol+JZVxP5SBujZ6Ypnx1J0xJfuKQs+UhB dGRyvhNFoZ8oS62bC21BtO0w+9w3U9k6l2ZBBWYpfoCmUvXKZA90orDcwjP6wnC7GsHL ZnZWg7Lyf2xONtDn/eE31A4ihKiEEcLJM1doPEAMYi6oOveQnquwD7n9eG7fY9XuXs9F AhmU3XAUY4esVgzREu1ExKfofz0fd0KIFvym7/2RU6Cdqiqnrm1SazWSpoPw7TN6VaKO Pxb8D5rolp8rga4TvNMPpPsuB0fhtEwG+O5u7cAuT7Hh6kU52JuUeKCd1guXOJNfQujO AoMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3hs1h6z81DTKF28gSkM1hmpoN1hgElxYH3buRnm51V4=; b=MnowJGb0x7uT8EybC2oUJcuT2x39Wvinw4qiCi3wbIQ2vyjGQCAMr84cJEa29widDo VEPGAzgXYaTQB8A5t1BmVO6Ao768/ePacpT1Bf3o2sXAy/+NbtGifCKh5qXCIYpGmvM8 YoKvGcMbfaHdzkiJc8m17oIuy5JfrSFsi3rK85hXZMiUXWzfaX++BQ2kMPCMQVthAoS6 gPdFL7evsWTe5LmjclrF9hlhXaZyIZk6rnt+lxYU2T2FAsTv033qdJ6/kOUpxHMyG5ux 5oIXHqGefIcJ/9HJDi15upBd3Ei/hhRKxH1zEUYNssrYQsue2phRatP89ntlLRlZSkdR o19Q== X-Gm-Message-State: AJIora/5yL0LvG2ikp0BBsSPjx1fULBw8NE7VueIClxlNs0k9C8/IPPU DsafKQGR6dF+P2s3qEAadBA= X-Google-Smtp-Source: AGRyM1sFNqH2o0iEzWOXlPTJ+cex7HQa6KdetSBAEqklx7/FKY8oRD+IXSINVWhZGuby7hfHm7tMtg== X-Received: by 2002:a17:907:1b25:b0:6da:8206:fc56 with SMTP id mp37-20020a1709071b2500b006da8206fc56mr851746ejc.81.1656442184865; Tue, 28 Jun 2022 11:49:44 -0700 (PDT) Received: from localhost.localdomain (93-42-70-190.ip85.fastwebnet.it. [93.42.70.190]) by smtp.googlemail.com with ESMTPSA id t21-20020a05640203d500b0043573c59ea0sm9747593edw.90.2022.06.28.11.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 11:49:44 -0700 (PDT) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Jens Axboe , Greg Kroah-Hartman , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 4/4] ARM: dts: qcom: fix various wrong definition for kpss-gcc node Date: Tue, 28 Jun 2022 20:41:37 +0200 Message-Id: <20220628184137.21678-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628184137.21678-1-ansuelsmth@gmail.com> References: <20220628184137.21678-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix dtbs_check warning now that we have a correct kpss-gcc yaml schema. Add additional qcom,kpss-gcc compatible to differentiate devices where kpss-gcc should provide a clk and where kpss-gcc should just provide the registers and the syscon phandle. Add missing #clock-cells and remove useless clock-output-names for ipq806x. Add missing binding for msm8090 kpss-gcc node. Signed-off-by: Christian Marangi --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++-- arch/arm/boot/dts/qcom-mdm9615.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8660.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 7 +++++-- 5 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index a1c8ae516d21..a79eda05a7c2 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -836,7 +836,7 @@ mmcc: clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..34b20b3d2243 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -780,11 +780,11 @@ tcsr: syscon@1a400000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; }; lcc: clock-controller@28000000 { diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 4d4f37cebf21..216668b4f274 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -152,7 +152,7 @@ lcc: clock-controller@28000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index a258abb23a64..db90f336f029 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -391,7 +391,7 @@ vibrator@4a { }; l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; reg = <0x02082000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 4a2d74cf01d2..a11a0fe7e0a9 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -63,7 +63,7 @@ cxo_board { clock-output-names = "cxo_board"; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -148,8 +148,11 @@ clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm@108000 {