From patchwork Tue Jan 22 05:51:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156279 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7183487jaa; Mon, 21 Jan 2019 21:52:47 -0800 (PST) X-Google-Smtp-Source: ALg8bN6igUaMIxDFQE4B+NXzPhpLk0j9yiRJs4Q2iUG5YBlrzPolOBvvEYxfsy6NRupnGZJF1CkZ X-Received: by 2002:a17:902:4:: with SMTP id 4mr33140638pla.20.1548136367849; Mon, 21 Jan 2019 21:52:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136367; cv=none; d=google.com; s=arc-20160816; b=M+3tRzI8KinSf3o1oH0PfCHuBrW3M8O/eMFIRoBz9AGwfPmNukiZ34DrmNfVrP2hSD hpOkJQbNk++vK3A3ml5QonVa62YGDvSw4KPz0fpp101K/eVgco2Bqy6bW1gfhVZnJx25 8Jz76JN81uR8V5EUf5D3lOAoRIxSb4UCx1X2T1UgPlXVCTzVz0dDVKUTjnPrXc7SsYwr eXT0YHlVVnvklzv4JZ1u5GQBne2mVPZ7Rgy0oI7VT27OTSke7SRwgCAw0T9WgWTvYBj4 fWReZ/EYAzoZC8EYo7ljT4Szdrz9h7jVILgxnliA5FS9Hh3C3jEbVd7CjKE6kpcd43pj ZhDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=sl0tPf1cXbi8vKXNTpstL1d2A0LU8sPSxUtRPLPpSis=; b=URlP1oSyPMv4+ipdT+zgVg7kTPkZQqp0QOSPeTAL80zDujO6kCvcV58zuxPOSmmDKF o3Jil8ex9qajur+pUwL8j60eaOIlkC3MA/1vEG9zx7VN/92dx9UvLI751D8ejeaF92iK 6zETXh/SECl4SSGYdZxHvByirH2gB62Q5dhdP+kYJxxlYnFAPPnkaXiYedzQJMVeuGS7 keKzrCfZb77wuJi2IOFEzRjWHEQc7tZjpWO1ZyCishzPxFqfzxiey1qqBqqS0SDzQCau ZV1Ok6ZQJiNWLH+JoXvgMU9tuVmHbWX0JE5sw5bdta608ENfQSJdhkXM/eEJoYvz5vt6 QUIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jdmohsLo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:45 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 01/10] arm64: dts: qcom: sdm845: Update PIL region memory map Date: Mon, 21 Jan 2019 21:51:03 -0800 Message-Id: <20190122055112.30943-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update existing and add all missing PIL regions to the reserved memory map, as described in version 10. Signed-off-by: Bjorn Andersson --- Changes since v2: - New patch arch/arm64/boot/dts/qcom/sdm845.dtsi | 61 ++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 3 deletions(-) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0ec827394e92..cdcac3704c13 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -89,12 +89,47 @@ }; memory@86200000 { - reg = <0 0x86200000 0 0x2d00000>; + reg = <0 0x86200000 0 0x100000>; no-map; }; - wlan_msa_mem: memory@96700000 { - reg = <0 0x96700000 0 0x100000>; + memory@86300000 { + reg = <0 0x86300000 0 0x4800000>; + no-map; + }; + + memory@8ab00000 { + reg = <0 0x8ab00000 0 0x1400000>; + no-map; + }; + + memory@8bf00000 { + reg = <0 0x8bf00000 0 0x500000>; + no-map; + }; + + ipa_fw_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@8c410000 { + reg = <0 0x8c410000 0 0x5000>; + no-map; + }; + + memory@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + wlan_msa_mem: memory@8df00000 { + reg = <0 0x8df00000 0 0x100000>; no-map; }; @@ -103,10 +138,30 @@ no-map; }; + venus_mem: memory@95800000 { + reg = <0 0x95800000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@95d00000 { + reg = <0 0x95d00000 0 0x800000>; + no-map; + }; + mba_region: memory@96500000 { reg = <0 0x96500000 0 0x200000>; no-map; }; + + slpi_mem: memory@96700000 { + reg = <0 0x96700000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; }; cpus { From patchwork Tue Jan 22 05:51:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156270 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7182869jaa; Mon, 21 Jan 2019 21:51:53 -0800 (PST) X-Google-Smtp-Source: ALg8bN6b/hYtBryCy6hDF7bONQB3aiFWskqqtnvbv1OIb8QGWJvCjUKK+uOzC/s923Ujak9OWQ2Z X-Received: by 2002:a63:f412:: with SMTP id g18mr30933746pgi.262.1548136313833; Mon, 21 Jan 2019 21:51:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136313; cv=none; d=google.com; s=arc-20160816; b=LY6g0rB3rNG7SFCCCKc5oYdy9UeK+85hKe/9TI4bXWlIZo5lRFezj4YJXnW9uzxGBa ebPOpc+X1VZFubLRCmxnulv9/bHIy28xj1WXLmrO8dRHdZkutw4eFBSqVJ3QRTjKYEEL v5mBRQu7bvCAd32LhmcVra+gAZejysnSEIfdkobq3RnOePnLqyNPGbBT7du/Rlqh8O8I wYgLxzNbNnBFkYiqtbCBDreY/oxQRsBN+9CK/SPetrpzS6iTSF4dCNQTNMEMaCXASiGh NcNTiQ+kpxvIW6/gVoKDWQTadochjJwj2IHCfWM0ayr0x99yPoACbiThKYjaVpWa/9AH xM2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=rOTwnk6dtXq1KXQGBQ526dvyAfi3nAsjQPbpfKkz9uA=; b=cEZUcw9MxXjDJDDyRyinuSVdYFCTe+0OSZFjbqUYMqiAk/O86JLBginqDwKCdvxkAT H6IGeTBAwpn+Bh7A3h0ErD2bKuQVKzDkunZZ6Nqi8b+nLBBmywpTo0KhabsWfAm5U5f0 JDOgMpvDero3c9bKq76I3qtC31t334et2xzIAE6OL6aj/074D8hKguZfHe1XEWFAqnpz 4Vslz2uGlp2vxuCXS1KSkQaA+5VWKqGVgqtXvD1Rxakvek6AxeUOAeQAJIjaPOzJOMeb 7lpLL65LlMZMoA0HKbVRCnRRmTyYvy0aijOVg5uT+a9NiqelZQ66KRG1/HAQZhF6ijsK 0WMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=apNyTeTI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:46 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/10] arm64: dts: qcom: sdm845: Define rmtfs memory Date: Mon, 21 Jan 2019 21:51:04 -0800 Message-Id: <20190122055112.30943-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define the rmtfs memory node, as described in version 10 of the memory map. Signed-off-by: Bjorn Andersson --- Changes since v2: - New patch arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cdcac3704c13..64f57cc5c61a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -72,6 +72,15 @@ #size-cells = <2>; ranges; + rmtfs@85d00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x85d00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + memory@85fc0000 { reg = <0 0x85fc0000 0 0x20000>; no-map; From patchwork Tue Jan 22 05:51:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156278 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7183414jaa; Mon, 21 Jan 2019 21:52:41 -0800 (PST) X-Google-Smtp-Source: ALg8bN4FS0aSNgvPcRosrdJFsbaim2uyOYYo4/IxhqWi9/ZChXmecz2JkvlECUJCQQqdRRML+VZj X-Received: by 2002:a17:902:bb05:: with SMTP id l5mr33462892pls.230.1548136361349; Mon, 21 Jan 2019 21:52:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136361; cv=none; d=google.com; s=arc-20160816; b=DeFcjRuzKCzqQ7iFkv9aiCTcC0oxmSLZWGuz8wLTGnEpxL1TDYa1hDdbvEgLg8jlhr OT0Xz0npS3rQ/fAP0VFlUsxOSlIOuCdG9ODqBzW9JyWwRtzamYzhSa1jqQKUL2N6vbZf 5BDVJ+WapTFoac4mQ8izov+QQbfX4bjXz4jWjr2kh+tOVR9glkbazHzJRDho6h7RyIiU WAcdtk4K/rQcN6AXbx/VL/P6bi8f80yieSHt5un4v4E1HDuvk7J3y1k3RL7f3nbbsVFu m3eqwRzN5pRkbkuxB0FBD3Xs6bR9PQmp3snLxBM2J1uvGgbUS3+qm91sLNvTamYLgJB7 a83A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kRXJdEO8I/SlhbNJiF5XYNK/PWPlwRsErJzpDvsBh7A=; b=OyGg9VKVvFl/q37DNi9pF1xOsrsnp90ZnJ8aiPYP/hPkv0Gru8OY56dYiXHTO0yy5K wRKkjahOGRw1FTXAsLqEoE0kvVTIEwdvyGP5ujjDbOnb57CGJByS4ohu6xYM0T5w7NEM m6Ar5t3PUwIqXcVVveZIq9AtII2vgxfxJM7wHXXOWXU2aQpleE+IGM5m1eCN8VI/QHoH Zt9EOe5jopKK7pRu26S10jiVkjF5cspC+rbsu7nYehzcsgRa2s/9BbrxN3FZiPigJwLH gy8XR0iLBduesCY1328Q78CgFyaEPaodOgRYTTbXbwjYgQU5cBmrc51w4RKYf83l/Ifo 5upA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RnnzFMqV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:48 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/10] arm64: dts: sdm845: Introduce ADSP and CDSP PAS nodes Date: Mon, 21 Jan 2019 21:51:05 -0800 Message-Id: <20190122055112.30943-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the ADSP and CDSP nodes for PAS-based remoteproc, supporting booting these cores on e.g. the MTP, and enable the same for the MTP. Signed-off-by: Bjorn Andersson --- Changes since v2: - New patch arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 8 ++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 58 +++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index af8c6a2445a2..02b8357c8ce8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -48,6 +48,10 @@ }; }; +&adsp_pas { + status = "okay"; +}; + &apps_rsc { pm8998-rpmh-regulators { compatible = "qcom,pm8998-rpmh-regulators"; @@ -344,6 +348,10 @@ }; }; +&cdsp_pas { + status = "okay"; +}; + &gcc { protected-clocks = , , diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 64f57cc5c61a..1033b77856e6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -319,6 +319,64 @@ }; }; + adsp_pas: remoteproc-adsp { + compatible = "qcom,sdm845-adsp-pas"; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + }; + }; + + cdsp_pas: remoteproc-cdsp { + compatible = "qcom,sdm845-cdsp-pas"; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "turing"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + }; + }; + tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>; From patchwork Tue Jan 22 05:51:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156277 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7183313jaa; Mon, 21 Jan 2019 21:52:33 -0800 (PST) X-Google-Smtp-Source: ALg8bN6i87eWhSxHxVbthOjb57Abg88js1NUNTZbKuBx1X04qTWClUqdNS9C4T6tY7TZBSRf7Nzt X-Received: by 2002:a63:c451:: with SMTP id m17mr30574712pgg.27.1548136353411; Mon, 21 Jan 2019 21:52:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136353; cv=none; d=google.com; s=arc-20160816; b=Zsf2s7O7Qet5A+0Tr58/rFv5dAo8i/Od/uDT5RvNGsd/R8S1oOKuUfhNOGRyDoOc5b qRd8TZCIlkmiA7j6FN/vzejhGUQpokTj6Xiox/JxtFLoj7Qnk1DFMRj4FdnjX6xRw+2J g/Xr747aBa6sR8KCZwPzGc6fD7H2+61ZrxkW5ZhhGYkmJs3c8TqOTGMo//qHxh2X/s8p sfPOK3K/5r8vrZK7zUp+2b08MqXZpnL2vVdEPPwCReNcJ3p7O8AOBBNr8nh3oBn/IFSN KmwQdrbi8VL/8wKFsgS/nvPkt5eEqTT74T+rzpSY5TtgElt9izurWWu1+Ob/gE+kMZI/ mc5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=zCHYvSO8eaeXp9atcghciWLMcYsRcNwmxrzlQR0jYTw=; b=weH2hz415o+fQmh3JptY++EF8GnCY44EkDBLbRN5UDIVRuZxAeCFsk+41PBmMQN9B6 vOruJi8uP5m5ayNmPSwNJGMg9jBLkIQOXMsYGAJLbJzCmtMVDuC+uxU7LSaRnjTg2uMr MII4Qd7kyPQPKs/TFvwbqamZsY+qGk/VJCPCzWk19tS3mLWEl6ehVw7PIBVQInmzTi6Z moP1K27gK5WkzGdQJ9V3eTy6ja5bTtssEdC1DdXgGzArKK5j/QwsF0MURFb7E4T/gM3J hJhH2xXx4Al4TW2++j4wPvk5/ua9aTRiO7RquA2LUlYCp8WftmZLyMp5FyZcy7O/xnGf /Liw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dVLVVgeN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:49 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 04/10] dt-bindings: soc: qcom: Add AOSS QMP binding Date: Mon, 21 Jan 2019 21:51:06 -0800 Message-Id: <20190122055112.30943-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for the QMP based side-channel communication mechanism to the AOSS, which is used to control resources not exposed through the RPMh interface. Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson --- Changes since v2: - Update indentation of example - Add colling device subnodes to the description .../bindings/soc/qcom/qcom,aoss-qmp.txt | 75 +++++++++++++++++++ include/dt-bindings/power/qcom-aoss-qmp.h | 15 ++++ 2 files changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h -- 2.18.0 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt new file mode 100644 index 000000000000..881dc8c7907a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -0,0 +1,75 @@ +Qualcomm Always-On Subsystem side channel binding + +This binding describes the hardware component responsible for side channel +requests to the always-on subsystem (AOSS), used for certain power management +requests that is not handled by the standard RPMh interface. Each client in the +SoC has it's own block of message RAM and IRQ for communication with the AOSS. +The protocol used to communicate in the message RAM is known as QMP. + +The AOSS side channel exposes control over a set of resources, used to control +a set of debug related clocks and to affect the low power state of resources +related to the secondary subsystems. These resources are exposed as a set of +power-domains. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-aoss-qmp" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the message RAM for this + client's communication with the AOSS + +- interrupts: + Usage: required + Value type: + Definition: should specify the AOSS message IRQ for this client + +- mboxes: + Usage: required + Value type: + Definition: reference to the mailbox representing the outgoing doorbell + in APCS for this client, as described in mailbox/mailbox.txt + +- #power-domain-cells: + Usage: optional + Value type: + Definition: must be 1 + The provided power-domains are: + QDSS clock-domain (0), CDSP state (1), LPASS state (2), + modem state (3), SLPI state (4), SPSS state (5) and Venus + state (6). + += SUBNODES +The AOSS side channel also provides the controls for three cooling devices, +these are expressed as subnodes of the QMP node. The name of the node is used +to identify the resource and must therefor be "cx", "mx" or "ebi". + +- #cooling-cells: + Usage: optional + Value type: + Definition: must be 2 + += EXAMPLE + +The following example represents the AOSS side-channel message RAM and the +mechanism exposing the power-domains, as found in SDM845. + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0x0c300000 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #power-domain-cells = <1>; + + cx_cdev: cx { + #cooling-cells = <2>; + }; + + mx_cdev: mx { + #cooling-cells = <2>; + }; + }; diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h new file mode 100644 index 000000000000..7d8ac1a4f90c --- /dev/null +++ b/include/dt-bindings/power/qcom-aoss-qmp.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H + +#define AOSS_QMP_QDSS_CLK 0 +#define AOSS_QMP_LS_CDSP 1 +#define AOSS_QMP_LS_LPASS 2 +#define AOSS_QMP_LS_MODEM 3 +#define AOSS_QMP_LS_SLPI 4 +#define AOSS_QMP_LS_SPSS 5 +#define AOSS_QMP_LS_VENUS 6 + +#endif From patchwork Tue Jan 22 05:51:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156276 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7183196jaa; Mon, 21 Jan 2019 21:52:22 -0800 (PST) X-Google-Smtp-Source: ALg8bN5h1qRk5SW0vuw7sC26XLSs4q5Zwugf/59IkS8S1bgL4UEB9DG7m3ODEBpJ8oe4B4eGgH2b X-Received: by 2002:a63:184a:: with SMTP id 10mr30311352pgy.81.1548136342836; Mon, 21 Jan 2019 21:52:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136342; cv=none; d=google.com; s=arc-20160816; b=lcEGUs2N8jZcPWXkpsG52CpA1JepbNkt9qcirmfthkbUeStXzxhLevv//wZTfQ7KPz F6fOrwPO7N2qFRYYzBNnNgQekuD7/nsUcf+vqwnbH0oApwl9+rTvPfASy66YVa/wVCVq ofwNge/jhsOZ8xrDSy90pnV+OhH5u8QVoVGQAY0Gk+7qaE0+nTZWkdWMzwVx6Hlu/QIS A23Fs+pIxMP2sYIs0QYAmcdEhq4v+KiVDPrsmMSTStaVoQQwPWkRB5+EuPEP06uGzsml dNIdUvF3Cq2LDCgSNjRN/jWywPhMVfegTjHWAkWs0oFtdkOozD7l5S5kTGvNRNTqMeSJ 4DFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pW9+FnFhTixsM1NvLiRxk7mkM5jyq1Bhl39XrdO6+DY=; b=lsIlceF2XtGqiB08OXCBjvHHlxupXrEgA2D4nR5aSb0wdGDHTcf7TfW5HvhDA/GRDU 1WuJb5btnhdZwkHF/N/4fIlfYQLbZzepROqo6ljb7EVRNQ+ITdZ7Nd1xVYn/LYo8KgRg Wgp53eLSp8uSz28EvEiIHP6yhb3SIoZRkM/GPvq7OpD/bOtHtW3lTRPV79yYMLZMtPMV q4vFwgp4mlvPk67MVNRcG8072VIKEDNTYKh4HhcJzAKtKAlnhMDi56AXRBDo0YGTh4B4 5mTNkHm/yEZLKJXwN4lXuph5Z4sZvIWRpPSe3ERRsud8vNV/Tmqpjj7UIV7BsnxdgAgU Vj5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GI5rtE9h; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:51 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/10] soc: qcom: Add AOSS QMP genpd provider Date: Mon, 21 Jan 2019 21:51:08 -0800 Message-Id: <20190122055112.30943-7-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The AOSS QMP genpd provider implements control over power-related resources related to low-power state associated with the remoteprocs in the system as well as control over a set of clocks related to debug hardware in the SoC. Tested-by: Sai Prakash Ranjan Signed-off-by: Bjorn Andersson --- Changes since v2: - Add define for request array size drivers/soc/qcom/Kconfig | 9 +++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/aoss-qmp-pd.c | 138 +++++++++++++++++++++++++++++++++ 3 files changed, 148 insertions(+) create mode 100644 drivers/soc/qcom/aoss-qmp-pd.c -- 2.18.0 diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e2c859121b88..9d71e23005ad 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -12,6 +12,15 @@ config QCOM_AOSS_QMP micro-controller in the AOSS, using QMP, to control certain resource that are not exposed through RPMh. +config QCOM_AOSS_QMP_PD + tristate "Qualcomm AOSS Messaging Power Domain driver" + depends on QCOM_AOSS_QMP + select PM_GENERIC_DOMAINS + help + This driver provides the means of controlling the AOSS's handling of + low-power state for resources related to the remoteproc subsystems as + well as controlling the debug clocks. + config QCOM_COMMAND_DB bool "Qualcomm Command DB" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 2c04d27fbf9e..16913e73fddf 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 CFLAGS_rpmh-rsc.o := -I$(src) obj-$(CONFIG_QCOM_AOSS_QMP) += aoss-qmp.o +obj-$(CONFIG_QCOM_AOSS_QMP_PD) += aoss-qmp-pd.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_GLINK_SSR) += glink_ssr.o diff --git a/drivers/soc/qcom/aoss-qmp-pd.c b/drivers/soc/qcom/aoss-qmp-pd.c new file mode 100644 index 000000000000..82dd569a2bc9 --- /dev/null +++ b/drivers/soc/qcom/aoss-qmp-pd.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Ltd + */ +#include +#include +#include +#include +#include + +/* Requests are expected to be 96 bytes long */ +#define AOSS_QMP_PD_MSG_LEN 96 + +struct qmp_pd { + struct qmp *qmp; + + struct generic_pm_domain pd; + + const char *name; +}; + +#define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd) + +struct qmp_pd_resource { + const char *name; + int (*on)(struct generic_pm_domain *domain); + int (*off)(struct generic_pm_domain *domain); +}; + +static int qmp_pd_clock_toggle(struct qmp_pd *res, bool enable) +{ + char buf[AOSS_QMP_PD_MSG_LEN]; + + snprintf(buf, sizeof(buf), "{class: clock, res: %s, val: %d}", + res->name, !!enable); + return qmp_send(res->qmp, buf, sizeof(buf)); +} + +static int qmp_pd_clock_on(struct generic_pm_domain *domain) +{ + return qmp_pd_clock_toggle(to_qmp_pd_resource(domain), true); +} + +static int qmp_pd_clock_off(struct generic_pm_domain *domain) +{ + return qmp_pd_clock_toggle(to_qmp_pd_resource(domain), false); +} + +static int qmp_pd_image_toggle(struct qmp_pd *res, bool enable) +{ + char buf[AOSS_QMP_PD_MSG_LEN]; + + snprintf(buf, sizeof(buf), + "{class: image, res: load_state, name: %s, val: %s}", + res->name, enable ? "on" : "off"); + return qmp_send(res->qmp, buf, sizeof(buf)); +} + +static int qmp_pd_image_on(struct generic_pm_domain *domain) +{ + return qmp_pd_image_toggle(to_qmp_pd_resource(domain), true); +} + +static int qmp_pd_image_off(struct generic_pm_domain *domain) +{ + return qmp_pd_image_toggle(to_qmp_pd_resource(domain), false); +} + +static const struct qmp_pd_resource sdm845_resources[] = { + [AOSS_QMP_QDSS_CLK] = { "qdss", qmp_pd_clock_on, qmp_pd_clock_off }, + [AOSS_QMP_LS_CDSP] = { "cdsp", qmp_pd_image_on, qmp_pd_image_off }, + [AOSS_QMP_LS_LPASS] = { "adsp", qmp_pd_image_on, qmp_pd_image_off }, + [AOSS_QMP_LS_MODEM] = { "modem", qmp_pd_image_on, qmp_pd_image_off }, + [AOSS_QMP_LS_SLPI] = { "slpi", qmp_pd_image_on, qmp_pd_image_off }, + [AOSS_QMP_LS_SPSS] = { "spss", qmp_pd_image_on, qmp_pd_image_off }, + [AOSS_QMP_LS_VENUS] = { "venus", qmp_pd_image_on, qmp_pd_image_off }, +}; + +static int qmp_pd_probe(struct platform_device *pdev) +{ + struct genpd_onecell_data *data; + struct device *parent = pdev->dev.parent; + struct qmp_pd *res; + struct qmp *qmp; + size_t num = ARRAY_SIZE(sdm845_resources); + int i; + + qmp = dev_get_drvdata(pdev->dev.parent); + if (!qmp) + return -EINVAL; + + res = devm_kcalloc(&pdev->dev, num, sizeof(*res), GFP_KERNEL); + if (!res) + return -ENOMEM; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->domains = devm_kcalloc(&pdev->dev, num, sizeof(*data->domains), + GFP_KERNEL); + + for (i = 0; i < num; i++) { + pm_genpd_init(&res[i].pd, NULL, true); + res[i].qmp = qmp; + res[i].name = sdm845_resources[i].name; + + res[i].pd.name = sdm845_resources[i].name; + res[i].pd.power_on = sdm845_resources[i].on; + res[i].pd.power_off = sdm845_resources[i].off; + + data->domains[data->num_domains++] = &res[i].pd; + } + + return of_genpd_add_provider_onecell(parent->of_node, data); +} + +static int qmp_pd_remove(struct platform_device *pdev) +{ + struct device *parent = pdev->dev.parent; + + of_genpd_del_provider(parent->of_node); + + return 0; +} + +static struct platform_driver qmp_pd_driver = { + .driver = { + .name = "aoss_qmp_pd", + }, + .probe = qmp_pd_probe, + .remove = qmp_pd_remove, +}; +module_platform_driver(qmp_pd_driver); + +MODULE_ALIAS("platform:aoss_qmp_pd"); +MODULE_DESCRIPTION("Qualcomm AOSS QMP load-state driver"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Jan 22 05:51:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156274 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7183084jaa; Mon, 21 Jan 2019 21:52:14 -0800 (PST) X-Google-Smtp-Source: ALg8bN49Dh3EKco0HFy3fHI07+juHAIy6diRJbiM0Q8JWKJJQ2KuQioHc6/uTAHdkukHuKIimHx+ X-Received: by 2002:a17:902:5a0b:: with SMTP id q11mr33237246pli.186.1548136334156; Mon, 21 Jan 2019 21:52:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136334; cv=none; d=google.com; s=arc-20160816; b=dmkrvlOqwjKDee4/GjNDuLhQ6Tyue3WNxZqMqMaR571E+gBlRxxOg/IN2umIRj8mcH hRb63l7+hqo661dYGrqHpUOy+FJUphiJdNdJAmV4luJpkSKOwAPZzw2iloK0rr+cDO2p JMCori3bgZzPQ4hi+GwIRsmJ3dVf73jqZa8M39Iom3MeWdf7ArJSfF3lFa7dPVoOGq0m rQz/xiZCLi5Ew6di3Om6N2+4nGkIhRMrMx7ItpM5hzlgymt8AUvLO3pjLR3rqDp612R4 WZXj0aysO2606il5B54IPUpHXC2jv8R4tQnpIaas17Euogle6snmMD69EFq7pRMW8JLx m08g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=GjBCWU0YLJV4xz8elAnATcaOk73UwOaJ2hgycUvAavI=; b=rPLCAhQUVLy5RDB7m7xYgAscRpyfYL14aprbjm+B6cUjTDVOh4Qs3cUIi1CmiMG5p5 UHrw8ezDRQtZffa2IinQwZaW+FPd2n79rU5sSRYZ6bs/mqrFxnsa4hGV5JUAf4UfEv+b 9tZvwIoP8ArDFVM4XGAgGzormMwInddCf873rNc797y7hgW6TzxC0WbQpDashMW5wpm9 Yog9uV0Nlj5KqrzJRUMVUYCN93Os/kbzAB80AoVWE3+y2Zn+6MI+BzAYFuogtctxZJAF Kcu465tyV89iHS74j/nJlI7Z3rS8G0Z01MAJ0DmSaGMgTDAK4rJRGyZBGJDcgdvxAFNL m+Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RKDtvGQL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:54 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 08/10] remoteproc: q6v5-mss: Active powerdomain for SDM845 Date: Mon, 21 Jan 2019 21:51:10 -0800 Message-Id: <20190122055112.30943-9-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The SDM845 MSS needs the load_state powerdomain voted for during the duration of the MSS being powered on, to let the AOSS know that it may not perform certain power save measures. So vote for this. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Changes since v2: - None drivers/remoteproc/qcom_q6v5_mss.c | 31 ++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index 003186ce56c7..3e25016954d9 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -133,6 +133,7 @@ struct rproc_hexagon_res { char **proxy_clk_names; char **reset_clk_names; char **active_clk_names; + char **active_pd_names; char **proxy_pd_names; int version; bool need_mem_protection; @@ -159,10 +160,12 @@ struct q6v5 { struct clk *active_clks[8]; struct clk *reset_clks[4]; struct clk *proxy_clks[4]; + struct device *active_pds[1]; struct device *proxy_pds[3]; int active_clk_count; int reset_clk_count; int proxy_clk_count; + int active_pd_count; int proxy_pd_count; struct reg_info active_regs[1]; @@ -730,10 +733,16 @@ static int q6v5_mba_load(struct q6v5 *qproc) qcom_q6v5_prepare(&qproc->q6v5); + ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count); + if (ret < 0) { + dev_err(qproc->dev, "failed to enable active power domains\n"); + goto disable_irqs; + } + ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); if (ret < 0) { dev_err(qproc->dev, "failed to enable proxy power domains\n"); - goto disable_irqs; + goto disable_active_pds; } ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, @@ -839,6 +848,8 @@ static int q6v5_mba_load(struct q6v5 *qproc) qproc->proxy_reg_count); disable_proxy_pds: q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); +disable_active_pds: + q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); disable_irqs: qcom_q6v5_unprepare(&qproc->q6v5); @@ -878,6 +889,7 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc) qproc->active_clk_count); q6v5_regulator_disable(qproc, qproc->active_regs, qproc->active_reg_count); + q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); /* In case of failure or coredump scenario where reclaiming MBA memory * could not happen reclaim it here. @@ -1412,11 +1424,19 @@ static int q6v5_probe(struct platform_device *pdev) } qproc->active_reg_count = ret; + ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds, + desc->active_pd_names); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to attach active power domains\n"); + goto free_rproc; + } + qproc->active_pd_count = ret; + ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds, desc->proxy_pd_names); if (ret < 0) { dev_err(&pdev->dev, "Failed to init power domains\n"); - goto free_rproc; + goto detach_active_pds; } qproc->proxy_pd_count = ret; @@ -1448,6 +1468,8 @@ static int q6v5_probe(struct platform_device *pdev) detach_proxy_pds: q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); +detach_active_pds: + q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); free_rproc: rproc_free(rproc); @@ -1465,6 +1487,7 @@ static int q6v5_remove(struct platform_device *pdev) qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev); qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev); + q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); rproc_free(qproc->rproc); @@ -1491,6 +1514,10 @@ static const struct rproc_hexagon_res sdm845_mss = { "mnoc_axi", NULL }, + .active_pd_names = (char*[]){ + "load_state", + NULL + }, .proxy_pd_names = (char*[]){ "cx", "mx", From patchwork Tue Jan 22 05:51:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156272 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7182936jaa; Mon, 21 Jan 2019 21:52:00 -0800 (PST) X-Google-Smtp-Source: ALg8bN6NzOs+zQWoS68qCwg1Clmnakm+1R5BSzcFdnMszxEjnn7rcDpyTK4AaE3MhPHtx2MKPsby X-Received: by 2002:a62:9657:: with SMTP id c84mr33053718pfe.77.1548136320914; Mon, 21 Jan 2019 21:52:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136320; cv=none; d=google.com; s=arc-20160816; b=NrN6OCziuIKvu0C6LVQLQ1HfRquEKVrooG6rxqpBIt5KureKilBAbfBwjs7CaSyRNV X3oPQcFFXpnUnirqerwo+1eFmZ1kiwLfOW7tvmEvE8N3DOVfVFS366lkEsyRYUYeKJgE BXvYiMmmne/bwJy70eQwiVQBDU81u5JlcEWyHewiXGlQ9BYHSSjl7OzYo05OiWPLHRxW ohSH1YTLEH9cafaSmRUfNq8XZu6+jLJmXyBENSbBf+E/orwwXkGPhn10TigiSdK6iWN7 2AkrN2ULLvjurW8B5VjTLuk3fpUzZkd7Cxqcq0etWs0iI2b+Zze/6l51clVVN4/r/pbT 6qnw== ARC-Message-Signature: i=1; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:55 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 09/10] arm64: dts: qcom: Add AOSS QMP node Date: Mon, 21 Jan 2019 21:51:11 -0800 Message-Id: <20190122055112.30943-10-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Signed-off-by: Bjorn Andersson --- Changes since v2: - New patch arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1033b77856e6..5cc2615461da 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -2070,6 +2071,15 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, From patchwork Tue Jan 22 05:51:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156273 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp7182980jaa; Mon, 21 Jan 2019 21:52:04 -0800 (PST) X-Google-Smtp-Source: ALg8bN7M2BdikTEXuCx32dMWNH5Ox83VXovMzjMAUlDbkocuTgDUlQVLYOjSnlWhQYAY2YPho1uq X-Received: by 2002:a17:902:bd46:: with SMTP id b6mr32705548plx.231.1548136324498; Mon, 21 Jan 2019 21:52:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548136324; cv=none; d=google.com; s=arc-20160816; b=LRgd63QoV/psbqPFohvj57bVVyQ0muJwk1AJz3xk1FBZ6GNkahTRaIPlN4U8g9N6LG fm6hNZhVr2teRYshQZg1QaOfoTSzuxMm94k22gdwcek+FEkJEFfi+rqVKm0jtZ6d3h1v HzXvr50aB/TCEsLqUCLyvzEE4+6jdh53otYQolEl3teCPPqEYCYiYjGgeQNMNLKpG6jf G5GO8UmoK/YWcuBgm4gbvSOGYM2HqmW6etfchJZXB6nKGzCU+pJhFmW1Vy3WoLrKmM/j Gz6IgatKapFqEJB72sSKPcZ7QDgWvlCnDlVhOHZSsRyP2eCP7Cj15CFZEvPHqfmuo+pk BzOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=1ewOPx/Q/MvKiqCUH4MpfT+IzxQNYFi2WjzfDjsydGo=; b=bclmJjnJU0MvKYWyAEvHdmE7t2Zf+oAn/v/aYsdFYeRzdGw/rpiecI4xoV8lmsfoLa 34art4XMjV9hrwBYvLM3FUirkIdowhom3E+FDDGTvSzUgaBYgGh5APvK7DLuxQHSnR+4 bfGB7mrtggzKvGR3Lx0qaN7poTQvBHbWkIma8zUF+vUn9/UXMmnTIQHMHi7Wa1gX2hYi WThmY4vSP2VpzPloYUWgPMcp6+beEOb+KHMUGKdgeeJSaw/GUYxx2yI/TIfAaz6ZKyzu eK0eGUUarr37XiTPeSOqd5y/S8PlPzp71kbe/lrDPLlTrp0A1m4IjAVUfuTneuMDji+8 hgDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwxYZeJW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z62sm23771572pfl.33.2019.01.21.21.51.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 21:51:56 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Sibi Sankar Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/10] arm64: dts: qcom: sdm845: Add Q6V5 MSS node Date: Mon, 21 Jan 2019 21:51:12 -0800 Message-Id: <20190122055112.30943-11-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190122055112.30943-1-bjorn.andersson@linaro.org> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sibi Sankar This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson --- Changes since v2: - Picked up Sibi's patch - Fixed reg to work with address/size-cells as 2 arch/arm64/boot/dts/qcom/sdm845.dtsi | 58 ++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5cc2615461da..78df5f1bce2d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1617,6 +1617,64 @@ clock-names = "xo"; }; + mss_pil: remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = + <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, + <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "load_state", "cx", "mx", "mss"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>;