From patchwork Tue Jul 12 14:42:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 589967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02FB2CCA47F for ; Tue, 12 Jul 2022 14:43:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233617AbiGLOnC (ORCPT ); Tue, 12 Jul 2022 10:43:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233577AbiGLOnB (ORCPT ); Tue, 12 Jul 2022 10:43:01 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32007BAABC for ; Tue, 12 Jul 2022 07:43:00 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id o7so14289498lfq.9 for ; Tue, 12 Jul 2022 07:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Wjg2aNHGHhzVH0rmb+gMIgs2nU+ES+Qag4lawsLAuY=; b=puVT3P1p2qJp+NmPSiMqNLoPTA+0Ma9/RXwHTNIccnaJspTHbnbW7GacdWIOtZS3xb NjFovWEJweHWtB/B7/MwAjAiPj3FcqFe8FxGrexHv/hXii8LTj6Po7un6Qs+d4OGw/Lh +jzZiarCoF+Wn3VpT5ogHARoL1RIp4Gqiv4iXWtPOjaXCc64eVfnoaZqxdZqSwah1qFd 9wZtGq79QLrbf20QyxxHwDyH9OcU8V+DgdPXoeDjh3dfczmns3kpZd2QGscvA3nDp4O6 uHi29KLR1SL3H+laWVXpewAERf7Ek/Dc3RkO3lSSN02JHwn4A4DGs2NJvizsgulOj33W p7WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Wjg2aNHGHhzVH0rmb+gMIgs2nU+ES+Qag4lawsLAuY=; b=VCwXptTbVjkXwrY1Uq5cSUobpJ6l6b2d7u9fZRlpYyvzm8fDgdgJLShLtJTkxtXivL Om0YgW9PW/hHjf4aPbTYXazkUycLz0IT+Ee6gdCS6NaA4sQQj1CNBtQ1+nLaNq+Hezjh 9DC7NqghadDdO76ySk/eaoUBNUYzEup8brK/KE0Vw+zH7gfdVb14lgdsPG6D+0bsYdqa AYo/bwSbtYDIVI8cYYqn1OKbP897zl883kvdjch7ObDRfSxhCho0ygf69J/Es/ec64up kNpxcGBjIR//y6iLJR/fSVObsQ49iVUkrukQPaXDLV+to94TFzhR/+IBjQzeSU85SEOD qZWw== X-Gm-Message-State: AJIora/9ZRaKoGeE9mZrSIIXujUjenqsDBFjD9c+JLqZF+4ZsG3jZBPo nPA0HsSi+nR7+mRiLsAJMHmodg== X-Google-Smtp-Source: AGRyM1uBu2DHJl3HCjTGsddMKmXgr1sdiOfLGZabWUMPxQUPwM9DZ0e4PJfWBLgoYiW1Q9uT1MF3AA== X-Received: by 2002:a05:6512:b14:b0:482:a9b1:ea3 with SMTP id w20-20020a0565120b1400b00482a9b10ea3mr15787589lfu.353.1657636978549; Tue, 12 Jul 2022 07:42:58 -0700 (PDT) Received: from krzk-bin.. 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:42:58 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 1/5] dt-bindings: mmc: sdhci-msm: fix reg-names entries Date: Tue, 12 Jul 2022 16:42:41 +0200 Message-Id: <20220712144245.17417-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Bindings before conversion to DT schema expected reg-names without "_mem" suffix. This was used by older DTS files and by the MSM SDHCI driver. Reported-by: Douglas Anderson Fixes: edfbf8c307ff ("dt-bindings: mmc: sdhci-msm: Fix issues in yaml bindings") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 0853d0c32dc7..fc6e5221985a 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -60,22 +60,22 @@ properties: maxItems: 4 oneOf: - items: - - const: hc_mem + - const: hc - items: - - const: hc_mem - - const: core_mem + - const: hc + - const: core - items: - - const: hc_mem - - const: cqe_mem + - const: hc + - const: cqhci - items: - - const: hc_mem - - const: cqe_mem - - const: ice_mem + - const: hc + - const: cqhci + - const: ice - items: - - const: hc_mem - - const: core_mem - - const: cqe_mem - - const: ice_mem + - const: hc + - const: core + - const: cqhci + - const: ice clocks: minItems: 3 From patchwork Tue Jul 12 14:42:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 590209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88DACCCA47C for ; Tue, 12 Jul 2022 14:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233627AbiGLOnF (ORCPT ); Tue, 12 Jul 2022 10:43:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233628AbiGLOnE (ORCPT ); Tue, 12 Jul 2022 10:43:04 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 507F5BAAAC for ; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id bx13so10147822ljb.1 for ; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ya4IX6aXZnfGLTgjCrxYJj58Us6/c6dgWp4HrtPsHjg=; b=FXYsU7ly87F6wYfaTWoiieSaNZcXj4m5ARLB2+oLmk8ZGHhuDeq5p2kADp6tZTS8pf jH231exCwusuketydoCydTEfgKAOaP4JWSUa8qhRKntdxBt0AoJOj/M0kFBRVZ7f+/4Y qN06BX2hrlJsBphFdELj5M9zb5c1NZTBrNQ52NNBkXDTrkf0/tPPbFp2ELrXJHPRvXyX 6xK6c70XGIxZbDsbopIMLNvhNWIHFB148igi+S+jMJOUb/8yC7uhoPD1Dlg0ucKQVcyq UnpvInJev8eIUiqBd+k8EKq+GRHyjHLilRotYperMJIiJCsP1BfBQE2C7QNdXgYjsUYl TblA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ya4IX6aXZnfGLTgjCrxYJj58Us6/c6dgWp4HrtPsHjg=; b=DZbz3mCvTiRSMJRrU6BMaBCY5KYxyFgqvFD8vsHYqfGSB0S4gE/WsskUFxNNyaTBul 8T+L8XdPRfa6almwiJShzEHXGpQoewni8M1rZK8ULFhYta0pXp8hYe3ba5SxzJWUQQqR laYGeEvzWVc0T7Eh/HSYZYpdTH+GkO3pnxi0yvIuFnEQVszsIMuYzDP0b2523CSNFx0v QixRxbZZfFjK5Mym9Uc1nviReAnm2rSV56III50XnfG8e4sODVavR0YeYOBxDObRaXLJ odcmXR9jl6qrq22RxD0q2DlajiThytUbaPlR1p+UOIcml3QMmBlO08KDlzAWYa4QOGAn TGAw== X-Gm-Message-State: AJIora8nFBmgWAX9EFQlF2RYzXPw4rRfjN99CM/bL20qZpBzJYIfY0oR lZpg5oq7QoKAxzmomLtP8v048khmkkv7iAjw X-Google-Smtp-Source: AGRyM1u3532cC5WBtGnIdYIeyjGVVbUGQwnn3owEYWqzk8kJyfj5OWr/QzPaDhFTtgk57pgzjO68Kg== X-Received: by 2002:a2e:8501:0:b0:249:17a0:ebf8 with SMTP id j1-20020a2e8501000000b0024917a0ebf8mr13334851lji.125.1657636980684; Tue, 12 Jul 2022 07:43:00 -0700 (PDT) Received: from krzk-bin.. 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:42:59 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 2/5] dt-bindings: mmc: sdhci-msm: constrain reg-names per variants Date: Tue, 12 Jul 2022 16:42:42 +0200 Message-Id: <20220712144245.17417-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The entries in arrays must have fixed order, so the bindings and Linux driver expecting various combinations of 'reg' addresses was never actually conforming to guidelines. The 'core' reg entry is valid only for SDCC v4 and lower, so disallow it in SDCC v5. SDCC v4 supports CQE and ICE, so allow them, even though the qcom,sdhci-msm-v4 compatible is used also for earlier SoCs with SDCC v2 or v3, so it is not entirely accurate. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson --- Changes since v2: 1. Fix commit title typo. 2. Add Rb tag. Changes since v1: 1. Rework the patch based on Doug's feedback. --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 61 ++++++++++++------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index fc6e5221985a..2f0fdd65e908 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -49,33 +49,11 @@ properties: reg: minItems: 1 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map + maxItems: 4 reg-names: minItems: 1 maxItems: 4 - oneOf: - - items: - - const: hc - - items: - - const: hc - - const: core - - items: - - const: hc - - const: cqhci - - items: - - const: hc - - const: cqhci - - const: ice - - items: - - const: hc - - const: core - - const: cqhci - - const: ice clocks: minItems: 3 @@ -177,6 +155,43 @@ required: allOf: - $ref: mmc-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sdhci-msm-v4 + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice + unevaluatedProperties: false examples: From patchwork Tue Jul 12 14:42:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 589966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B5DFCCA488 for ; Tue, 12 Jul 2022 14:43:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233637AbiGLOnG (ORCPT ); Tue, 12 Jul 2022 10:43:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233619AbiGLOnF (ORCPT ); Tue, 12 Jul 2022 10:43:05 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E286BB7C0 for ; Tue, 12 Jul 2022 07:43:03 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id u13so14312832lfn.5 for ; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XRKH8Efyp+7WaOc4hkxLZdMcS/Z3VlGzrmvpw8bwAY8=; b=BRbdomsDxFHOtoR1pKSBtc+JkWGr0hTXZSBEwJphmxjaf3E12XpfYyF++PTjcd5G4e CiF8vU7fW8Zsfyx3fFmUP1k9lar/YwX9slYkh7Fyg71bY+mjGPkJeiTMOCRR9Yqpcslg Jq4MXfBJ9ikZUKD4+dfyY4K3YhcXYljSoLaC8ZNUcqhjPaGQyeZxoth+eO5lngYf4Qyn G6PBH368YJpixAMXBov9uzcjnDXoegf6XHIIrllIfDkoWrWDeeTE6y/ryfLIMQJ2yB3c p2d7PochcgBCieeHmHU3H0DAZqoap2ATGQM/7Fvlv5rm9K8iWfXLoF55acdVsI3UJO0d IYyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XRKH8Efyp+7WaOc4hkxLZdMcS/Z3VlGzrmvpw8bwAY8=; b=LUM0sCf4uuN8vNkpDnxKhlDL8Ynh6l66IgZUk+x+n/ix4e3IpadvMJ3upVWGGS1Ly1 cmvtACY02SPlP2Z1b+ENU+FuNKJ31z8yvSWfssE9ztzBazt6b73omigThCNk6pTZUcaL 3oUhB3JImA4bAL7dRA1p8Ao0eFsNCQT2cBnr/wV4cv7f/8sqSvmrfeRfzapbZm3BAPWk q+HZ2UGE4vF4IbR+vOs1VSMFnrdwQC0EBh2aVI8zACRfKgh5TbqYPMWyDxXS9ZxxPfGl Gvc6AL5WVSgYcpjgaUIM3l77SmsGjImGa6HzYV1H0PkS0urZ6BPNBc3m1KZFpiCQT4S4 i+7A== X-Gm-Message-State: AJIora9N8VSpcL5WOBKJSm1iR/gi27+nlxpTSgwwWGwP+ZJdN7KZ16Gm RPuVBbfLN1PGExNDXEhP/P5sMw== X-Google-Smtp-Source: AGRyM1vWK54rOOsp6Y8z7B/A8kPn7tb3dKWCgu3FZRLRPUY2zH6lMOnK9l//YCWg4/hghYpRFrfXYw== X-Received: by 2002:a05:6512:12c8:b0:489:efbf:18d1 with SMTP id p8-20020a05651212c800b00489efbf18d1mr2700825lfg.192.1657636982571; Tue, 12 Jul 2022 07:43:02 -0700 (PDT) Received: from krzk-bin.. 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:43:02 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 3/5] arm64: dts: qcom: align SDHCI reg-names with DT schema Date: Tue, 12 Jul 2022 16:42:43 +0200 Message-Id: <20220712144245.17417-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index a6cb0dafcc17..2b9374f61d5b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -379,7 +379,7 @@ spmi_bus: spmi@200f000 { sdhc_1: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 48bc2e09128d..0bdf4d39f778 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1469,7 +1469,7 @@ lpass_codec: audio-codec@771c000 { sdhc_1: mmc@7824000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; @@ -1487,7 +1487,7 @@ sdhc_1: mmc@7824000 { sdhc_2: mmc@7864000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 1bc0ef476cdb..97dde1a429d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -799,7 +799,7 @@ sdhc_1: mmc@7824900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; @@ -859,7 +859,7 @@ sdhc_2: mmc@7864900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7864900 0x500>, <0x7864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8bc6c070e306..35c1ca080684 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -464,7 +464,7 @@ usb@f9200000 { sdhc1: mmc@f9824900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; @@ -487,7 +487,7 @@ sdhc1: mmc@f9824900 { sdhc2: mmc@f98a4900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 25d6b26fab60..9745df5dc007 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2896,7 +2896,7 @@ hsusb_phy2: phy@7412000 { sdhc1: mmc@7464900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07464900 0x11c>, <0x07464000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; @@ -2920,7 +2920,7 @@ sdhc1: mmc@7464900 { sdhc2: mmc@74a4900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index e263a59d84b0..c98f36f95f3c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2078,7 +2078,7 @@ qusb2phy: phy@c012000 { sdhc2: mmc@c0a4900 { compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; From patchwork Tue Jul 12 14:42:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 590208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64A08C433EF for ; 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:43:04 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 4/5] ARM: dts: qcom: align SDHCI reg-names with DT schema Date: Tue, 12 Jul 2022 16:42:44 +0200 Message-Id: <20220712144245.17417-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++--- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 3e8bded2b5c8..45f3cbcf6238 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -422,7 +422,7 @@ blsp2_uart2: serial@f995e000 { mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, @@ -435,7 +435,7 @@ mmc@f9824900 { mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index a2632349cec4..1b98764bab7a 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -224,6 +224,7 @@ vqmmc: regulator@1948000 { sdhci: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c>, <0x7824000 0x800>; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 0b5effdb269a..f711463d22dc 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -137,7 +137,7 @@ apcs: syscon@f9011000 { sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -153,7 +153,7 @@ sdhc_1: mmc@f9824900 { sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -169,7 +169,7 @@ sdhc_2: mmc@f98a4900 { sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 11b4206036e6..971eceaef3d1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -439,7 +439,7 @@ acc3: clock-controller@f90b8000 { sdhc_1: mmc@f9824900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -456,7 +456,7 @@ sdhc_1: mmc@f9824900 { sdhc_3: mmc@f9864900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -475,7 +475,7 @@ sdhc_3: mmc@f9864900 { sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7a193678b4f5..4f3389cb6300 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -334,7 +334,7 @@ glink-edge { sdhc_1: mmc@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; - reg-names = "hc_mem"; + reg-names = "hc"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; From patchwork Tue Jul 12 14:42:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 589965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A964C433EF for ; Tue, 12 Jul 2022 14:43:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233710AbiGLOnc (ORCPT ); Tue, 12 Jul 2022 10:43:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233676AbiGLOnS (ORCPT ); Tue, 12 Jul 2022 10:43:18 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45D01BBD0B for ; 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[88.93.169.171]) by smtp.gmail.com with ESMTPSA id w15-20020a05651234cf00b00489e88d6a72sm737577lfr.198.2022.07.12.07.43.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 07:43:06 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski , Douglas Anderson Subject: [PATCH v3 5/5] ARM: dts: qcom: align SDHCI clocks with DT schema Date: Tue, 12 Jul 2022 16:42:45 +0200 Message-Id: <20220712144245.17417-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> References: <20220712144245.17417-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The DT schema expects clocks iface-core order. No functional change. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-apq8084.dtsi | 12 ++++++------ arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- arch/arm/boot/dts/qcom-msm8226.dtsi | 18 +++++++++--------- arch/arm/boot/dts/qcom-msm8974.dtsi | 18 +++++++++--------- arch/arm/boot/dts/qcom-msm8974pro.dtsi | 6 +++--- 5 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 45f3cbcf6238..c887ac5cdd7d 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -425,10 +425,10 @@ mmc@f9824900 { reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; @@ -438,10 +438,10 @@ mmc@f98a4900 { reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 1b98764bab7a..a8a32a5e7e5d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -228,9 +228,9 @@ sdhci: mmc@7824900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_DCD_XO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index f711463d22dc..9d4223bf8fc1 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -141,10 +141,10 @@ sdhc_1: mmc@f9824900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc1_default_state>; status = "disabled"; @@ -157,10 +157,10 @@ sdhc_2: mmc@f98a4900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_default_state>; status = "disabled"; @@ -173,10 +173,10 @@ sdhc_3: mmc@f9864900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc3_default_state>; status = "disabled"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 971eceaef3d1..1f4baa6ac64d 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -443,10 +443,10 @@ sdhc_1: mmc@f9824900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <8>; non-removable; @@ -460,10 +460,10 @@ sdhc_3: mmc@f9864900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; #address-cells = <1>; @@ -479,10 +479,10 @@ sdhc_2: mmc@f98a4900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom-msm8974pro.dtsi index 1e882e16a221..58df6e75ab6d 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974pro.dtsi @@ -10,10 +10,10 @@ &gpu { }; &sdhc_1 { - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names = "core", "iface", "xo", "cal", "sleep"; + clock-names = "iface", "core", "xo", "cal", "sleep"; };