From patchwork Wed Jul 13 04:22:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 590263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB027C43334 for ; Wed, 13 Jul 2022 04:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234142AbiGME3V (ORCPT ); Wed, 13 Jul 2022 00:29:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234062AbiGME25 (ORCPT ); Wed, 13 Jul 2022 00:28:57 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09BD22CDE7; Tue, 12 Jul 2022 21:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657686531; x=1689222531; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=CUOQ3MTsrIQPtqhO8Ly+54TTEamCTAfU40O4qkARrq0=; b=cw2PZBY672voIlwjzq8qxVOZa4Eh/4DQRpgRO/DM+seK0MonfuvX0es+ nypjMtSBO5v1c3Rf4BA4wfD7esdt0Jj2u6j98F30Ngl+spEM1tF7rw2RF LxxmmJCCdLT6G32i3boRdBXKMn/XbUvBCazf6KzIVkF5BaNLdsqzBQ8Xi hx3CWc/RJ8BUGdkV2S16VGAUIJPutSgA7CQYShyvbWhVR96Ei6lz8JCWV otNtgZ2OPzDJLGfG+l6mpZ54ZRu1ymOT+QNrb4sxpUkZv7w/JFMKegW+r oCmyAOzv11jg+lnH+JfzfoSbAUQpJJvVbx9WxYNOCCVs1aUb0zyhDTkUb g==; X-IronPort-AV: E=McAfee;i="6400,9594,10406"; a="264894382" X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="264894382" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2022 21:28:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="570463222" Received: from srikandan-ilbpg12.png.intel.com ([10.88.229.69]) by orsmga006.jf.intel.com with ESMTP; 12 Jul 2022 21:28:43 -0700 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v6 1/4] spi: dw: Fix IP-core versions macro Date: Wed, 13 Jul 2022 12:22:20 +0800 Message-Id: <20220713042223.1458-2-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220713042223.1458-1-nandhini.srikandan@intel.com> References: <20220713042223.1458-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add the missing underscore in IP version macro to avoid compilation issue. The macro is used for IP version comparison in the current patchset. Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface") Signed-off-by: Nandhini Srikandan Acked-by: Serge Semin --- drivers/spi/spi-dw.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index d5ee5130601e..79d853f6d192 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -23,7 +23,7 @@ ((_dws)->ip == DW_ ## _ip ## _ID) #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \ - (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ver) + (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver) #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==) From patchwork Wed Jul 13 04:22:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 591151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7D97CCA480 for ; Wed, 13 Jul 2022 04:29:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233322AbiGME3W (ORCPT ); Wed, 13 Jul 2022 00:29:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234077AbiGME26 (ORCPT ); Wed, 13 Jul 2022 00:28:58 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E5DF32B85; Tue, 12 Jul 2022 21:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657686531; x=1689222531; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=mb8fOeDMOUQ3s+b4ghuFSAs0by4vPak2ZcTmVb4tKqU=; b=OeFStukkIhKjRHkquwEdHJJXhxrtsJMdPtidfphUVf9Op0GlUIw1iP6g wsApkgtaf5wcYlMdqdI9IUE0F39MsP2d/DHFvQjTtdz7Ahcosq99iw++E 3d2eOgeTJWxRSZdyCBuNGXkW3RprT4+pjk34IKpcry8HFogDLSenY2PjF dCoSE0Y593ePwM+ROgs3D4iB+O8/RkQBYv2m0Mk+XvTJ7kDMs46/tglhX e22LPhiLgsTuZKZX+KeKHraa74O8EIL/KdBNOGzqcgoLynPESwS6wkrgN SuiMEzalxJOwqfupGQ1TLM3G1AJ+YChT4cznibNRPnIXn6p/kuWfpxBxv A==; X-IronPort-AV: E=McAfee;i="6400,9594,10406"; a="264894386" X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="264894386" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2022 21:28:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="570463243" Received: from srikandan-ilbpg12.png.intel.com ([10.88.229.69]) by orsmga006.jf.intel.com with ESMTP; 12 Jul 2022 21:28:47 -0700 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v6 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SOC Date: Wed, 13 Jul 2022 12:22:21 +0800 Message-Id: <20220713042223.1458-3-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220713042223.1458-1-nandhini.srikandan@intel.com> References: <20220713042223.1458-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add documentation for SPI controller in Intel Thunder Bay SoC. Signed-off-by: Nandhini Srikandan Acked-by: Rob Herring Reviewed-by: Serge Semin --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index d7e08b03e204..5ecd996ebf33 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -61,6 +61,8 @@ properties: - const: snps,dw-apb-ssi - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi + - description: Intel Thunder Bay SPI Controller + const: intel,thunderbay-ssi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller From patchwork Wed Jul 13 04:22:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 590262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69796C43334 for ; Wed, 13 Jul 2022 04:29:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234107AbiGME32 (ORCPT ); Wed, 13 Jul 2022 00:29:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234102AbiGME3B (ORCPT ); Wed, 13 Jul 2022 00:29:01 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEC336B26A; Tue, 12 Jul 2022 21:28:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657686534; x=1689222534; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=l+ZqLrpVFlkrQ2zO4adzOFv+jVRMntH8EJhMK/ZmKL4=; b=XyQ+GGtCRy6K3U/XdN24rto4cBQ4d2lIMHVHicDb9v6kOy6/66xVQEXB T9QF0W9i8h6jSbIILUd7fcXEMVI4y0hOGRMiFQZrhBSWq4XbOg7rqe3P0 J03GboYFB4YFj4/MZnZKUoomolbzsd5nkDTHwbSkEOpSbmMGEgKZ7VtLm 7TUtIHcAvoTGvGgv1O8sxHkEq0rKphLFNfiPVZalMCoKUdC0EYfz5HTTK +GzSe3pJKjvw2xitzulPLoAL+GD7T0H/C/TXfmIiTGVVNn8NaYMif8/0R CEqmq0HTtml9tsj346/bams4MCmpgD1hXNJoTeksEWdsfbnOHb71T64vE A==; X-IronPort-AV: E=McAfee;i="6400,9594,10406"; a="264894389" X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="264894389" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2022 21:28:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="570463277" Received: from srikandan-ilbpg12.png.intel.com ([10.88.229.69]) by orsmga006.jf.intel.com with ESMTP; 12 Jul 2022 21:28:51 -0700 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v6 3/4] spi: dw: Add support for master mode selection for DWC SSI controller Date: Wed, 13 Jul 2022 12:22:22 +0800 Message-Id: <20220713042223.1458-4-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220713042223.1458-1-nandhini.srikandan@intel.com> References: <20220713042223.1458-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add support to select the controller mode as master mode by setting Bit 31 of CTRLR0 register. This feature is supported for controller versions above v1.02. Signed-off-by: Nandhini Srikandan Acked-by: Serge Semin --- drivers/spi/spi-dw-core.c | 5 +++-- drivers/spi/spi-dw.h | 8 +------- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index ecea471ff42c..41ae21e1b879 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) if (spi->mode & SPI_LOOP) cr0 |= DW_HSSI_CTRLR0_SRL; - if (dws->caps & DW_SPI_CAP_KEEMBAY_MST) - cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST; + /* CTRLR0[31] MST */ + if (dw_spi_ver_is_ge(dws, HSSI, 102A)) + cr0 |= DW_HSSI_CTRLR0_MST; } return cr0; diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 79d853f6d192..8b8f924ac410 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -94,13 +94,7 @@ #define DW_HSSI_CTRLR0_SCPOL BIT(9) #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10) #define DW_HSSI_CTRLR0_SRL BIT(13) - -/* - * For Keem Bay, CTRLR0[31] is used to select controller mode. - * 0: SSI is slave - * 1: SSI is master - */ -#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31) +#define DW_HSSI_CTRLR0_MST BIT(31) /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) From patchwork Wed Jul 13 04:22:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srikandan, Nandhini" X-Patchwork-Id: 591150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7310C43334 for ; Wed, 13 Jul 2022 04:29:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234267AbiGME3f (ORCPT ); Wed, 13 Jul 2022 00:29:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233545AbiGME3D (ORCPT ); Wed, 13 Jul 2022 00:29:03 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3080C2A9; Tue, 12 Jul 2022 21:28:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657686538; x=1689222538; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=NoB13u4fK3Q3uVQDxAOnHpTJ7tm+CsyAuJJu2/m52q4=; b=dcuAMsXd37tlk+gEz/FaYDgKVSeF6n4/szxOoJonJPjgzr5iSlQDgD91 bSy3DajDv0WOKFvI0GYFtDeon/4lE4UGkGPhpk0tfgPqVESBXtwYaASgP MlMpl0mQAqLL8qZKBPfZ9vEryG1Sq2/6Iul+qpawJcupxx6KP14XNsP2P 68YmTnQSAKADmYI9m82iWm82iI2NAWCr5WIIEzx/+HmSuCR0Tt7ipWbzl JQ5xptNkcj1+F8RAB+PfNrL4Psp/VSDypNd1c/APQvQrgAH7eK2m12XXt xEXTNooiC5cBbLlPRVJUUjO8HlxjdLkPsGrcjkDt1oaO9YRiv8ph4WEmb Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10406"; a="264894399" X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="264894399" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2022 21:28:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,267,1650956400"; d="scan'208";a="570463292" Received: from srikandan-ilbpg12.png.intel.com ([10.88.229.69]) by orsmga006.jf.intel.com with ESMTP; 12 Jul 2022 21:28:54 -0700 From: nandhini.srikandan@intel.com To: fancer.lancer@gmail.com, broonie@kernel.org, robh+dt@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, mgross@linux.intel.com, kris.pan@intel.com, kenchappa.demakkanavar@intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v6 4/4] spi: dw: Add support for Intel Thunder Bay SPI controller Date: Wed, 13 Jul 2022 12:22:23 +0800 Message-Id: <20220713042223.1458-5-nandhini.srikandan@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220713042223.1458-1-nandhini.srikandan@intel.com> References: <20220713042223.1458-1-nandhini.srikandan@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Nandhini Srikandan Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by: Nandhini Srikandan Acked-by: Serge Semin --- drivers/spi/spi-dw-mmio.c | 8 ++++---- drivers/spi/spi-dw.h | 3 +-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 5101c4c6017b..26c40ea6dd12 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev, return 0; } -static int dw_spi_keembay_init(struct platform_device *pdev, - struct dw_spi_mmio *dwsmmio) +static int dw_spi_intel_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) { dwsmmio->dws.ip = DW_HSSI_ID; - dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST; return 0; } @@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init}, { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init}, - { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, + { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init}, + { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, { /* end of table */} diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 8b8f924ac410..9e8eb2b52d5c 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -31,8 +31,7 @@ /* DW SPI controller capabilities */ #define DW_SPI_CAP_CS_OVERRIDE BIT(0) -#define DW_SPI_CAP_KEEMBAY_MST BIT(1) -#define DW_SPI_CAP_DFS32 BIT(2) +#define DW_SPI_CAP_DFS32 BIT(1) /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ #define DW_SPI_CTRLR0 0x00