From patchwork Wed Jan 30 11:04:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 157062 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5799052jaa; Wed, 30 Jan 2019 03:04:48 -0800 (PST) X-Google-Smtp-Source: ALg8bN6So8E7S49HZjTv/37DUD1nf7zKxed92rewQmXepleN+5L7zdsDYZb8LTeR/FRkEPMMi2Gz X-Received: by 2002:a17:902:6b49:: with SMTP id g9mr29379268plt.98.1548846287958; Wed, 30 Jan 2019 03:04:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548846287; cv=none; d=google.com; s=arc-20160816; b=b3PnNiWaBmUHri+XmLtW/sYxe5N1JiA2EGS+ruVDjt03O/ihP1ZFCFcrcs+D8WW9Zi mv5wYZLlZ9ftGS8hG3uwJPjmGywzMbXbp2dObe06QHE4Wj6bRTekwX28XMRrkS3hCiFn R4ds0+xLk4S+T71fNHzeZs0FdQiXDtRW1g8OZaT9EPYMog69ir6Xk6Xk+JTi8CKe6Pwc THXkcHPZyWekJx0YlQ/VMYp+LdpC9brRLxE01VUO4JbpFbOjc9gwijDzkNrHTyRiMkul 7Um/NwwhygSQ89ma6hyW5y5uNc8EKXPtvkQlLR/UE1n6R7JivYDLmEm3DoS0OjqDgOlE 2/tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cJVPwkmiIQelbKGNm2p5QIWk1VCEgPV2Jz4v/peH4c0=; b=tdc4z5q3UyE6LiosTbZBs2XUo8HVATbQ14u/ADJ9Lz8AlH3fq87oNMd21c1cwfFV7U GP6DYvQ5qDm2sgN7W0gAt/G1ClAANW1xYJCN1inFgjT1Bh30R1mCbEScUk44oq3meuBi ZLWXxxVMmJFH5Q/5LLWuBMpDwf5GDJbtcgw21QdrtpF47uX7OwCvZnIDq3dtLrT+h4sE MIo0tDtvh/YvoiHlvk8dJ0Bt77ilDqR5+IShfpyBN8W3fm0plBpO8clZit5DsdL78Vzt N4toiVMdn03AWxpLT2Lv5/33e9ykCBFuDxGOeEbHjtKOYFv6zoVXdnEBcCLP3hwecZlU T+Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IWr9Rc2j; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id w16sm1138208wrp.1.2019.01.30.03.04.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 03:04:44 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Archit Taneja , Vivek Gautam , Srinivas Kandagatla Subject: [PATCH v2 3/6] arm64: qcom: msm8996.dtsi: Add Display nodes Date: Wed, 30 Jan 2019 11:04:34 +0000 Message-Id: <20190130110437.5424-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> References: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Archit Taneja Signed-off-by: Archit Taneja [Removed instances of mmagic clocks; Use qcom,msm8996-smmu-v2 bindings] Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 120 ++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 96adda520bd5..0d0b9482aa4d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1337,6 +1337,126 @@ "bus_slave"; }; }; + + mdss: mdss@900000 { + compatible = "qcom,mdss"; + + reg = <0x900000 0x1000>, + <0x9b0000 0x1040>, + <0x9b8000 0x1040>; + reg-names = "mdss_phys", + "vbif_phys", + "vbif_nrt_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&mmcc MDSS_AHB_CLK>; + clock-names = "iface_clk"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@901000 { + compatible = "qcom,mdp5"; + reg = <0x901000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "core_clk", + "iommu_clk", + "vsync_clk"; + + iommus = <&mdp_smmu 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf3_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; + + hdmi: hdmi-tx@9a0000 { + compatible = "qcom,hdmi-tx-8996"; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; + reg-names = "core_physical", + "qfprom_physical", + "hdcp_physical"; + + interrupt-parent = <&mdss>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>, + <&mmcc MDSS_EXTPCLK_CLK>; + clock-names = + "mdp_core_clk", + "iface_clk", + "core_clk", + "alt_iface_clk", + "extp_clk"; + + phys = <&hdmi_phy>; + phy-names = "hdmi_phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_in: endpoint { + remote-endpoint = <&mdp5_intf3_out>; + }; + }; + }; + }; + + hdmi_phy: hdmi-phy@9a0600 { + #phy-cells = <0>; + compatible = "qcom,hdmi-phy-8996"; + reg = <0x9a0600 0x1c4>, + <0x9a0a00 0x124>, + <0x9a0c00 0x124>, + <0x9a0e00 0x124>, + <0x9a1000 0x124>, + <0x9a1200 0x0c8>; + reg-names = "hdmi_pll", + "hdmi_tx_l0", + "hdmi_tx_l1", + "hdmi_tx_l2", + "hdmi_tx_l3", + "hdmi_phy"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&gcc GCC_HDMI_CLKREF_CLK>; + clock-names = "iface_clk", + "ref_clk"; + }; + }; }; adsp-pil { From patchwork Wed Jan 30 11:04:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 157063 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5799089jaa; Wed, 30 Jan 2019 03:04:49 -0800 (PST) X-Google-Smtp-Source: ALg8bN5FXaxV4O3pEl6RjBBhbTJO1uMghWcpJq7txlutzMJeM0itB6SfQyuJ42Q8L/YFExdgacjQ X-Received: by 2002:a17:902:9a9:: with SMTP id 38mr29414968pln.204.1548846289308; Wed, 30 Jan 2019 03:04:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548846289; cv=none; d=google.com; s=arc-20160816; b=EZqYt4DGnSmKKV2krZQ3afRWkUQO9dNbzJwv5KiTPDau1deA1RMILbYrhivbh8f28t O7nT933XYElRw0YVlnv+8LaWDoq/P8PLAdwo06yH2VqbMWjPoDp9nTC2DrrXZ+nUuU/s DxS6jNgY5sEQtg0ZHLklZn3syO+XPUNuXbsQNWd28f/YUuN5bLIAV7VWsBV2ECDQU8mF 8CQWTVlq7NRQ83F4nYvbU02REASFy/38dDZctc5jzXQLxu612zKflsRS+9GoQ2RTiGw2 KHX9Cm4IuZwAppge62u+gI+YqMbjkYgpSOYyXmJpv0j9isrVe1i6kRkl3ZbHkBt3Xwwm wALQ== ARC-Message-Signature: i=1; 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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id w16sm1138208wrp.1.2019.01.30.03.04.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 03:04:45 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jordan Crouse , Vivek Gautam , Srinivas Kandagatla Subject: [PATCH v2 4/6] arm64: dts: Add Adreno GPU definitions Date: Wed, 30 Jan 2019 11:04:35 +0000 Message-Id: <20190130110437.5424-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> References: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jordan Crouse Add an initial node for the Adreno GPU. Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 86 +++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0d0b9482aa4d..095041589954 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -84,6 +84,12 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; + + zap_shader_region: gpu@8f200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; }; cpus { @@ -796,6 +802,11 @@ reg = <0x24f 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu_speed_bin@133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; }; phy@34000 { @@ -1338,6 +1349,81 @@ }; }; + gpu@b00000 { + compatible = "qcom,adreno-530.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0xb00000 0x3f000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc GPU_GX_GFX3D_CLK>, + <&mmcc GPU_AHB_CLK>, + <&mmcc GPU_GX_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>; + + clock-names = "core", + "iface", + "rbbmtimer", + "mem", + "mem_iface"; + + power-domains = <&mmcc GPU_GDSC>; + iommus = <&adreno_smmu 0>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-fault-detect-mask; + + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible ="operating-points-v2"; + + /* + * 624Mhz and 560Mhz are only available on speed + * bin (1 << 0). All the rest are available on + * all bins of the hardware + */ + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-supported-hw = <0x01>; + }; + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-supported-hw = <0x01>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-supported-hw = <0xFF>; + }; + opp-401800000 { + opp-hz = /bits/ 64 <401800000>; + opp-supported-hw = <0xFF>; + }; + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-supported-hw = <0xFF>; + }; + opp-214000000 { + opp-hz = /bits/ 64 <214000000>; + opp-supported-hw = <0xFF>; + }; + opp-133000000 { + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0xFF>; + }; + }; + + zap-shader { + memory-region = <&zap_shader_region>; + }; + }; + mdss: mdss@900000 { compatible = "qcom,mdss"; From patchwork Wed Jan 30 11:04:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 157065 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5799152jaa; Wed, 30 Jan 2019 03:04:52 -0800 (PST) X-Google-Smtp-Source: ALg8bN6w2z0FfCy//G+Y3JepcjSO+bU5Q2YSLHLV6mv7CFMynWxuB6GZnVeYBQstkAckIQOoYvXo X-Received: by 2002:a63:2d2:: with SMTP id 201mr27080143pgc.14.1548846292631; Wed, 30 Jan 2019 03:04:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548846292; cv=none; d=google.com; s=arc-20160816; b=APge2n0knyWPrgI9JD5Al07Nx2YvSn36RGa6fUj8oPT8qygySVC+BiBbpMTKv6TuG8 Nj9LgX+pqgVwKMnhhRLrG1CyPdZBWYRjVgdU3dd10aaxNEgK1fe/hYc555tSWikYntPm 8A7yqxN2Z9Ko3iVaGz3t/amrOStQv7/IDV2f9ymDZgOJXtGedgRb+8AEsgXN2QdO0+hn F3N5WxXJLSa/+ES3qsGY1ApTJsPeRSqpV0Wry7GbRsEUUxRjPL0q2iF8/y1b1QXDf7x4 nD8e5PvaH/1Qi7kaXTlpUz/hDnvIAbRJgTu+IKTOBKfRdCfgF7qEyaXHMB38+u/LkzKl NTJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1JcYrtZvqszw/iSfFkQPBLaB9WUxnesJNxpeizJa6Cw=; b=bnGJJZLl+WIpbV0V+dbAfmUPBbVBhedG/Is0uNbBhlItPljt2JJBnQZdeyYlWh05QP k6aq5q8W0XO1KBEaPH9pv8UmEVYR+81yU4K1RYX6ly29pSY4/MSig9mRiikk+/fdLbe9 D87cakKYIZHmwlRkYsgRFv7/sB3dPsjY5xi5sWdc12vLYZ1dci8YeTuxwBEUoWN2BNyj JYs3DRMxhH1MnqEX+db5oYSn9qwo1px+Ot2cYHx4zUkv93uInDekFkID3EQLwnUZJGGC LXU0gfvvOgTJQ9IxF8a76cUOG4Dtj8xCK+5KJvdfH4GcAJQvGeR8YOE9yMnG+uLb9gZ6 E/4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KItaiU4h; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id w16sm1138208wrp.1.2019.01.30.03.04.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 03:04:47 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 6/6] arm64: dts: db820c: Add sound card support Date: Wed, 30 Jan 2019 11:04:37 +0000 Message-Id: <20190130110437.5424-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> References: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds support both digital and analog audio on DB820c. This board has HDMI port and 3.5mm audio jack to support both digital and analog audio respectively. Signed-off-by: Srinivas Kandagatla --- .../dts/qcom/apq8096-db820c-pmic-pins.dtsi | 8 + arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 94 ++++++++++++ arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 43 ++++++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 140 ++++++++++++++++++ 4 files changed, 285 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi index a6ad3d7fe655..31a3e3311ad5 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi @@ -36,6 +36,14 @@ }; }; + audio_mclk: clk_div1 { + pinconf { + pins = "gpio15"; + function = "func1"; + power-source = ; // 1.8V + }; + }; + volume_up_gpio: pm8996_gpio2 { pinconf { pins = "gpio2"; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 1e78f0b47c89..7f4a8a08a029 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -18,6 +18,8 @@ #include "apq8096-db820c-pmic-pins.dtsi" #include #include +#include +#include /* * GPIO name legend: proper name = the GPIO line is used as GPIO @@ -63,6 +65,7 @@ }; clocks { + compatible = "simple-bus"; divclk4: divclk4 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -72,6 +75,15 @@ pinctrl-names = "default"; pinctrl-0 = <&divclk4_pin_a>; }; + + div1_mclk: divclk1 { + compatible = "gpio-gate-clock"; + pinctrl-0 = <&audio_mclk>; + pinctrl-names = "default"; + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; + #clock-cells = <0>; + enable-gpios = <&pm8994_gpios 15 0>; + }; }; soc { @@ -453,6 +465,16 @@ }; }; + slim_msm: slim@91c0000 { + ngd@1 { + wcd9335: codec@1{ + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + }; + }; + }; + mdss@900000 { status = "okay"; @@ -666,3 +688,75 @@ }; }; }; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "DB820c"; + audio-routing = "RX_BIAS", "MCLK"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + hdmi-dai-link { + link-name = "HDMI"; + cpu { + sound-dai = <&q6afedai HDMI_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&hdmi 0>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 6>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 131878db9852..fba2229b6236 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -13,6 +13,49 @@ &msmgpio { + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + config { + pins = "gpio64"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio64"; + function = "gpio"; + }; + config { + pins = "gpio64"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; + blsp1_spi0_default: blsp1_spi0_default { pinmux { function = "blsp_spi1"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 095041589954..79fa666a4522 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1183,6 +1184,33 @@ power-domains = <&mmcc MDSS_GDSC>; }; + lpass_q6_smmu: arm,smmu-lpass_q6@1600000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0x1600000 0x20000>; + #iommu-cells = <1>; + power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; + + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, + <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; + clock-names = "iface", "bus"; + status = "okay"; + }; + agnoc@0 { power-domains = <&gcc AGGRE0_NOC_GDSC>; compatible = "simple-pm-bus"; @@ -1349,6 +1377,66 @@ }; }; + slimbam:dma@9184000 + { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0x9184000 0x32000>; + num-channels = <31>; + interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim@91c0000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x91c0000 0x2C000>; + reg-names = "ctrl"; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&slimbam 3>, <&slimbam 4>, + <&slimbam 5>, <&slimbam 6>; + dma-names = "rx", "tx", "tx2", "rx2"; + #address-cells = <1>; + #size-cells = <0>; + ngd@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + + tasha_ifd: tas-ifd { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1{ + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + compatible = "slim217,1a0"; + reg = <1 0>; + + interrupt-parent = <&msmgpio>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + reset-gpios = <&msmgpio 64 0>; + + slim-ifc-dev = <&tasha_ifd>; + + vdd-buck-supply = <&pm8994_s4>; + vdd-buck-sido-supply = <&pm8994_s4>; + vdd-tx-supply = <&pm8994_s4>; + vdd-rx-supply = <&pm8994_s4>; + vdd-io-supply = <&pm8994_s4>; + + #sound-dai-cells = <1>; + }; + }; + }; + gpu@b00000 { compatible = "qcom,adreno-530.2", "qcom,adreno"; #stream-id-cells = <16>; @@ -1507,6 +1595,7 @@ phys = <&hdmi_phy>; phy-names = "hdmi_phy"; + #sound-dai-cells = <1>; ports { #address-cells = <1>; @@ -1545,6 +1634,9 @@ }; }; + sound: sound { + }; + adsp-pil { compatible = "qcom,msm8996-adsp-pil"; @@ -1571,6 +1663,54 @@ mboxes = <&apcs_glb 8>; qcom,smd-edge = <1>; qcom,remote-pid = <2>; + #address-cells = <1>; + #size-cells = <0>; + apr { + power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; + compatible = "qcom,apr-v2"; + qcom,smd-channels = "apr_audio_svc"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + q6core { + reg = ; + compatible = "qcom,q6core"; + }; + + q6afe: q6afe { + compatible = "qcom,q6afe"; + reg = ; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + hdmi@1 { + reg = <1>; + }; + }; + }; + + q6asm: q6asm { + compatible = "qcom,q6asm"; + reg = ; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #sound-dai-cells = <1>; + iommus = <&lpass_q6_smmu 1>; + }; + }; + + q6adm: q6adm { + compatible = "qcom,q6adm"; + reg = ; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; }; };