From patchwork Wed Jan 30 18:50:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 157081 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6286338jaa; Wed, 30 Jan 2019 10:50:46 -0800 (PST) X-Google-Smtp-Source: ALg8bN5rIcEZVh3tYk5b3ooQpTTps0/yfPTJwiiPMpiveg/EmaBmSWvuBsRKJrqCVfBu1Y0nbsNe X-Received: by 2002:a63:d208:: with SMTP id a8mr28135181pgg.77.1548874246623; Wed, 30 Jan 2019 10:50:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548874246; cv=none; d=google.com; s=arc-20160816; b=LarYVR/2YM/TmzlkZK9RW0WLK0EalN1NgQ1gx5Ioc3JDkYk3CL1T9+aHTdFge708da dFu3YcKN69OyBWtjED6gYIzlWLWU1cQuXevEwf04KvM7DpnKfBs+KQxfiJ7ZisEiqwo0 DH/GIsxTiyZ6V2ltm+412MGrDL+9rtBW+Xoq2kuz07EC9HQ/fjLW86ahRIvKbay0ozjx Y10aAMg4/PoHaVCz5NNL6mDkh9JfTwKLkTHsAk+OjOE91a1FDvwtzGnmXhgl6zxjQrxt rKQYerPS4LNdv6i6UX1vJLMuRoLoCEX3eXDDhzJQd8JoF2f362oSExvsK2wOpHMqfcO+ d2Pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=b8M0eSUZUgsVMGxbQEiMn7Shg3Ln/ABC8nhad3aEAW8=; b=ev9aa1qCbZvIHIHNGI3XISlFGle392zkZi+RY6sBcnH+T+b5DMGJmUftuPZp+h9ox6 /Lngm04e5+8apPCoX/C1HGmMy91qJLOqF6t36y6ygCIqKYB/KFSWEv6OwtWHOf6+L3XU Jxh+aFx0AuMZA7McOsZErcRj+XaiSgPH6EjRMyXTJf4fmEWBr/BPavr2zG93lOUGCobe Sk9qNrm6JXlBBnWD0EYWQYowEW56MksM+/8f9FW/16vVM0qslHkwvfusZJyF3Q1oUGeI spUK5yuYI3rGpyNKc1wamx5HCPiWfUnemLrzDPJhnL6ijHlbLJAXZW1COI49WSLIc9bV Hs4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dFDxQf+c; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[79.146.83.99]) by smtp.gmail.com with ESMTPSA id a17sm2802575wrs.58.2019.01.30.10.50.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 10:50:40 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, gregkh@linuxfoundation.org, mark.rutland@arm.com, kishon@ti.com, jackp@codeaurora.org, andy.gross@linaro.org, swboyd@chromium.org Cc: shawn.guo@linaro.org, vkoul@kernel.org, khasim.mohammed@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Date: Wed, 30 Jan 2019 19:50:30 +0100 Message-Id: <20190130185031.24798-2-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190130185031.24798-1-jorge.ramirez-ortiz@linaro.org> References: <20190130185031.24798-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Binding description for Qualcomm's 1.0.0 SuperSpeed phy controller embedded in QCS404. Based on Sriharsha Allenki's original definitions. Signed-off-by: Jorge Ramirez-Ortiz --- .../bindings/usb/qcom,usb-ssphy.txt | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt new file mode 100644 index 000000000000..83748a07d665 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt @@ -0,0 +1,74 @@ +Qualcomm Synopsys 1.0.0 SS phy controller +=========================================== + +Qualcomm 1.0.0 SS phy controller supports SuperSpeed USB connectivity on +some Qualcomm platforms. + +Required properties: + +- compatible: + Value type: + Definition: Should contain "qcom,usb-ssphy". + +- reg: + Value type: + Definition: USB PHY base address and length of the register map. + +- #phy-cells: + Value type: + Definition: Should be 0. See phy/phy-bindings.txt for details. + +- clocks: + Value type: + Definition: See clock-bindings.txt section "consumers". List of + three clock specifiers for reference, phy core and + pipe clocks. + +- clock-names: + Value type: + Definition: Names of the clocks in 1-1 correspondence with the "clocks" + property. Must contain "ref", "phy" and "pipe". + +- vdd-supply: + Value type: + Definition: phandle to the regulator VDD supply node. + +- vdda1p8-supply: + Value type: + Definition: phandle to the regulator 1.8V supply node. + + +Optional child nodes: + +- vbus-supply: + Value type: + Definition: phandle to the VBUS supply node. + +- resets: + Value type: + Definition: See reset.txt section "consumers". PHY reset specifiers + for phy core and COR resets. + +- reset-names: + Value type: + Definition: Names of the resets in 1-1 correspondence with the "resets" + property. Must contain "com" and "phy" if the property is + specified. + +Example: + +usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + vbus-supply = <&usb3_vbus_reg>; +}; From patchwork Wed Jan 30 18:50:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 157082 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6286385jaa; Wed, 30 Jan 2019 10:50:49 -0800 (PST) X-Google-Smtp-Source: AHgI3IZAHHLFIx1xnDIZ+V6Ol/eBMgN1X5jnXMsQLuEG26HaqKBwHXdBu762y0oqvRgLVeteG5QR X-Received: by 2002:a62:22c9:: with SMTP id p70mr3168238pfj.114.1548874249214; Wed, 30 Jan 2019 10:50:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548874249; cv=none; d=google.com; s=arc-20160816; b=OiWoCIXHKgfy6t13cabAbB3d7LwIcjWy/r4c7Ef3UaxEle5nBOjFsAtxiOChU2RJGD jUKgl2SA7fTUUqVxHSuxSTnp52S7i0r99eGzuDu9OIlmk73KW1QfpkCU6ISy1vpUHC2q W7S93nSC9WD7SAOfHu5Yd4q9GnGMiC1yfTZEk0XO8752FnIICqGtfXJPO5UxhgRQdLbk FYPpJ9+fNDP4OoMu3xufdaeQm55FLQ8YJCBttRQLipy+IeUxzQoIGS7wt06UEmAMnhrg vbJjRYt9fX6gPVRMT2e5LIS3SA7OT/oA+VhE+MpzXC8t+aDzw3CtNvJZWnnKqYPEC5fG hX/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ecUbVsN8uqs8tjjRxYkvRQ9Yo8oPmLrGQCqfZU0F2EQ=; b=0LJTAXEP74xlZL4lZBmQ7l1PPRRBcC+A7jb2d1FBeo56sN7r63e/OaUUU/zTRi3ojk ekEMSAJCShFp0axqjaqrrJQxxq42SEOGWBJSuyarYjDWGv/VGSuVi4T4zwZopRi4eFHL GzJ5qg+ivpuDDHkoXBZrZu3YcdjpAbNxuVYG+mn0uYjSAw1jnhEAyXppYAjHhgV2GXGV PDR7+2WZvNng8gUYJlI1XPKXnc7Od5Y04xgwUwWENzah13TzshA6UZLrAcOr8WM35Pi/ FQt6SLoPF2avq623mHeqtw6zhFowaLw7EPdJmz9BUGLum7ltpIlRV2qFELrkK3g5x6rC COXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OAw6gyHz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[79.146.83.99]) by smtp.gmail.com with ESMTPSA id a17sm2802575wrs.58.2019.01.30.10.50.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 10:50:41 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, gregkh@linuxfoundation.org, mark.rutland@arm.com, kishon@ti.com, jackp@codeaurora.org, andy.gross@linaro.org, swboyd@chromium.org Cc: shawn.guo@linaro.org, vkoul@kernel.org, khasim.mohammed@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] phy: qualcomm: usb: Add SuperSpeed PHY driver Date: Wed, 30 Jan 2019 19:50:31 +0100 Message-Id: <20190130185031.24798-3-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190130185031.24798-1-jorge.ramirez-ortiz@linaro.org> References: <20190130185031.24798-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Controls Qualcomm's SS phy 1.0.0 implemented in the QCS404 and some other Qualcomm platforms. Based on Sriharsha Allenki's original code. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/phy/qualcomm/Kconfig | 11 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-usb-ss.c | 328 +++++++++++++++++++++++++ 3 files changed, 340 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c -- 2.20.1 diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 32f7d34eb784..a8dc550d25fb 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -82,3 +82,14 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_USB_SS + tristate "Qualcomm USB SS PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Super-Speed USB transceiver on Qualcomm + chips. This driver supports the PHY which uses the QSCRATCH-based + register set for its control sequences, normally paired with newer + DWC3-based Super-Speed controllers on Qualcomm SoCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index c56efd3af205..d594d532d137 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c new file mode 100644 index 000000000000..9e5f4fd9c3a5 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_CTRL0 0x6C +#define PHY_CTRL1 0x70 +#define PHY_CTRL2 0x74 +#define PHY_CTRL4 0x7C + +/* PHY_CTRL bits */ +#define REF_PHY_EN BIT(0) +#define LANE0_PWR_ON BIT(2) +#define SWI_PCS_CLK_SEL BIT(4) +#define TST_PWR_DOWN BIT(4) +#define PHY_RESET BIT(7) + +#define NUM_BULK_CLKS 3 +#define NUM_BULK_REGS 2 + +struct ssphy_priv { + void __iomem *base; + struct device *dev; + struct reset_control *reset_com; + struct reset_control *reset_phy; + struct regulator_bulk_data regs[NUM_BULK_REGS]; + struct clk_bulk_data clks[NUM_BULK_CLKS]; + /* optional vbus regulator */ + struct vbus_regulator { + struct regulator *consumer; + bool voted; /* regulator balancing: extcon controlled voltage */ + } vbus; + enum phy_mode mode; +}; + +static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val) +{ + writel((readl(addr) & ~mask) | val, addr); +} + +static inline int qcom_ssphy_vbus_enable(struct vbus_regulator *vbus) +{ + struct regulator *consumer = vbus->consumer; + int ret; + + if (vbus->voted || !consumer) + return 0; + + ret = regulator_enable(consumer); + if (!ret) { + /* use count only increments on success */ + vbus->voted = true; + } + + return ret; +} + +static inline int qcom_ssphy_vbus_disable(struct vbus_regulator *vbus) +{ + struct regulator *consumer = vbus->consumer; + + if (!vbus->voted || !consumer) + return 0; + + vbus->voted = false; + + return regulator_disable(consumer); +} + +static int qcom_ssphy_vbus_ctrl(struct vbus_regulator *vbus, enum phy_mode mode) +{ + if (mode == PHY_MODE_INVALID) + return 0; + + /* gadget attached */ + if (mode == PHY_MODE_USB_HOST) + return qcom_ssphy_vbus_enable(vbus); + + /* USB_DEVICE: gadget removed: enable detection */ + return qcom_ssphy_vbus_disable(vbus); +} + +static int qcom_ssphy_do_reset(struct ssphy_priv *priv) +{ + int ret; + + if (!priv->reset_com) { + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, + PHY_RESET); + usleep_range(10, 20); + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0); + } else { + ret = reset_control_assert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to assert reset com\n"); + return ret; + } + + ret = reset_control_assert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to assert reset phy\n"); + return ret; + } + + usleep_range(10, 20); + + ret = reset_control_deassert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset com\n"); + return ret; + } + + ret = reset_control_deassert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset phy\n"); + return ret; + } + } + + return 0; +} + +static int qcom_ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks); + if (ret) + goto err_disable_regulator; + + /* depending on the extcon reported mode, enable or disable vbus */ + ret = qcom_ssphy_vbus_ctrl(&priv->vbus, priv->mode); + if (ret) + goto err_disable_clock; + + ret = qcom_ssphy_do_reset(priv); + if (ret) + goto err_disable_vbus; + + writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); + + return 0; + +err_disable_vbus: + qcom_ssphy_vbus_disable(&priv->vbus); +err_disable_clock: + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); +err_disable_regulator: + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + + return ret; +} + +static int qcom_ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); + + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + qcom_ssphy_vbus_disable(&priv->vbus); + + return 0; +} + +static int qcom_ssphy_init_clock(struct ssphy_priv *priv) +{ + priv->clks[0].id = "ref"; + priv->clks[1].id = "phy"; + priv->clks[2].id = "pipe"; + + return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks); +} + +static int qcom_ssphy_init_regulator(struct ssphy_priv *priv) +{ + int ret; + + priv->regs[0].supply = "vdd"; + priv->regs[1].supply = "vdda1p8"; + ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs); + if (ret) + return ret; + + priv->vbus.voted = false; + priv->vbus.consumer = devm_regulator_get_optional(priv->dev, "vbus"); + if (IS_ERR(priv->vbus.consumer)) { + if (PTR_ERR(priv->vbus.consumer) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + /* regulator_get_optional does not return NULL if not found */ + priv->vbus.consumer = NULL; + } + + return 0; +} + +static int qcom_ssphy_init_reset(struct ssphy_priv *priv) +{ + priv->reset_com = devm_reset_control_get_optional(priv->dev, "com"); + if (IS_ERR(priv->reset_com)) { + dev_err(priv->dev, "Failed to get reset control com\n"); + return PTR_ERR(priv->reset_com); + } + + if (priv->reset_com) { + /* if reset_com is present, reset_phy is no longer optional */ + priv->reset_phy = devm_reset_control_get(priv->dev, "phy"); + if (IS_ERR(priv->reset_phy)) { + dev_err(priv->dev, "Failed to get reset control phy\n"); + return PTR_ERR(priv->reset_phy); + } + } + + return 0; +} + +static int qcom_ssphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + if (!priv->vbus.consumer) + return 0; + + if (mode != PHY_MODE_USB_HOST && mode != PHY_MODE_USB_DEVICE) + return -EINVAL; + + priv->mode = mode; + dev_dbg(priv->dev, "mode %d", mode); + + return qcom_ssphy_vbus_ctrl(&priv->vbus, priv->mode); +} + +static const struct phy_ops qcom_ssphy_ops = { + .set_mode = qcom_ssphy_set_mode, + .power_off = qcom_ssphy_power_off, + .power_on = qcom_ssphy_power_on, + .owner = THIS_MODULE, +}; + +static int qcom_ssphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct ssphy_priv *priv; + struct resource *res; + struct phy *phy; + int ret; + + priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->mode = PHY_MODE_INVALID; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = qcom_ssphy_init_clock(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_reset(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_regulator(priv); + if (ret) + return ret; + + phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create the SS phy\n"); + return PTR_ERR(phy); + } + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id qcom_ssphy_match[] = { + { .compatible = "qcom,usb-ssphy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ssphy_match); + +static struct platform_driver qcom_ssphy_driver = { + .probe = qcom_ssphy_probe, + .driver = { + .name = "qcom_usb_ssphy", + .of_match_table = qcom_ssphy_match, + }, +}; +module_platform_driver(qcom_ssphy_driver); + +MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver"); +MODULE_LICENSE("GPL v2");