From patchwork Fri Aug 5 16:50:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C590C25B08 for ; Fri, 5 Aug 2022 16:50:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240906AbiHEQut (ORCPT ); Fri, 5 Aug 2022 12:50:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236448AbiHEQur (ORCPT ); Fri, 5 Aug 2022 12:50:47 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7B431C125 for ; Fri, 5 Aug 2022 09:50:45 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id n20-20020a05600c3b9400b003a4f2261a7eso1524368wms.2 for ; Fri, 05 Aug 2022 09:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=9JYdpth5RmfS3EJypo1rTclGHef1NaLLFmN2AxjOh40=; b=lHYMIHAF31vYCzNvEQ97uO10D2+YE23yHf+ECBSCU17szTlwH1Hkvz0vwYZKFZnkOF +4BFhC8tSMH+Lt42TJh1yUXKzj+XqUP6tbZ6rqzuxqLTOlP1LE8XQg29icJ2gzRGD9iq Ll7ZCVeNf1liG0SLhLq3svWLHbIuxDW11jHwwuqHlb3AKtpR59mKeYyCa7HVzuhjyEiJ FPJ/9pq3B2tM6IVu2Mr7+JvH9+DHIrmyXdrGmfIZmJrUpj36CbQajB4o6hlxIUsy2FoW 74HBtRQeyZH/3D5AnaY7a3vhrbXVpkXB9mX9PoE0zVllx+oCz8rv0a9kGGNmEPNdH364 TBjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=9JYdpth5RmfS3EJypo1rTclGHef1NaLLFmN2AxjOh40=; b=SYcLBqYrkkyQz2Nn+Yg0iTQdtj26WvuXEhphXXj13oK7dz+dRu4sWm+/lIkwWhJmMt VAS3SwnJnKNChptmlbOk6YZsc9MEJsX/YPFlOPq9nXGFyz96e5YuCM0iNHd1d0vzjvpH oawOvCxxbOw84FYUke8PKwSJWCduM4tABBbSGVLjVzqe9kTU/PwAQvcz3oY3Y0qCX16m EN4fbZEEUEVJPQMWjn5Inhb1L3ztJmTa4KrjAg6Yb0JXO1Esv2LVymiDturs2bLohr4r i43vH53Pqmo3/XapZGPcQBTOxlVn8fCkvGGp2E7LyBhNjJXMeav9qsSUAqb3zkO5uY98 vjfQ== X-Gm-Message-State: ACgBeo0pBM3x+dHQFlr7k4gz2x95h4sJQPtyttxXKdBgOBzphZ4bza2w WgQCDfPPjAF7D7Y+Ssbb+Wuv8g== X-Google-Smtp-Source: AA6agR4Mi0UPWTL1T47WzzTxVOC58jhj7r9VoEL7DRotfy/iJGjyA/sHbaZ+DJT6H/TU7vAhG9O3Xw== X-Received: by 2002:a05:600c:22c1:b0:3a3:170a:7ae1 with SMTP id 1-20020a05600c22c100b003a3170a7ae1mr10077337wmg.192.1659718244364; Fri, 05 Aug 2022 09:50:44 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id h28-20020a05600c2cbc00b003a4f08495b7sm11325374wmc.34.2022.08.05.09.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:50:44 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha --subject-prefix=PATCH v3 , Ben Dooks Subject: [PATCH 1/8] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm-dw-apb-timers-pwm2 Date: Fri, 5 Aug 2022 17:50:26 +0100 Message-Id: <20220805165033.140958-2-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220805165033.140958-1-ben.dooks@sifive.com> References: <20220805165033.140958-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the bindings for Synopsys' DesignWare PWM block as we will be adding DT/platform support to the Linux driver soon. Signed-off-by: Ben Dooks --- v3: - add description and example - merge the snps,pwm-number into this patch - rename snps,pwm to snps,dw-apb-timers-pwm2 v2: - fix #pwm-cells to be 3 - fix indentation and ordering issues --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..a81f2c2e485c --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-tiners-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + +required: + - "#pwm-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + + +examples: + - | + pwm: pwm@180000 { + #pwm-cells = <3>; + compatible = "snps,dw-apb-timers-pwm2"; + reg = <0x180000 0x200>; + clocks = <&bus &timer>; + clock-names = "bus", "timer"; + }; From patchwork Fri Aug 5 16:50:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3654BC25B0D for ; Fri, 5 Aug 2022 16:50:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240928AbiHEQut (ORCPT ); Fri, 5 Aug 2022 12:50:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239415AbiHEQur (ORCPT ); Fri, 5 Aug 2022 12:50:47 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B1191BEA5 for ; Fri, 5 Aug 2022 09:50:46 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id z12so3844597wrs.9 for ; Fri, 05 Aug 2022 09:50:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=BWgOaWILsYq3ZBv0suGifNsfC2RNDB9yng6qUNHLD2A72Z8UNlShi8mSGKRMUhqsIS ANwKPPkJr1qBoG5gzFp7/dbql53OzOY3rJCUPu0kmgNnoX8TBwRPwI41gsZaH7SNFdRr FEM8YoCzDYRYdNGS5ao/oeN4tr3ipUYJoISGPc215xJvVGnltoFdX2wIgStnAdqc+VME uEl9traG294lJCrT4DIKtF/p7u52k7qErwMgLPGIFdG1lEi0OoEtOgz+zko45xnpAO8g RuXrfuMOSRYqE1QqDn6rZztuuXu7wAcqVzNPQVs60UZmIRTVTqyxDyyNmgEWtdSWycrq 3B/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=yo7u/jLwPzy+03zch0drdNGpiefDf2EN2ROHfyb27tVo4YYgtbU/o+4mTqdiAHf8FC fsAFnUIsc1Q0yWFQn8TsUz8CBaqG3Fl/xSFraVBPGDKZy/oZ8/20Qs6L1hCfIeTvd2AG jrlr6Eksylt2KP4bQxSNZqd/lZbJaMEbczpDz+vmKwNgA4RKz0j70LapzPYgMfPg2EUY 2AntLp6jfvKciPbUDhPtwBeOW4exGutUTDZ9JIapEN5Qis7ibyVPeKvDJoifRW6RnX1k agUoaZlSUmBOqpTtz4of2++8y1/5I7nnR/AfWD3w6LhY2nNR0mDsc0TQIJaZU470azv7 rtMQ== X-Gm-Message-State: ACgBeo0RRnYP7aRYJUn7sa3ZWzwlYgkahJcjmLpsZz2HP4SNoDv6FGG1 eVNAsiLNAD5R+Uke33keiXa97w== X-Google-Smtp-Source: AA6agR43TeIxmPhDHtFF9FnHQf/9/Wzpvq74xTkzRALOkCM6ipkcvArjUG7CwoF9zR+WV3poGVebpw== X-Received: by 2002:a5d:47a8:0:b0:221:7c03:f60 with SMTP id 8-20020a5d47a8000000b002217c030f60mr1331655wrb.4.1659718245049; Fri, 05 Aug 2022 09:50:45 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id h28-20020a05600c2cbc00b003a4f08495b7sm11325374wmc.34.2022.08.05.09.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:50:44 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha --subject-prefix=PATCH v3 , Ben Dooks Subject: [PATCH 2/8] pwm: change &pci->dev to dev in probe Date: Fri, 5 Aug 2022 17:50:27 +0100 Message-Id: <20220805165033.140958-3-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220805165033.140958-1-ben.dooks@sifive.com> References: <20220805165033.140958-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dwc_pwm_probe() assignes dev to be &pci->dev but then uses &pci->dev throughout the function. Change these all to the be 'dev' variable to make lines shorter. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 7568300bb11e..c706ef9a7ba1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -202,14 +202,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL); + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; ret = pcim_enable_device(pci); if (ret) { - dev_err(&pci->dev, - "Failed to enable device (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); return ret; } @@ -217,14 +216,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); if (ret) { - dev_err(&pci->dev, - "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); return ret; } dwc->base = pcim_iomap_table(pci)[0]; if (!dwc->base) { - dev_err(&pci->dev, "Base address missing\n"); + dev_err(dev, "Base address missing\n"); return -ENOMEM; } From patchwork Fri Aug 5 16:50:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC983C282E7 for ; Fri, 5 Aug 2022 16:50:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240965AbiHEQuu (ORCPT ); Fri, 5 Aug 2022 12:50:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240858AbiHEQus (ORCPT ); Fri, 5 Aug 2022 12:50:48 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4151A22B3B for ; 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Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index c706ef9a7ba1..61f11e0a9319 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -196,13 +196,29 @@ static const struct pwm_ops dwc_pwm_ops = { .owner = THIS_MODULE, }; +static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev = dev; + dwc->chip.ops = &dwc_pwm_ops; + dwc->chip.npwm = DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} + static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) { struct device *dev = &pci->dev; struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + dwc = dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; @@ -226,12 +242,6 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - pci_set_drvdata(pci, dwc); - - dwc->chip.dev = dev; - dwc->chip.ops = &dwc_pwm_ops; - dwc->chip.npwm = DWC_TIMERS_TOTAL; - ret = pwmchip_add(&dwc->chip); if (ret) return ret; From patchwork Fri Aug 5 16:50:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEC15C25B0F for ; Fri, 5 Aug 2022 16:50:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240994AbiHEQuv (ORCPT ); Fri, 5 Aug 2022 12:50:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230244AbiHEQut (ORCPT ); Fri, 5 Aug 2022 12:50:49 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23C3224F01 for ; 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Signed-off-by: Ben Dooks Reported-by: kernel test robot Reported-by: kernel test robot --- v3: - changed compatible name --- drivers/pwm/Kconfig | 5 ++-- drivers/pwm/pwm-dwc.c | 53 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..b8717877a524 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,9 +176,10 @@ config PWM_CROS_EC config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI + depends on PCI || OF help - PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + PWM driver for Synopsys DWC PWM Controller attached to either a + PCI or platform bus. To compile this driver as a module, choose M here: the module will be called pwm-dwc. diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 61f11e0a9319..d5f2df6fee62 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -319,6 +320,58 @@ static struct pci_driver dwc_pwm_driver = { module_pci_driver(dwc_pwm_driver); +#ifdef CONFIG_OF +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwc_pwm *dwc; + int ret; + + dwc = dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + dwc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return dev_err_probe(dev, PTR_ERR(dwc->base), + "failed to map IO\n"); + + ret = pwmchip_add(&dwc->chip); + if (ret) + return ret; + + return 0; +} + +static int dwc_pwm_plat_remove(struct platform_device *pdev) +{ + struct dwc_pwm *dwc = platform_get_drvdata(pdev); + + pwmchip_remove(&dwc->chip); + return 0; +} + +static const struct of_device_id dwc_pwm_dt_ids[] = { + { .compatible = "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver = { + .driver = { + .name = "dwc-pwm", + .of_match_table = dwc_pwm_dt_ids, + }, + .probe = dwc_pwm_plat_probe, + .remove = dwc_pwm_plat_remove, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm"); +#endif /* CONFIG_OF */ + + MODULE_AUTHOR("Felipe Balbi (Intel)"); MODULE_AUTHOR("Jarkko Nikula "); MODULE_AUTHOR("Raymond Tan "); From patchwork Fri Aug 5 16:50:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A976C00140 for ; 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Fri, 05 Aug 2022 09:50:47 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha --subject-prefix=PATCH v3 , Ben Dooks Subject: [PATCH 5/8] pwm: dwc: allow driver to be built with COMPILE_TEST Date: Fri, 5 Aug 2022 17:50:30 +0100 Message-Id: <20220805165033.140958-6-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220805165033.140958-1-ben.dooks@sifive.com> References: <20220805165033.140958-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow dwc driver to be built with COMPILE_TEST should allow better coverage when build testing. Signed-off-by: Ben Dooks --- v3: - add HAS_IOMEM depdency for compile testing --- drivers/pwm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index b8717877a524..05718e0faac9 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,7 +176,8 @@ config PWM_CROS_EC config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI || OF + depends on PCI || OF || COMPILE_TEST + depends on HAS_IOMEM help PWM driver for Synopsys DWC PWM Controller attached to either a PCI or platform bus. From patchwork Fri Aug 5 16:50:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2AB3C00140 for ; Fri, 5 Aug 2022 16:50:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241010AbiHEQuy (ORCPT ); Fri, 5 Aug 2022 12:50:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240858AbiHEQuv (ORCPT ); Fri, 5 Aug 2022 12:50:51 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CECD222B3B for ; Fri, 5 Aug 2022 09:50:49 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id c187-20020a1c35c4000000b003a30d88fe8eso4222704wma.2 for ; Fri, 05 Aug 2022 09:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=xtgPxFLwZi/ozmv/dKYJFl8mhw/7WaaIbNbRSLG6I4E=; b=P7qv2wQrbujU2+Ct2z5eGGgnDRDKYBtYxyKk/LhObJLXBCxZpQ8PVxTvsLL2OciOnw PjM4AZZf0umyZueaHTX0UwY+OAOXg9VYwiPlNvDHPbijtykL2f+scdlH1RkBiQwgl1DB ycKUbNDcAM1Q6iGKkOV6BAqF4nh3zaR2FoDzWqWSNgMdRhpGZDtpcpc9f5WCx8C+dWKt 0tFPU13DOSInoQiKqrfCoNqUTL2r1FOLdY3AitJdocgumVn/gpT91ljJOq1dCvtMJmTN Tzt+Z4C7IDSRMPLptBcx8BNr39tB/8JCmFRvzC1KBE0do2hHPf4fiLUlaaq0uni5BEqB n3Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=xtgPxFLwZi/ozmv/dKYJFl8mhw/7WaaIbNbRSLG6I4E=; b=HBE1MYy0HlzTM7vNHLt2axw+1k64qSfcGdHA6+gLmELqxEgBnQAt2vscEBUIuLYj5Y qo92V2UxZ8JrJMKUsLLZp52ggj2IGGhO4UhY/BigaaTOiWB6qM5eQmfobu6bqBNE+/j6 jlwF4F9Tc+fRyg+7U+8O2Ql/TxWn4Q/TGu3SGEzff0H9f2heOJTuHlmuJ6G9LJfpA0lr dtaHaM+S5ePF/8+NqgXZ6Fr4Fvcem/4sVXXLE/VqcNN/4UikSwyS/4tszE+z6VAqnVh6 /k8CdvxR7j6x7nDVEw55jD/lqIoz34mK4Y5em5kM+3fDEBPvN/Q1Bik3gSfJYtcyAK1q lUGg== X-Gm-Message-State: ACgBeo2igmg4lQFUFuBnGBBpVuKPkKHBHylKx9BPSM+nki2Gefcu162A LPJSIDI8tz5qoSzQ3m8xx8uTSQ== X-Google-Smtp-Source: AA6agR7ARuXIJSEwDQX/+7fSmp2PM7Ulf7L2hECWM0MxrfrcAEn/nH3j6wZb0OVTkKTZzU3gdyCzHg== X-Received: by 2002:a05:600c:1f13:b0:3a3:3f0d:d9d4 with SMTP id bd19-20020a05600c1f1300b003a33f0dd9d4mr10369535wmb.4.1659718248235; Fri, 05 Aug 2022 09:50:48 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id h28-20020a05600c2cbc00b003a4f08495b7sm11325374wmc.34.2022.08.05.09.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:50:47 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha --subject-prefix=PATCH v3 , Ben Dooks Subject: [PATCH 6/8] pwm: dwc: add timer clock Date: Fri, 5 Aug 2022 17:50:31 +0100 Message-Id: <20220805165033.140958-7-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220805165033.140958-1-ben.dooks@sifive.com> References: <20220805165033.140958-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks --- v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index d5f2df6fee62..5c319d0e3d52 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -35,7 +36,6 @@ #define DWC_TIMERS_COMP_VERSION 0xac #define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 /* Timer Control Register */ #define DWC_TIM_CTRL_EN BIT(0) @@ -54,6 +54,8 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + struct clk *clk; + unsigned int clk_ns; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) @@ -96,13 +98,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -177,12 +179,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty += 1; - duty *= DWC_CLK_PERIOD_NS; + duty *= dwc->clk_ns; state->duty_cycle = duty; period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period += 1; - period *= DWC_CLK_PERIOD_NS; + period *= dwc->clk_ns; period += duty; state->period = period; @@ -205,6 +207,7 @@ static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; + dwc->clk_ns = 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; @@ -336,6 +339,14 @@ static int dwc_pwm_plat_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(dwc->base), "failed to map IO\n"); + dwc->clk = devm_clk_get(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + clk_prepare_enable(dwc->clk); + dwc->clk_ns = 1000000000 / clk_get_rate(dwc->clk); + ret = pwmchip_add(&dwc->chip); if (ret) return ret; @@ -347,6 +358,7 @@ static int dwc_pwm_plat_remove(struct platform_device *pdev) { struct dwc_pwm *dwc = platform_get_drvdata(pdev); + clk_disable_unprepare(dwc->clk); pwmchip_remove(&dwc->chip); return 0; } From patchwork Fri Aug 5 16:50:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F4F9C00140 for ; Fri, 5 Aug 2022 16:51:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241150AbiHEQvE (ORCPT ); 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Fri, 05 Aug 2022 09:50:48 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha --subject-prefix=PATCH v3 , Ben Dooks Subject: [PATCH 7/8] pwm: dwc: add snps,pwm-number to limit pwm count Date: Fri, 5 Aug 2022 17:50:32 +0100 Message-Id: <20220805165033.140958-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220805165033.140958-1-ben.dooks@sifive.com> References: <20220805165033.140958-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add snps,pwm-number property to indicate if the block does not have all 8 of the PWM blocks. Not sure if this should be a general PWM property consider optional for all PWM types, so have added a specific one here (there is only one other controller with a property for PWM count at the moment) Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 5c319d0e3d52..5edfb8f8acbf 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -328,12 +328,20 @@ static int dwc_pwm_plat_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct dwc_pwm *dwc; + u32 nr_pwm; int ret; dwc = dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs specified (%d)\n", nr_pwm); + else + dwc->chip.npwm = nr_pwm; + } + dwc->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dwc->base)) return dev_err_probe(dev, PTR_ERR(dwc->base), From patchwork Fri Aug 5 16:50:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 595601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A185BC00140 for ; Fri, 5 Aug 2022 16:51:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241215AbiHEQvN (ORCPT ); Fri, 5 Aug 2022 12:51:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241046AbiHEQuy (ORCPT ); Fri, 5 Aug 2022 12:50:54 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F4176D554 for ; Fri, 5 Aug 2022 09:50:51 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id a18-20020a05600c349200b003a30de68697so4220787wmq.0 for ; Fri, 05 Aug 2022 09:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=yBJp61T732NhGvuYuS8ssmWnNYi45D7jFrvNVeym7no=; b=LUgQeOOwftQJP0tKGwJY1ZErHDgZUvn4JHdWsZOolJMRDJPF33KXTjxkBQjFIU0GQt YfEAVlMNTTy2rCodHHTHKM4yTERMMIimuLasIyIRLPe69kjbnSvZlV0qVFiR+oMnEKE5 eM/NYISQApci32tIh1y2eBx50mc8+03wgBXPGkWtW8+zqmwgshsy+8CQMUXtS+ChE9Vn IyOE5RiHl0iEsfROzcLquyDInSs2SVs6oOT8OdFCzMzEU4085GX6Wf5ci9eACkF4ZUBK i3hpu2/Y0JFdLpwd0x+hvDfPGl9S9S/BhS7oyqaZExY/jnlhHxROpw+JkyCejYVww/Ik dL/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=yBJp61T732NhGvuYuS8ssmWnNYi45D7jFrvNVeym7no=; b=YGti99GDohEa0NjqmlE7C8wpuEbRF3rPzh9njCC4dMXlzOdzZpVzhgliNA6q2USVgW 9OkRCvgllX/VoIPrItXV2u/ZmQLhYAAwUWzqNrI9kw55JGCWeQyCd+r2IR8k5M6esEew p79IBNozo13WDJ1h6Rb9ZkTSdaNVZU/TWodskroexTAe/NtnlB5EoRhiVz4inPDZDJz7 H8mSO3kzouo4J+41zmQokNCCZrUDVsS2xXPd+UTX33GVJ96hVrSytNrp5B4NgFpEokx3 LFERTw3JapSJVrCMcSm9MicZp01j/nc5vFWzLTxV1RkKj/4DntO5W1f1WiRxzP321j7r WWsQ== X-Gm-Message-State: ACgBeo1dvopsCIT7A7LC9unxuu2rkZbN/XnyAuakMuuHDPNbsm32ZiDu 7a+r8/iKw5hjUrJEMrdErNMZ3yOGhUduZ4mX X-Google-Smtp-Source: AA6agR4PJ6FvfUDry8dDMg/k/gZ2UHnGi7IpK1O00WLhlYJzCF6UAcvJhmmLLVY1R3TAfAXGSTClqw== X-Received: by 2002:a05:600c:a18f:b0:3a5:174e:d650 with SMTP id id15-20020a05600ca18f00b003a5174ed650mr3463797wmb.47.1659718249542; Fri, 05 Aug 2022 09:50:49 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id h28-20020a05600c2cbc00b003a4f08495b7sm11325374wmc.34.2022.08.05.09.50.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 09:50:49 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha --subject-prefix=PATCH v3 , Ben Dooks Subject: [PATCH 8/8] pwm: dwc: add PWM bit unset in get_state call Date: Fri, 5 Aug 2022 17:50:33 +0100 Message-Id: <20220805165033.140958-9-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220805165033.140958-1-ben.dooks@sifive.com> References: <20220805165033.140958-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 5edfb8f8acbf..49e666be7afd 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -171,23 +171,35 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, { struct dwc_pwm *dwc = to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; pm_runtime_get_sync(chip->dev); - state->enabled = !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty += 1; - duty *= dwc->clk_ns; - state->duty_cycle = duty; + state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); - period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period += 1; - period *= dwc->clk_ns; - period += duty; - state->period = period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty = ld; + duty += 1; + duty *= dwc->clk_ns; + + period = ld2; + period += 1; + period *= dwc->clk_ns; + period += duty; + } else { + duty = (ld + 1) * dwc->clk_ns; + period = duty * 2; + } + state->period = period; + state->duty_cycle = duty; state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev);