From patchwork Sat Aug 20 19:57:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 598843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51965C32772 for ; Sat, 20 Aug 2022 19:58:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231336AbiHTT6Z (ORCPT ); Sat, 20 Aug 2022 15:58:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231346AbiHTT6R (ORCPT ); Sat, 20 Aug 2022 15:58:17 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 449ABD13C for ; Sat, 20 Aug 2022 12:58:16 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id y15so3067778pfr.9 for ; Sat, 20 Aug 2022 12:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=0zartni4WWKXkld6e1WeGJpYpeF1RS1wwjz0ltPgHus=; b=U95uH/zNEa/TQ4D+jYVIJdvJ8GymR00qdKpot0h8As14wkzSPTEvQEUOOjDDmW6ZRV duFLC6eaowNl1KDOXwMk4uTMxZ5UbDsurrvbsi/DpNewV779jBdMR+RH//XZYFSY5Vdj XFjWhC6fpzKWPk0ZP7eJXs6Neq/i2NwlLlzaj/uhjxIjFIJgaZkHFDM6zvL8Kl3SFe4S Nq/wNxJb9ivY6SfmkvdXFohdpjnwjxFksyvJU4/a4q6mzgyWfb0rfswD451bxN4dCh6Q AZgJDSjJszuIc0m7RqxY1qdt+nbACAVcuLvJNTtt1wIFOz2OahFXCWEv5L2xlp3w+FW2 upLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=0zartni4WWKXkld6e1WeGJpYpeF1RS1wwjz0ltPgHus=; b=1l9OEFkKxWMzXadz9odwKqC21rM2XQxbZLp8cxomRS7o+ykPoLA+3vUxkC2EM5oYj6 2HYF/z4pgRgDMblfpNtnodTO8B/IeG9CDRqI2TV3T44amiNHRSYoQhW7wY1l3C7Z1lTJ bLG5Yurkd4h4cNfGZ+gPhkoiLdp/DDMbdOldktP8F4ivkKwTGzNCg6CQvtbsCL3QBPeH vjkmvvQ5T6iQR5S6gwHD6YdfnhYpaLLFetypeUp1Scl/ybNAoZakbcQ3TGeTA1wROEfc ejoEpMFZ8ic/ZQ4F2M38cD0OzCDusNNUXpuroV8lGadabtjk1Rn+DAeN4NfCY1Eb4qGf 2Uwg== X-Gm-Message-State: ACgBeo2SV1MKeQZLL+MHsvqeqjalPH0tOUhHdbrISWZsN4ckmNofFM2t Nv6Kk7Nquh4/DwyHWRWGskD7TQ== X-Google-Smtp-Source: AA6agR7EpSBOnin4/WKnF0P/ZYB5n/9+bKy1kJfNuoM4SGkFRNSu7jH2CbMw7hR+06qrxYA1QEJOzg== X-Received: by 2002:a05:6a00:21c2:b0:52b:ff44:6680 with SMTP id t2-20020a056a0021c200b0052bff446680mr13809251pfj.57.1661025495792; Sat, 20 Aug 2022 12:58:15 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:15 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 01/17] dt-bindings: arm: add AMD Pensando boards Date: Sat, 20 Aug 2022 12:57:34 -0700 Message-Id: <20220820195750.70861-2-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Document the compatible for AMD Pensando Elba SoC boards. Signed-off-by: Brad Larson --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... From patchwork Sat Aug 20 19:57:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 599069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB84EC32796 for ; Sat, 20 Aug 2022 19:58:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229986AbiHTT60 (ORCPT ); Sat, 20 Aug 2022 15:58:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231398AbiHTT6T (ORCPT ); Sat, 20 Aug 2022 15:58:19 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF09915FE9 for ; Sat, 20 Aug 2022 12:58:18 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id v23so1476283plo.9 for ; Sat, 20 Aug 2022 12:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=NTXAxyQL3waGEJkz3JFJl11ykh+V7CnflPyyCrkRmVo=; b=aDa+MkMjVsjqpzMdLGR6xZaO83PwMwIyrZk1GxVo53E9S8vjB9rlObTewiew3FvTg9 PsmXG+TvLB+kgfj/mcJ2XaywU1rNXrEAUj3nPhpqmZ5YSLfTolGBVp2+oxHN3xxXv0V6 QyCuqJhpn2pRir62TbQzOyzsahTjKTvVsI2BqP3rWHEB8nifJPHLG1boGRd10ty1mUKH iqj6LJQH+pu00fdELeJ+itJKXkM2mmWwl3xm2HTPAgoHIacTVprXbH+2jD1X+/PhvKv1 1c207Zornyjs8wquci/ZHDxlHF5mWGFuKOFM5SSeE5m7llxoQKCNdgE0dsrSJ+oasP6n Xz6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=NTXAxyQL3waGEJkz3JFJl11ykh+V7CnflPyyCrkRmVo=; b=UzKfywt6UhytZXRMamveJ5gz7OYlD6Ck5yzKSXivk8zGcHg6SWJhQkf+dQe3mbauuv nHQ/vUejElAH++KlQmZAJb0R9PymH0v6L4ViHmn4VvzL8vakCX8pitB8olP73T5nIoHH MHi9RaAM07bkm2LdtFDEnovsod/F4xPINdy2WpF9JUnUvwbVPJfSE/i7Mtd+W4WMEhFf CqanroGlG8HGhtd/dUONoVBvEfOfcCgyLevMe4zxIfTVFeLsDTnQ5RnFrNoKeN7HG1XX /xZS5xvsACKG6xgvUYQM0SQFyLTKvmpLeqWltD3RJLc54F8aQ4fiBX8aOHPL8DXUh5Co cvQg== X-Gm-Message-State: ACgBeo2+vZ6nUBz8VTbZNHhkeiawEODTV/BS1oDN17WpcdczN7l5AAxz PmFCIDWIWFqss0cYKMUj3Mmgpg== X-Google-Smtp-Source: AA6agR4lIy2KV6bT/mtcoUBCfdxboF9vk9E8rQOlcdA7QKnG74sjDawFROrHf2Z3OgHjdJ4lYC890g== X-Received: by 2002:a17:902:70c7:b0:170:9030:8219 with SMTP id l7-20020a17090270c700b0017090308219mr13177138plt.163.1661025498268; Sat, 20 Aug 2022 12:58:18 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:17 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 02/17] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Date: Sat, 20 Aug 2022 12:57:35 -0700 Message-Id: <20220820195750.70861-3-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index 4207fed62dfe..964b610eeef2 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -17,12 +17,14 @@ properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -118,6 +120,15 @@ required: - interrupts - clocks +if: + properties: + compatible: + const: amd,pensando-elba-sd4hc +then: + properties: + reg: + minItems: 2 + unevaluatedProperties: false examples: From patchwork Sat Aug 20 19:57:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 598842 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5CC8C32793 for ; Sat, 20 Aug 2022 19:58:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231398AbiHTT63 (ORCPT ); Sat, 20 Aug 2022 15:58:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231748AbiHTT6X (ORCPT ); Sat, 20 Aug 2022 15:58:23 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72A7F1C110 for ; Sat, 20 Aug 2022 12:58:21 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id y127so4080577pfy.5 for ; Sat, 20 Aug 2022 12:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=wz9MsUwmI5n+ymksjYC4EkZBI5QAxatLdHbVurA5ZlI=; b=B8EI6enIRiLHMyZoWfn+OOYNPz31hR0ZY++Q94mK6NKM8A3wITa5OvTvgeINH8KgD4 AmuRI/+HTkNFJtsvXt23x2KKRBDeiIDx5CIfhzmS9w3Gme000XD+BSvtAo9hQRwTZUr3 MWC9RLksiznlY89PnUyIuGGUPD/9xLkT1fYwWsb9y7LRZTsm9e/Gj8FQsyut0jLf8CBs Gb/qfpwINSLdJDqNn8WGC988FtkhZKkAep2W+Cw4e3SS/8huflK49+9iiDiLZv9T3164 EHpuw28I0pxqcuqerOIBOA99r0j7RkGTjWSbuqKI1U4ft3fcyU9qJbJVyGY0h4wZqxHi xqtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=wz9MsUwmI5n+ymksjYC4EkZBI5QAxatLdHbVurA5ZlI=; b=5gEkRihX/X8Htg3TLIOB2TKPr6q+mGSDpRWOoDKPy0Kz6asr5RlDXclUQ4mcO/G9Ld eMcdFcD3uRNgFB0nl1/QRjgdY7GuOpF64t9Ju2cTNN/nqf686mKjtcX9dzmW0y+MAPjP e57lRgZRY+Vsi+HbK7DlfQt1esUK5FCfyXcUmbPx8zqzlBKCVxe64sOGAxPsAB1u5iuV FEqxoz9FusaTjUAnkyZGj9JgoRvYMOTwk8nfjRKlWwzx0nL+1QA8ame8rmfki6s9A9KM uRZXn/HbsxN1uD6O4dwi4DGXVdEq8owHNAV8BKMZoSuPuablH7GGbLPADzZpKYarSrI9 SZvA== X-Gm-Message-State: ACgBeo3XIq8wBG8K7IsUPZaQh0zzatpAzB8Ijisa+4ZjagE5cfV6SvaS 5J5u64y/vZda8ZfclWyhL8M6AQ== X-Google-Smtp-Source: AA6agR7hs5dMUXq2LiE7InqSQSJ3w32+PKzInx3oGBczozrPj5Qd2Ax7XXzFuEy4aAGPzi6V/t+b7Q== X-Received: by 2002:a65:4501:0:b0:3fc:4895:283b with SMTP id n1-20020a654501000000b003fc4895283bmr11262902pgq.231.1661025500870; Sat, 20 Aug 2022 12:58:20 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:20 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 03/17] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC Date: Sat, 20 Aug 2022 12:57:36 -0700 Message-Id: <20220820195750.70861-4-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 4707294d8f59..b9e49e90e280 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,23 @@ allOf: required: - power-domains + - if: + properties: + compatible: + enum: + - amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi From patchwork Sat Aug 20 19:57:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 599068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2D80C25B08 for ; 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Sat, 20 Aug 2022 12:58:22 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 04/17] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Date: Sat, 20 Aug 2022 12:57:37 -0700 Message-Id: <20220820195750.70861-5-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson --- .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 37c3c272407d..403d6416f7ac 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,15 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + enum: + - amd,pensando-elba-spi + then: + required: + - amd,pensando-elba-syscon properties: compatible: @@ -75,6 +84,8 @@ properties: - renesas,r9a06g032-spi # RZ/N1D - renesas,r9a06g033-spi # RZ/N1S - const: renesas,rzn1-spi # RZ/N1 + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi reg: minItems: 1 From patchwork Sat Aug 20 19:57:38 2022 Content-Type: text/plain; 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Sat, 20 Aug 2022 12:58:25 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:25 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 05/17] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Date: Sat, 20 Aug 2022 12:57:38 -0700 Message-Id: <20220820195750.70861-6-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add the AMD Pensando Elba SoC system registers compatible. Signed-off-by: Brad Larson --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index c10f0b577268..b6ae68851752 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - amd,pensando-elba-syscon - brcm,cru-clkset - freecom,fsg-cs2-system-controller - hisilicon,dsa-subctrl From patchwork Sat Aug 20 19:57:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 599067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63F21C3F6B0 for ; Sat, 20 Aug 2022 19:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231903AbiHTT6e (ORCPT ); Sat, 20 Aug 2022 15:58:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231965AbiHTT6b (ORCPT ); Sat, 20 Aug 2022 15:58:31 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BBC015FE9 for ; Sat, 20 Aug 2022 12:58:28 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id g8so2868136plq.11 for ; Sat, 20 Aug 2022 12:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=di2SPGU5x1pTiaeM4K+fw8L7yPhLD/oZqXCEZ+r+vdc=; b=Kt3Dgo1jDXx7s0mZOIqmWuvVIfmApyXitJu3xxj8Ufsl5L2t88PxrUvhKRtjtOGMqn 0HTS0DzqdQovD+OK2qgjp9Cn6p5AMCmRsnD5jsCn1EXqTSbRmbHTmVdlxr706KBOV7lZ IDMO6vHu4HcSqlnP9KARqlDfunDglJ+paNmYYFWAxmq6XXrA0kl2uRBSmEXZ4Pwe1tuF 3rtmKPYCv89sKqnOAc51aN7Rj1eZ2nV453xWCszHObWdckDgLilkftxJwINRus2PaIA6 B65DJR/iR8hcPntsfDNStrSpNrbHD7X3mzScjMlsBrY/m+4KutloRN33y7EVvv2cNQzp fM2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=di2SPGU5x1pTiaeM4K+fw8L7yPhLD/oZqXCEZ+r+vdc=; b=xItBDdPGaJy4XwFfd88YoZK3ROOALxZA13ZsaEoEG85KB29Xkuvw1wSX3spWvwIhmw DFNyHBjBFo8t1xgvV4TmTtWVhVvW1glVkWJoO+vNnR30vKs0B6CLTiBkP2NCHtpza4cZ CTAzELJE8UgnVIp9nC36kfNQrLz0aeAsdKMKADaGFN6nVLlGooDrWCqGIC4VS732MZVA yxVzxd0X3GN7/y88mNc8+1hoqsv+7CccvyVK57i67MJmScDWnDk/0OOmNpougrqDIVgj Sy4UDBJO5I0AhXkuCm9U7Zpwy/593jn6D68Uk2VqZHLraEAS6PUOxrT6pYusvQXJVQlC A9tA== X-Gm-Message-State: ACgBeo2aMzfOVRtxt3BxJLA4/fLQcenTRpCTkHyJ3LjTtIeAq/6s1AI+ 8RDsh0FSOQeXhwOm0gubN2vF5A== X-Google-Smtp-Source: AA6agR7i3yPKVE4Kp5uSMKmrbyXdBYlktP2wELeOCMKvIwDlFLhtppJXK5q4nU97XkKr/2FPPx0bUg== X-Received: by 2002:a17:90b:3b47:b0:1fa:d988:c916 with SMTP id ot7-20020a17090b3b4700b001fad988c916mr11885488pjb.240.1661025508471; Sat, 20 Aug 2022 12:58:28 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:27 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Sat, 20 Aug 2022 12:57:39 -0700 Message-Id: <20220820195750.70861-7-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add support for the AMD Pensando Elba SoC System Resource chip using the SPI interface. The Elba SR is a Multi-function Device supporting device register access using CS0, smbus interface for FRU and board peripherals using CS1, dual Lattice I2C masters for transceiver management using CS2, and CS3 for flash access. Signed-off-by: Brad Larson --- .../bindings/mfd/amd,pensando-elbasr.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml new file mode 100644 index 000000000000..ded347c3352c --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/amd,pensando-elbasr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Resource Controller bindings + +description: | + AMD Pensando Elba SoC Resource Controller is a set of + miscellaneous control/status registers accessed on CS0, + a designware i2c master/slave on CS1, a Lattice rd1173 + dual i2c master on CS2, and flash on CS3. The /dev interfaces + created are /dev/pensr0.. Hardware reset of the eMMC + is implemented by a sub-device reset-controller which accesses + a CS0 control register. + +maintainers: + - Brad Larson + +properties: + compatible: + items: + - enum: + - amd,pensando-elbasr + + spi-max-frequency: + description: Maximum SPI frequency of the device in Hz. + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - spi-max-frequency + +patternProperties: + '^reset-controller@[a-f0-9]+$': + $ref: /schemas/reset/amd,pensando-elbasr-reset.yaml + +additionalProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + + sysc: system-controller@0 { + compatible = "amd,pensando-elbasr"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <12000000>; + + rstc: reset-controller@0 { + compatible = "amd,pensando-elbasr-reset"; + reg = <0>; + #reset-cells = <1>; + }; + }; + + i2c1: i2c@1 { + compatible = "amd,pensando-elbasr"; + reg = <1>; + spi-max-frequency = <12000000>; + }; + + i2c2: i2c@2 { + compatible = "amd,pensando-elbasr"; + reg = <2>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + flash@3 { + compatible = "amd,pensando-elbasr"; + reg = <3>; + spi-max-frequency = <12000000>; + }; + }; + +... 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Sat, 20 Aug 2022 12:58:32 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:30 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 07/17] dt-bindings: reset: amd,pensando-elbasr-reset: Add AMD Pensando SR Reset Controller bindings Date: Sat, 20 Aug 2022 12:57:40 -0700 Message-Id: <20220820195750.70861-8-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Document bindings for AMD Pensando Elba SR Reset Controller Signed-off-by: Brad Larson --- .../reset/amd,pensando-elbasr-reset.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml b/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml new file mode 100644 index 000000000000..0fdc6cc5ecdd --- /dev/null +++ b/Documentation/devicetree/bindings/reset/amd,pensando-elbasr-reset.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/amd,pensando-elbasr-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Reset Controller + +maintainers: + - Brad Larson + +description: | + AMD Pensando Elba SoC reset controller driver which supports a resource + controller connected to the Elba SoC over a SPI bus. The Elba reset + controller must be defined as a child node of the Elba SPI bus + chip-select 0 node. + +properties: + compatible: + const: amd,pensando-elbasr-reset + + reg: + const: 0 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + + spi@0 { + compatible = "amd,pensando-elbasr"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <12000000>; + + rstc: reset-controller@0 { + compatible = "amd,pensando-elbasr-reset"; + reg = <0>; + #reset-cells = <1>; + }; + }; + }; + +... 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Sat, 20 Aug 2022 12:58:34 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:34 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 08/17] MAINTAINERS: Add entry for AMD PENSANDO Date: Sat, 20 Aug 2022 12:57:41 -0700 Message-Id: <20220820195750.70861-9-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f512b430c7cb..b46379a15a86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1802,6 +1802,15 @@ N: allwinner N: sun[x456789]i N: sun50i +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* +F: drivers/mfd/pensando* +F: drivers/reset/reset-elbasr.c + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet From patchwork Sat Aug 20 19:57:42 2022 Content-Type: text/plain; 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Sat, 20 Aug 2022 12:58:37 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:36 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 09/17] arm64: Add config for AMD Pensando SoC platforms Date: Sat, 20 Aug 2022 12:57:42 -0700 Message-Id: <20220820195750.70861-10-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 74e9e9de3759..4de253974544 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -225,6 +225,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Sat Aug 20 19:57:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 599065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6AE2C32772 for ; Sat, 20 Aug 2022 19:58:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233208AbiHTT64 (ORCPT ); Sat, 20 Aug 2022 15:58:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232443AbiHTT6n (ORCPT ); Sat, 20 Aug 2022 15:58:43 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA0482F03B for ; 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Sat, 20 Aug 2022 12:58:39 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:39 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 10/17] arm64: dts: Add AMD Pensando Elba SoC support Date: Sat, 20 Aug 2022 12:57:43 -0700 Message-Id: <20220820195750.70861-11-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 101 +++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 192 ++++++++++++++++++ 6 files changed, 617 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi new file mode 100644 index 000000000000..37aadd442db8 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..b0d6ec1953ab --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-hw-reset; + reset-names = "hw"; + resets = <&rstc 0>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + sysc: system-controller@0 { + compatible = "amd,pensando-elbasr"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <12000000>; + + rstc: reset-controller@0 { + compatible = "amd,pensando-elbasr-reset"; + reg = <0>; + #reset-cells = <1>; + }; + }; + + i2c1: i2c@1 { + compatible = "amd,pensando-elbasr"; + reg = <1>; + spi-max-frequency = <12000000>; + }; + + i2c2: i2c@2 { + compatible = "amd,pensando-elbasr"; + reg = <2>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + flash@3 { + compatible = "amd,pensando-elbasr"; + reg = <3>; + spi-max-frequency = <12000000>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model = "AMD Pensando Elba Board"; + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..734893fef2c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi new file mode 100644 index 000000000000..285d776aa67b --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model = "Elba ASIC Board"; + compatible = "amd,pensando-elba"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + snps,sda-timeout-ms = <750>; + interrupts = ; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "amd,pensando-elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + amd,pensando-elba-syscon = <&syscon>; + clocks = <&ahb_clk>; + interrupts = ; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + ranges; + interrupt-controller; + interrupts = ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks = <&emmc_clk>; + interrupts = ; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + syscon: syscon@307c0000 { + compatible = "amd,pensando-elba-syscon", "syscon"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; From patchwork Sat Aug 20 19:57:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 598838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A7D2C32796 for ; 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Sat, 20 Aug 2022 12:58:41 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 11/17] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Sat, 20 Aug 2022 12:57:44 -0700 Message-Id: <20220820195750.70861-12-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 72b1a5a2298c..fe1e96e93091 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -39,6 +39,7 @@ #define CQSPI_DISABLE_DAC_MODE BIT(1) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(4) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -87,6 +88,7 @@ struct cqspi_st { bool use_dma_read; u32 pd_dev_id; bool wr_completion; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -952,6 +954,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1667,6 +1676,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->use_dma_read = true; if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) cqspi->wr_completion = false; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1789,6 +1800,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pen_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1814,6 +1829,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pen_cdns_qspi, + }, { /* end of table */ } }; From patchwork Sat Aug 20 19:57:45 2022 Content-Type: text/plain; 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Sat, 20 Aug 2022 12:58:45 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:44 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 12/17] spi: dw: Add support for AMD Pensando Elba SoC Date: Sat, 20 Aug 2022 12:57:45 -0700 Message-Id: <20220820195750.70861-13-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson --- drivers/spi/spi-dw-mmio.c | 77 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..36b8c5e10bb3 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,24 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; +struct dw_spi_elba { + struct regmap *syscon; +}; + +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_SHIFT(cs) (2 * (cs)) +#define ELBA_SPICS_MASK(cs) (0x3 << ELBA_SPICS_SHIFT(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | 0x1) << ELBA_SPICS_SHIFT(cs)) + /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -237,6 +255,64 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, int enable) +{ + regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct dw_spi_elba *dwselba = dwsmmio->priv; + u8 cs; + + cs = spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(dwselba, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select = 0; + dw_spi_set_cs(spi, enable); + spi->chip_select = cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + const char *syscon_name = "amd,pensando-elba-syscon"; + struct device_node *np = pdev->dev.of_node; + struct device_node *node; + struct dw_spi_elba *dwselba; + struct regmap *regmap; + + node = of_parse_phandle(np, syscon_name, 0); + if (!node) { + dev_err(&pdev->dev, "failed to find %s\n", syscon_name); + return -ENODEV; + } + + regmap = syscon_node_to_regmap(node); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "syscon regmap lookup failed\n"); + return PTR_ERR(regmap); + } + + dwselba = devm_kzalloc(&pdev->dev, sizeof(*dwselba), GFP_KERNEL); + if (!dwselba) + return -ENOMEM; + + dwselba->syscon = regmap; + dwsmmio->priv = dwselba; + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +428,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); From patchwork Sat Aug 20 19:57:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 598837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D25E8C25B08 for ; Sat, 20 Aug 2022 19:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233894AbiHTT7F (ORCPT ); Sat, 20 Aug 2022 15:59:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232782AbiHTT6x (ORCPT ); Sat, 20 Aug 2022 15:58:53 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34437326E1 for ; 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Sat, 20 Aug 2022 12:58:47 -0700 (PDT) Received: from platform-dev1.pensando.io ([12.226.153.42]) by smtp.gmail.com with ESMTPSA id u66-20020a626045000000b005363bc65bb1sm2316794pfb.91.2022.08.20.12.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 12:58:47 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 13/17] mmc: sdhci-cadence: Enable device specific override of writel() Date: Sat, 20 Aug 2022 12:57:46 -0700 Message-Id: <20220820195750.70861-14-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson SoCs with device specific Cadence implementation, such as setting byte-enables before the write, need to override writel(). Add a callback where the default is writel() for all existing chips. Signed-off-by: Brad Larson --- drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 6f2de54a5987..708d4297f241 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; bool enhanced_strobe; + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) */ for (i = 0; i < 2; i++) { tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev) priv->nr_phy_params = nr_phy_params; priv->hrs_addr = host->ioaddr; priv->enhanced_strobe = false; + priv->priv_writel = cdns_writel; host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; From patchwork Sat Aug 20 19:57:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 599063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C1FAC25B08 for ; Sat, 20 Aug 2022 19:59:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234847AbiHTT7b (ORCPT ); Sat, 20 Aug 2022 15:59:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233625AbiHTT7B (ORCPT ); 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Sat, 20 Aug 2022 12:58:49 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 14/17] mfd: pensando-elbasr: Add AMD Pensando Elba System Resource chip Date: Sat, 20 Aug 2022 12:57:47 -0700 Message-Id: <20220820195750.70861-15-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add support for the AMD Pensando Elba SoC System Resource chip using the SPI interface. The Elba SR is a Multi-function Device supporting device register access using CS0, Designware I2C interface for FRU and board peripherals using CS1, dual Lattice rd1173 I2C masters for transceiver management using CS2, and CS3 for flash access. Signed-off-by: Brad Larson --- drivers/mfd/Kconfig | 14 + drivers/mfd/Makefile | 1 + drivers/mfd/pensando-elbasr.c | 854 ++++++++++++++++++++++++++++ include/linux/mfd/pensando-elbasr.h | 78 +++ 4 files changed, 947 insertions(+) create mode 100644 drivers/mfd/pensando-elbasr.c create mode 100644 include/linux/mfd/pensando-elbasr.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index abb58ab1a1a4..902c33386c52 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1051,6 +1051,20 @@ config UCB1400_CORE To compile this driver as a module, choose M here: the module will be called ucb1400_core. +config MFD_PENSANDO_ELBASR + bool "AMD Pensando Elba System Resource chip" + depends on SPI_MASTER=y + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + select REGMAP_SPI + select MFD_CORE + select MFD_SYSCON + help + Support for the AMD Pensando Elba SoC System Resource chip using the + SPI interface. This driver provides userspace access to four device + functions to include CS0 device registers, CS1 smbus interface for + FRU and board peripherals, CS2 dual Lattice I2C masters for + transceiver management, and CS3 flash for firmware update. + config MFD_PM8XXX tristate "Qualcomm PM8xxx PMIC chips driver" depends on (ARM || HEXAGON || COMPILE_TEST) diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 858cacf659d6..917b128abe5b 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -212,6 +212,7 @@ obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o obj-$(CONFIG_MFD_INTEL_PMC_BXT) += intel_pmc_bxt.o obj-$(CONFIG_MFD_PALMAS) += palmas.o +obj-$(CONFIG_MFD_PENSANDO_ELBASR) += pensando-elbasr.o obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o obj-$(CONFIG_MFD_NTXEC) += ntxec.o obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o diff --git a/drivers/mfd/pensando-elbasr.c b/drivers/mfd/pensando-elbasr.c new file mode 100644 index 000000000000..7cc02d44c5b9 --- /dev/null +++ b/drivers/mfd/pensando-elbasr.c @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD Pensando Elba System Resource MFD Driver + * + * Userspace interface and reset driver support for SPI connected + * Pensando Elba System Resource Chip. + * + * Adapted from spidev.c + * + * Copyright (C) 2006 SWAPP + * Andrea Paterniani + * Copyright (C) 2007 David Brownell (simplification, cleanup) + * Copyright 2022 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ELBASR_SPI_CMD_REGRD 0x0b +#define ELBASR_SPI_CMD_REGWR 0x02 +#define ELBASR_MAX_DEVS 4 + +/* + * The main reason to have this class is to make mdev/udev create the + * /dev/pensrB.C character device nodes exposing our userspace API. + * It also simplifies memory management. The device nodes + * /dev/pensrB.C are used for backward compatibility. + */ +static struct class *elbasr_class; + +static dev_t elbasr_devt; +static DECLARE_BITMAP(minors, ELBASR_MAX_DEVS); +static unsigned int bufsiz = 4096; + +static LIST_HEAD(device_list); +static DEFINE_MUTEX(device_list_lock); + +static const struct mfd_cell pensando_elbasr_subdev_info[] = { + { + .name = "pensando_elbasr_reset", + .of_compatible = "amd,pensando-elbasr-reset", + }, +}; + +/* + * Bit masks for spi_device.mode management. Note that incorrect + * settings for some settings can cause *lots* of trouble for other + * devices on a shared bus: + * + * - CS_HIGH ... this device will be active when it shouldn't be + * - 3WIRE ... when active, it won't behave as it should + * - NO_CS ... there will be no explicit message boundaries; this + * is completely incompatible with the shared bus model + * - READY ... transfers may proceed when they shouldn't. + */ +#define SPI_MODE_MASK (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH \ + | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ + | SPI_NO_CS | SPI_READY | SPI_TX_DUAL \ + | SPI_TX_QUAD | SPI_TX_OCTAL | SPI_RX_DUAL \ + | SPI_RX_QUAD | SPI_RX_OCTAL) + +static ssize_t +elbasr_spi_sync(struct elbasr_data *elbasr_spi, struct spi_message *message) +{ + int status; + struct spi_device *spi; + + spin_lock_irq(&elbasr_spi->spi_lock); + spi = elbasr_spi->spi; + spin_unlock_irq(&elbasr_spi->spi_lock); + if (!spi) + return -ESHUTDOWN; + + status = spi_sync(spi, message); + if (status) + return status; + + return message->actual_length; +} + +static inline ssize_t elbasr_spi_sync_write(struct elbasr_data *elbasr, size_t len) +{ + struct spi_transfer t[] = { + { + .tx_buf = elbasr->tx_buffer, + .len = len, + .speed_hz = elbasr->speed_hz, + }, + }; + struct spi_message m; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + return elbasr_spi_sync(elbasr, &m); +} + +static inline ssize_t elbasr_spi_sync_read(struct elbasr_data *elbasr, size_t len) +{ + struct spi_transfer t[] = { + { + .rx_buf = elbasr->rx_buffer, + .len = len, + .speed_hz = elbasr->speed_hz, + }, + }; + struct spi_message m; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + return elbasr_spi_sync(elbasr, &m); +} + +/* Read-only message with current device setup */ +static ssize_t +elbasr_spi_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos) +{ + struct elbasr_data *elbasr; + ssize_t status; + + /* chipselect only toggles at start or end of operation */ + if (count > bufsiz) + return -EMSGSIZE; + + elbasr = filp->private_data; + + mutex_lock(&elbasr->buf_lock); + status = elbasr_spi_sync_read(elbasr, count); + if (status > 0) { + unsigned long missing; + + missing = copy_to_user(buf, elbasr->rx_buffer, status); + if (missing == status) + status = -EFAULT; + else + status = status - missing; + } + mutex_unlock(&elbasr->buf_lock); + + return status; +} + +/* Write-only message with current device setup */ +static ssize_t elbasr_spi_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + struct elbasr_data *elbasr; + ssize_t status; + unsigned long missing; + + /* chipselect only toggles at start or end of operation */ + if (count > bufsiz) + return -EMSGSIZE; + + elbasr = filp->private_data; + + mutex_lock(&elbasr->buf_lock); + missing = copy_from_user(elbasr->tx_buffer, buf, count); + if (missing == 0) + status = elbasr_spi_sync_write(elbasr, count); + else + status = -EFAULT; + mutex_unlock(&elbasr->buf_lock); + + return status; +} + +static int elbasr_spi_message(struct elbasr_data *elbasr, + struct spi_ioc_transfer *u_xfers, + unsigned int n_xfers) +{ + struct spi_message msg; + struct spi_transfer *k_xfers; + struct spi_transfer *k_tmp; + struct spi_ioc_transfer *u_tmp; + unsigned int n, total, tx_total, rx_total; + u8 *tx_buf, *rx_buf; + int status = -EFAULT; + + spi_message_init(&msg); + k_xfers = kcalloc(n_xfers, sizeof(*k_tmp), GFP_KERNEL); + if (k_xfers == NULL) + return -ENOMEM; + + /* + * Construct spi_message, copying any tx data to bounce buffer. + * We walk the array of user-provided transfers, using each one + * to initialize a kernel version of the same transfer. + */ + tx_buf = elbasr->tx_buffer; + rx_buf = elbasr->rx_buffer; + total = 0; + tx_total = 0; + rx_total = 0; + for (n = n_xfers, k_tmp = k_xfers, u_tmp = u_xfers; + n; + n--, k_tmp++, u_tmp++) { + /* + * Ensure that also following allocations from rx_buf/tx_buf will meet + * DMA alignment requirements. + */ + unsigned int len_aligned = ALIGN(u_tmp->len, + ARCH_KMALLOC_MINALIGN); + + k_tmp->len = u_tmp->len; + + total += k_tmp->len; + /* + * Since the function returns the total length of transfers + * on success, restrict the total to positive int values to + * avoid the return value looking like an error. Also check + * each transfer length to avoid arithmetic overflow. + */ + if (total > INT_MAX || k_tmp->len > INT_MAX) { + status = -EMSGSIZE; + goto done; + } + + if (u_tmp->rx_buf) { + /* this transfer needs space in RX bounce buffer */ + rx_total += len_aligned; + if (rx_total > bufsiz) { + status = -EMSGSIZE; + goto done; + } + k_tmp->rx_buf = rx_buf; + rx_buf += len_aligned; + } + if (u_tmp->tx_buf) { + /* this transfer needs space in TX bounce buffer */ + tx_total += len_aligned; + if (tx_total > bufsiz) { + status = -EMSGSIZE; + goto done; + } + k_tmp->tx_buf = tx_buf; + if (copy_from_user(tx_buf, (const u8 __user *) + (uintptr_t) u_tmp->tx_buf, + u_tmp->len)) + goto done; + tx_buf += len_aligned; + } + + k_tmp->cs_change = !!u_tmp->cs_change; + k_tmp->tx_nbits = u_tmp->tx_nbits; + k_tmp->rx_nbits = u_tmp->rx_nbits; + k_tmp->bits_per_word = u_tmp->bits_per_word; + k_tmp->delay.value = u_tmp->delay_usecs; + k_tmp->delay.unit = SPI_DELAY_UNIT_USECS; + k_tmp->speed_hz = u_tmp->speed_hz; + k_tmp->word_delay.value = u_tmp->word_delay_usecs; + k_tmp->word_delay.unit = SPI_DELAY_UNIT_USECS; + if (!k_tmp->speed_hz) + k_tmp->speed_hz = elbasr->speed_hz; +#ifdef VERBOSE + dev_dbg(&elbasr->spi->dev, + " xfer len %u %s%s%s%dbits %u usec %u usec %uHz (%u)\n", + k_tmp->len, + k_tmp->rx_buf ? "rx " : "", + k_tmp->tx_buf ? "tx " : "", + k_tmp->cs_change ? "cs " : "", + k_tmp->bits_per_word ? : elbasr->spi->bits_per_word, + k_tmp->delay.value, + k_tmp->word_delay.value, + k_tmp->speed_hz ? : elbasr->spi->max_speed_hz); +#endif + spi_message_add_tail(k_tmp, &msg); + } + + status = elbasr_spi_sync(elbasr, &msg); + if (status < 0) + goto done; + + /* copy any rx data out of bounce buffer */ + for (n = n_xfers, k_tmp = k_xfers, u_tmp = u_xfers; + n; + n--, k_tmp++, u_tmp++) { + if (u_tmp->rx_buf) { + if (copy_to_user((u8 __user *) + (uintptr_t) u_tmp->rx_buf, k_tmp->rx_buf, + u_tmp->len)) { + status = -EFAULT; + goto done; + } + } + } + status = total; + +done: + kfree(k_xfers); + return status; +} + +static struct spi_ioc_transfer * +elbasr_spi_get_ioc_message(unsigned int cmd, + struct spi_ioc_transfer __user *u_ioc, + unsigned int *n_ioc) +{ + u32 tmp; + + /* Check type, command number and direction */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC + || _IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) + || _IOC_DIR(cmd) != _IOC_WRITE) + return ERR_PTR(-ENOTTY); + + tmp = _IOC_SIZE(cmd); + if ((tmp % sizeof(struct spi_ioc_transfer)) != 0) + return ERR_PTR(-EINVAL); + *n_ioc = tmp / sizeof(struct spi_ioc_transfer); + if (*n_ioc == 0) + return NULL; + + /* copy into scratch area */ + return memdup_user(u_ioc, tmp); +} + +static long +elbasr_spi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int retval = 0; + struct elbasr_data *elbasr; + struct spi_device *spi; + u32 tmp; + unsigned int n_ioc; + struct spi_ioc_transfer *ioc; + + /* Check type and command number */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC) + return -ENOTTY; + + /* + * guard against device removal before, or while, + * we issue this ioctl. + */ + elbasr = filp->private_data; + spin_lock_irq(&elbasr->spi_lock); + spi = spi_dev_get(elbasr->spi); + spin_unlock_irq(&elbasr->spi_lock); + + if (spi == NULL) + return -ESHUTDOWN; + + /* + * use the buffer lock here for triple duty: + * - prevent I/O (from us) so calling spi_setup() is safe; + * - prevent concurrent SPI_IOC_WR_* from morphing + * data fields while SPI_IOC_RD_* reads them; + * - SPI_IOC_MESSAGE needs the buffer locked "normally". + */ + mutex_lock(&elbasr->buf_lock); + + switch (cmd) { + /* read requests */ + case SPI_IOC_RD_MODE: + retval = put_user(spi->mode & SPI_MODE_MASK, + (__u8 __user *)arg); + break; + case SPI_IOC_RD_MODE32: + retval = put_user(spi->mode & SPI_MODE_MASK, + (__u32 __user *)arg); + break; + case SPI_IOC_RD_LSB_FIRST: + retval = put_user((spi->mode & SPI_LSB_FIRST) ? 1 : 0, + (__u8 __user *)arg); + break; + case SPI_IOC_RD_BITS_PER_WORD: + retval = put_user(spi->bits_per_word, (__u8 __user *)arg); + break; + case SPI_IOC_RD_MAX_SPEED_HZ: + retval = put_user(elbasr->speed_hz, (__u32 __user *)arg); + break; + + /* write requests */ + case SPI_IOC_WR_MODE: + case SPI_IOC_WR_MODE32: + if (cmd == SPI_IOC_WR_MODE) + retval = get_user(tmp, (u8 __user *)arg); + else + retval = get_user(tmp, (u32 __user *)arg); + if (retval == 0) { + struct spi_controller *ctlr = spi->controller; + u32 save = spi->mode; + + if (tmp & ~SPI_MODE_MASK) { + retval = -EINVAL; + break; + } + + if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods && + ctlr->cs_gpiods[spi->chip_select]) + tmp |= SPI_CS_HIGH; + + tmp |= spi->mode & ~SPI_MODE_MASK; + spi->mode = (u16)tmp; + retval = spi_setup(spi); + if (retval < 0) + spi->mode = save; + else + dev_dbg(&spi->dev, "spi mode %x\n", tmp); + } + break; + case SPI_IOC_WR_LSB_FIRST: + retval = get_user(tmp, (__u8 __user *)arg); + if (retval == 0) { + u32 save = spi->mode; + + if (tmp) + spi->mode |= SPI_LSB_FIRST; + else + spi->mode &= ~SPI_LSB_FIRST; + retval = spi_setup(spi); + if (retval < 0) + spi->mode = save; + else + dev_dbg(&spi->dev, "%csb first\n", + tmp ? 'l' : 'm'); + } + break; + case SPI_IOC_WR_BITS_PER_WORD: + retval = get_user(tmp, (__u8 __user *)arg); + if (retval == 0) { + u8 save = spi->bits_per_word; + + spi->bits_per_word = tmp; + retval = spi_setup(spi); + if (retval < 0) + spi->bits_per_word = save; + else + dev_dbg(&spi->dev, "%d bits per word\n", tmp); + } + break; + case SPI_IOC_WR_MAX_SPEED_HZ: + retval = get_user(tmp, (__u32 __user *)arg); + if (retval == 0) { + u32 save = spi->max_speed_hz; + + spi->max_speed_hz = tmp; + retval = spi_setup(spi); + if (retval == 0) { + elbasr->speed_hz = tmp; + dev_dbg(&spi->dev, "%d Hz (max)\n", + elbasr->speed_hz); + } + spi->max_speed_hz = save; + } + break; + + default: + /* + * Segmented and/or full-duplex I/O request. + * Check message and copy into scratch area. + */ + ioc = elbasr_spi_get_ioc_message(cmd, + (struct spi_ioc_transfer __user *)arg, &n_ioc); + if (IS_ERR(ioc)) { + retval = PTR_ERR(ioc); + break; + } + if (!ioc) + break; /* n_ioc is also 0 */ + + /* translate to spi_message, execute */ + retval = elbasr_spi_message(elbasr, ioc, n_ioc); + kfree(ioc); + break; + } + + mutex_unlock(&elbasr->buf_lock); + spi_dev_put(spi); + return retval; +} + +static long +elbasr_spi_compat_ioc_message(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct spi_ioc_transfer __user *u_ioc; + int retval = 0; + struct elbasr_data *elbasr; + struct spi_device *spi; + unsigned int n_ioc, n; + struct spi_ioc_transfer *ioc; + + u_ioc = (struct spi_ioc_transfer __user *) compat_ptr(arg); + + /* + * Guard against device removal before, or while, + * we issue this ioctl. + */ + elbasr = filp->private_data; + spin_lock_irq(&elbasr->spi_lock); + spi = spi_dev_get(elbasr->spi); + spin_unlock_irq(&elbasr->spi_lock); + + if (spi == NULL) + return -ESHUTDOWN; + + /* SPI_IOC_MESSAGE needs the buffer locked "normally" */ + mutex_lock(&elbasr->buf_lock); + + /* Check message and copy into scratch area */ + ioc = elbasr_spi_get_ioc_message(cmd, u_ioc, &n_ioc); + if (IS_ERR(ioc)) { + retval = PTR_ERR(ioc); + goto done; + } + if (!ioc) + goto done; /* n_ioc is also 0 */ + + /* Convert buffer pointers */ + for (n = 0; n < n_ioc; n++) { + ioc[n].rx_buf = (uintptr_t) compat_ptr(ioc[n].rx_buf); + ioc[n].tx_buf = (uintptr_t) compat_ptr(ioc[n].tx_buf); + } + + /* translate to spi_message, execute */ + retval = elbasr_spi_message(elbasr, ioc, n_ioc); + kfree(ioc); + +done: + mutex_unlock(&elbasr->buf_lock); + spi_dev_put(spi); + return retval; +} + +static long +elbasr_spi_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + if (_IOC_TYPE(cmd) == SPI_IOC_MAGIC + && _IOC_NR(cmd) == _IOC_NR(SPI_IOC_MESSAGE(0)) + && _IOC_DIR(cmd) == _IOC_WRITE) + return elbasr_spi_compat_ioc_message(filp, cmd, arg); + + return elbasr_spi_ioctl(filp, cmd, (unsigned long)compat_ptr(arg)); +} + +static int elbasr_spi_open(struct inode *inode, struct file *filp) +{ + struct elbasr_data *elbasr; + int status = -ENXIO; + + mutex_lock(&device_list_lock); + + list_for_each_entry(elbasr, &device_list, device_entry) { + if (elbasr->devt == inode->i_rdev) { + status = 0; + break; + } + } + + if (status) + goto err_find_dev; + + if (!elbasr->tx_buffer) { + elbasr->tx_buffer = kmalloc(bufsiz, GFP_KERNEL); + if (!elbasr->tx_buffer) { + status = -ENOMEM; + goto err_find_dev; + } + } + + if (!elbasr->rx_buffer) { + elbasr->rx_buffer = kmalloc(bufsiz, GFP_KERNEL); + if (!elbasr->rx_buffer) { + status = -ENOMEM; + goto err_alloc_rx_buf; + } + } + + elbasr->users++; + filp->private_data = elbasr; + stream_open(inode, filp); + + mutex_unlock(&device_list_lock); + return 0; + +err_alloc_rx_buf: + kfree(elbasr->tx_buffer); + elbasr->tx_buffer = NULL; +err_find_dev: + mutex_unlock(&device_list_lock); + return status; +} + +static int elbasr_spi_release(struct inode *inode, struct file *filp) +{ + struct elbasr_data *elbasr; + int dofree; + + mutex_lock(&device_list_lock); + elbasr = filp->private_data; + filp->private_data = NULL; + + spin_lock_irq(&elbasr->spi_lock); + /* ... after we unbound from the underlying device? */ + dofree = (elbasr->spi == NULL); + spin_unlock_irq(&elbasr->spi_lock); + + /* last close? */ + elbasr->users--; + if (!elbasr->users) { + + kfree(elbasr->tx_buffer); + elbasr->tx_buffer = NULL; + + kfree(elbasr->rx_buffer); + elbasr->rx_buffer = NULL; + + if (dofree) + kfree(elbasr); + else + elbasr->speed_hz = elbasr->spi->max_speed_hz; + } +#ifdef CONFIG_SPI_SLAVE + if (!dofree) + spi_slave_abort(elbasr->spi); +#endif + mutex_unlock(&device_list_lock); + + return 0; +} + +static const struct file_operations elbasr_spi_fops = { + .owner = THIS_MODULE, + .write = elbasr_spi_write, + .read = elbasr_spi_read, + .unlocked_ioctl = elbasr_spi_ioctl, + .compat_ioctl = elbasr_spi_compat_ioctl, + .open = elbasr_spi_open, + .release = elbasr_spi_release, + .llseek = no_llseek, +}; + +static bool elbasr_reg_readable(struct device *dev, unsigned int reg) +{ + return reg <= ELBASR_MAX_REG; +} + +static bool elbasr_reg_writeable(struct device *dev, unsigned int reg) +{ + return reg <= ELBASR_MAX_REG; +} + +static int elbasr_regs_read(void *ctx, u32 reg, u32 *val) +{ + struct elbasr_data *elbasr = dev_get_drvdata(ctx); + struct spi_message m; + struct spi_transfer t[2] = { 0 }; + int ret; + u8 txbuf[3]; + u8 rxbuf[1]; + + txbuf[0] = ELBASR_SPI_CMD_REGRD; + txbuf[1] = reg; + txbuf[2] = 0x0; + t[0].tx_buf = (u8 *)txbuf; + t[0].len = 3; + + rxbuf[0] = 0x0; + t[1].rx_buf = rxbuf; + t[1].len = 1; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = elbasr_spi_sync(elbasr, &m); + if (ret == 4) { + /* 3 Tx + 1 Rx = 4 */ + *val = rxbuf[0]; + return 0; + } + return -EIO; +} + +static int elbasr_regs_write(void *ctx, u32 reg, u32 val) +{ + struct elbasr_data *elbasr = dev_get_drvdata(ctx); + struct spi_message m; + struct spi_transfer t[1] = { 0 }; + u8 txbuf[4]; + + txbuf[0] = ELBASR_SPI_CMD_REGWR; + txbuf[1] = reg; + txbuf[2] = val; + txbuf[3] = 0; + + t[0].tx_buf = txbuf; + t[0].len = 4; + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + return elbasr_spi_sync(elbasr, &m); +} + +static const struct regmap_config pensando_elbasr_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_NONE, + .readable_reg = elbasr_reg_readable, + .writeable_reg = elbasr_reg_writeable, + .reg_read = elbasr_regs_read, + .reg_write = elbasr_regs_write, + .max_register = ELBASR_MAX_REG, +}; + +/* + * Setup Elba SPI access to System Resource Chip registers on CS0 + */ +static int elbasr_regs_setup(struct spi_device *spi, struct elbasr_data *elbasr) +{ + int ret; + + spi->bits_per_word = 8; + spi_setup(spi); + if (!spi->dev.dma_mask) + spi->dev.dma_mask = &spi->dev.coherent_dma_mask; + + elbasr->elbasr_regs = regmap_init(&spi->dev, NULL, spi, + &pensando_elbasr_regmap_config); + if (IS_ERR(elbasr->elbasr_regs)) + return dev_err_probe(&spi->dev, PTR_ERR(elbasr->elbasr_regs), + "Failed to allocate register map"); + + ret = mfd_add_devices(&spi->dev, PLATFORM_DEVID_NONE, + pensando_elbasr_subdev_info, + ARRAY_SIZE(pensando_elbasr_subdev_info), + NULL, 0, NULL); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to register sub-devices\n"); + return 0; +} + +static int elbasr_spi_probe(struct spi_device *spi) +{ + struct elbasr_data *elbasr; + unsigned long minor; + int status; + + if (spi->chip_select == 0) { + status = alloc_chrdev_region(&elbasr_devt, 0, ELBASR_MAX_DEVS, + "elbasr"); + if (status < 0) + return status; + + elbasr_class = class_create(THIS_MODULE, "elbasr"); + if (IS_ERR(elbasr_class)) { + unregister_chrdev(MAJOR(elbasr_devt), "elbasr"); + return PTR_ERR(elbasr_class); + } + } + + /* Allocate driver data */ + elbasr = kzalloc(sizeof(*elbasr), GFP_KERNEL); + if (!elbasr) + return -ENOMEM; + + /* Initialize the driver data */ + elbasr->spi = spi; + elbasr->speed_hz = spi->max_speed_hz; + spin_lock_init(&elbasr->spi_lock); + mutex_init(&elbasr->buf_lock); + + INIT_LIST_HEAD(&elbasr->device_entry); + + mutex_lock(&device_list_lock); + minor = find_first_zero_bit(minors, ELBASR_MAX_DEVS); + if (minor < ELBASR_MAX_DEVS) { + struct device *dev; + + elbasr->devt = MKDEV(MAJOR(elbasr_devt), minor); + dev = device_create(elbasr_class, + &spi->dev, + elbasr->devt, + elbasr, + "pensr%d.%d", + spi->master->bus_num, + spi->chip_select); + + status = PTR_ERR_OR_ZERO(dev); + } else { + dev_dbg(&spi->dev, "no minor number available\n"); + status = -ENODEV; + goto minor_failed; + } + + set_bit(minor, minors); + list_add(&elbasr->device_entry, &device_list); + dev_dbg(&spi->dev, + "created device for major %d, minor %lu\n", + MAJOR(elbasr_devt), minor); + mutex_unlock(&device_list_lock); + + /* Create cdev */ + elbasr->cdev = cdev_alloc(); + if (!elbasr->cdev) { + dev_err(elbasr->dev, "allocation of cdev failed"); + status = -ENOMEM; + goto cdev_failed; + } + elbasr->cdev->owner = THIS_MODULE; + cdev_init(elbasr->cdev, &elbasr_spi_fops); + + status = cdev_add(elbasr->cdev, elbasr->devt, 1); + if (status) { + dev_err(elbasr->dev, "register of cdev failed"); + goto cdev_delete; + } + spi_set_drvdata(spi, elbasr); + + /* Add Elba reset driver sub-device */ + if (spi->chip_select == 0) { + status = elbasr_regs_setup(spi, elbasr); + if (status) + dev_err(elbasr->dev, "sub-device setup failed"); + } + return 0; + +cdev_delete: + if (spi->chip_select == 0) + cdev_del(elbasr->cdev); +cdev_failed: + if (spi->chip_select == 0) + device_destroy(elbasr_class, elbasr->devt); +minor_failed: + kfree(elbasr); + + return status; +} + +static const struct of_device_id elbasr_dt_match[] = { + { .compatible = "amd,pensando-elbasr" }, + { /* sentinel */ } +}; + +static struct spi_driver elbasr_spi_driver = { + .probe = elbasr_spi_probe, + .driver = { + .name = "pensando-elbasr", + .of_match_table = elbasr_dt_match, + }, +}; +builtin_driver(elbasr_spi_driver, spi_register_driver) diff --git a/include/linux/mfd/pensando-elbasr.h b/include/linux/mfd/pensando-elbasr.h new file mode 100644 index 000000000000..32969397a72d --- /dev/null +++ b/include/linux/mfd/pensando-elbasr.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Declarations for AMD Pensando Elba System Resource Chip + */ + +#ifndef __MFD_AMD_PENSANDO_ELBA_H +#define __MFD_AMD_PENSANDO_ELBA_H + +#include +#include + +#define ELBASR_REVISION_REG 0x00 +#define ELBASR_CTRL_REG 0x01 +#define ELBASR_QSFP_CTRL_REG 0x02 +#define ELBASR_INTERRUPT_ENABLE_REG 0x03 +#define ELBASR_INTERRUPT_STATUS_REG 0x04 +#define ELBASR_QSFP_LED_REG 0x05 +#define ELBASR_QSFP_LED_FREQUENCY_REG 0x0F +#define ELBASR_CTRL0_REG 0x10 +#define ELBASR_CTRL1_REG 0x11 +#define ELBASR_CTRL2_REG 0x12 +#define ELBASR_SYSTEM_LED_REG 0x15 +#define ELBASR_CORE_TEMP_REG 0x16 +#define ELBASR_HBM_TEMP_REG 0x17 +#define ELBASR_BOARD_TEMP_REG 0x18 +#define ELBASR_QSFP_PORT1_TEMP_REG 0x19 +#define ELBASR_QSFP_PORT2_TEMP_REG 0x1a +#define ELBASR_HBM_WARNING_TEMP_REG 0x1b +#define ELBASR_HBM_CRITICAL_TEMP_REG 0x1c +#define ELBASR_HBM_FATAL_TEMP_REG 0x1d +#define ELBASR_ROT_REG0_CNTL_REG 0x23 +#define ELBASR_PUF_ERROR_LIMITS_REG 0x29 +#define ELBASR_PUF_ERROR_COUNT_REG 0x2a +#define ELBASR_QSFP_PORT1_ALARM_TEMP_REG 0x34 +#define ELBASR_QSFP_PORT1_WARNING_TEMP_REG 0x35 +#define ELBASR_QSFP_PORT2_ALARM_TEMP_REG 0x36 +#define ELBASR_QSFP_PORT2_WARNING_TEMP_REG 0x37 +#define ELBASR_SYSTEM_HEALTH0_REG 0x38 +#define ELBASR_SYSTEM_HEALTH1_REG 0x39 +#define ELBASR_MAJOR_FW_VER_REG 0x3a +#define ELBASR_MINOR_FW_VER_REG 0x3b +#define ELBASR_MAINTANENCE_FW_VER_REG 0x3c +#define ELBASR_PIPELINE_FW_REG 0x3d +#define ELBASR_QSFP_PRESENT_REG 0x40 +#define ELBASR_OCP_SLOTID_REG 0x42 +#define ELBASR_OCP_SC_DATA0_REG 0x43 +#define ELBASR_OCP_SC_DATA1_REG 0x44 +#define ELBASR_ID 0x80 + +#define ELBASR_MAX_REG 0xff +#define ELBASR_NR_RESETS 1 + +/* + * Pensando Elba System Resource device private data structure + */ +struct elbasr_data { + dev_t devt; + int minor; + struct device *dev; + struct cdev *cdev; + struct spi_device *spi; + struct list_head device_entry; + spinlock_t spi_lock; + + /* TX/RX buffers are NULL unless this device is open (users > 0) */ + struct mutex buf_lock; + unsigned int users; + u8 *tx_buffer; + u8 *rx_buffer; + u32 speed_hz; + + /* System Resource Chip CS0 register access */ + struct regmap *elbasr_regs; +}; + +#endif /* __MFD_AMD_PENSANDO_ELBA_H */ From patchwork Sat Aug 20 19:57:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 598836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B51BBC32772 for ; Sat, 20 Aug 2022 19:59:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235030AbiHTT7b (ORCPT ); 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Sat, 20 Aug 2022 12:58:52 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 15/17] reset: elbasr: Add AMD Pensando Elba SR Reset Controller Date: Sat, 20 Aug 2022 12:57:48 -0700 Message-Id: <20220820195750.70861-16-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson This patch adds the reset controller functionality for the AMD Pensando Elba System Resource Chip. Signed-off-by: Brad Larson Reviewed-by: Philipp Zabel --- drivers/reset/Kconfig | 9 +++++ drivers/reset/Makefile | 1 + drivers/reset/reset-elbasr.c | 77 ++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/reset/reset-elbasr.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 806773e88832..04b700c90ce4 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,15 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. +config RESET_ELBASR + tristate "Pensando Elba System Resource reset controller" + depends on MFD_PENSANDO_ELBASR || COMPILE_TEST + help + This option enables support for the external reset functions + on the Pensando Elba System Resource Chip. Reset control + of peripherals is accessed over SPI to the system resource + chip device registers using CS0. + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on HAS_IOMEM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index cd5cf8e7c6a7..9e6b095ee63a 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_ELBASR) += reset-elbasr.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o diff --git a/drivers/reset/reset-elbasr.c b/drivers/reset/reset-elbasr.c new file mode 100644 index 000000000000..ab5d49f5e6a7 --- /dev/null +++ b/drivers/reset/reset-elbasr.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2022 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include + +struct elbasr_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static inline struct elbasr_reset *to_elbasr_rst(struct reset_controller_dev *rc) +{ + return container_of(rc, struct elbasr_reset, rcdev); +} + +static int elbasr_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct elbasr_reset *elbar = to_elbasr_rst(rcdev); + + return regmap_update_bits(elbar->regmap, ELBASR_CTRL0_REG, BIT(6), BIT(6)); +} + +static int elbasr_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct elbasr_reset *elbar = to_elbasr_rst(rcdev); + + return regmap_update_bits(elbar->regmap, ELBASR_CTRL0_REG, BIT(6), 0); +} + +static const struct reset_control_ops elbasr_reset_ops = { + .assert = elbasr_reset_assert, + .deassert = elbasr_reset_deassert, +}; + +static int elbasr_reset_probe(struct platform_device *pdev) +{ + struct elbasr_data *elbasr = dev_get_drvdata(pdev->dev.parent); + struct elbasr_reset *elbar; + + elbar = devm_kzalloc(&pdev->dev, sizeof(struct elbasr_reset), + GFP_KERNEL); + if (!elbar) + return -ENOMEM; + + elbar->rcdev.owner = THIS_MODULE; + elbar->rcdev.nr_resets = ELBASR_NR_RESETS; + elbar->rcdev.ops = &elbasr_reset_ops; + elbar->rcdev.of_node = pdev->dev.of_node; + elbar->regmap = elbasr->elbasr_regs; + + platform_set_drvdata(pdev, elbar); + + return devm_reset_controller_register(&pdev->dev, &elbar->rcdev); +} + +static const struct of_device_id elba_reset_dt_match[] = { + { .compatible = "amd,pensando-elbasr-reset", }, + { /* sentinel */ } +}; + +static struct platform_driver elbasr_reset_driver = { + .probe = elbasr_reset_probe, + .driver = { + .name = "pensando_elbasr_reset", + .of_match_table = elba_reset_dt_match, + }, +}; +builtin_platform_driver(elbasr_reset_driver); From patchwork Sat Aug 20 19:57:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 599062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34D10C32772 for ; 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Sat, 20 Aug 2022 12:58:54 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 16/17] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Sat, 20 Aug 2022 12:57:49 -0700 Message-Id: <20220820195750.70861-17-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors. Signed-off-by: Brad Larson --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 132 ++++++++++++++++++++++++++++--- 2 files changed, 123 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 10c563999d3d..9af316d5bca4 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -244,6 +244,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 708d4297f241..c662c63d49fa 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; @@ -77,6 +79,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -316,6 +323,92 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, sdhci_set_uhs_signaling(host, timing); } +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = GENMASK(1, 0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = BIT(0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + struct resource *iomem; + void __iomem *ioaddr; + + host->mmc->caps |= (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA); + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!iomem) + return -ENOMEM; + + /* Byte-lane control register */ + ioaddr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr = ioaddr; + priv->priv_writel = elba_priv_writel; + spin_lock_init(&priv->wrlock); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -325,13 +418,24 @@ static const struct sdhci_ops sdhci_cdns_ops = { .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, }; -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, +}; + +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, }; -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + }, }; static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -357,7 +461,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -376,10 +480,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev) data = of_device_get_match_data(dev); if (!data) - data = &sdhci_cdns_pltfm_data; + data = &sdhci_cdns_drv_data; nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); - host = sdhci_pltfm_init(pdev, data, + host = sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret = PTR_ERR(host); @@ -388,7 +492,6 @@ static int sdhci_cdns_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); pltfm_host->clk = clk; - priv = sdhci_pltfm_priv(pltfm_host); priv->nr_phy_params = nr_phy_params; priv->hrs_addr = host->ioaddr; @@ -397,6 +500,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev) host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret = data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); @@ -461,7 +569,11 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = { static const struct of_device_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc", - .data = &sdhci_cdns_uniphier_pltfm_data, + .data = &sdhci_cdns_uniphier_drv_data, + }, + { + .compatible = "amd,pensando-elba-sd4hc", + .data = &sdhci_elba_drv_data, }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ } From patchwork Sat Aug 20 19:57:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 598835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 039BBC25B08 for ; Sat, 20 Aug 2022 20:00:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231792AbiHTUAS (ORCPT ); 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Sat, 20 Aug 2022 12:58:56 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, ulf.hansson@linaro.org, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 17/17] mmc: sdhci-cadence: Support mmc hardware reset Date: Sat, 20 Aug 2022 12:57:50 -0700 Message-Id: <20220820195750.70861-18-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220820195750.70861-1-brad@pensando.io> References: <20220820195750.70861-1-brad@pensando.io> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Brad Larson Add support for mmc hardware reset with a reset-controller which would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson --- drivers/mmc/host/sdhci-cadence.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index c662c63d49fa..35d37b9aba63 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "sdhci-pltfm.h" @@ -70,6 +71,7 @@ struct sdhci_cdns_priv { spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -458,6 +460,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } +static void sdhci_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + + dev_info(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 9us for good measure */ + udelay(9); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -520,6 +538,17 @@ static int sdhci_cdns_probe(struct platform_device *pdev) if (ret) goto free; + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, "hw"); + if (IS_ERR(priv->rst_hw)) { + ret = PTR_ERR(priv->rst_hw); + if (ret == -ENOENT) + priv->rst_hw = NULL; + } else { + host->mmc_host_ops.card_hw_reset = sdhci_mmc_hw_reset; + } + } + ret = sdhci_add_host(host); if (ret) goto free;