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[209.132.180.67]) by mx.google.com with ESMTP id t71si2001081pfa.244.2019.02.07.02.50.16; Thu, 07 Feb 2019 02:50:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EjBps9hd; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726755AbfBGKuP (ORCPT + 15 others); Thu, 7 Feb 2019 05:50:15 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:36752 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726844AbfBGKuP (ORCPT ); Thu, 7 Feb 2019 05:50:15 -0500 Received: by mail-wm1-f67.google.com with SMTP id p6so6142813wmc.1 for ; Thu, 07 Feb 2019 02:50:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=Ek3UlFm5/xHdKnlORtmVdKzhnOGPoXA69pA85rEGLP0=; b=EjBps9hdBDdU1QWCCvTV4SM2TgGUojliCWAAFt5MmQvIxN2S/krqfEkB2rCwwZHw2l Yjq/KmbEuS4sY+GnpHTaHYAAFOZZP2EQ6GlQpk9E+w65PLEo1WB9DK15BjDl5Iw0Z/oy Oulv2MDfpHNSqkv45+IS0QMAwVcFTkRNBUAfBUJWrkTtHiUZQHn8Bn0GclYsyWTQM0b3 vX2Hem7YguabKsVxRtwEGwu+gB0ISk2xKP+BQMC3u2nRx7qEwGrT1WRabVvbdN2esa+M cz+8vyGWJoacL/A5fpn8Cv4c+K8/Wco6x1x2MrdidRNPnjGcxUyCmSf8HaO2qsXFh4/C MbBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=Ek3UlFm5/xHdKnlORtmVdKzhnOGPoXA69pA85rEGLP0=; b=eNnuyjL9hnPIfhtM29xtUxvMcSAuNOD7i3aoY671SWOrEqAd95dSC3TGAihjt8Tzpu c8ygmyvlL3Jv45vk88Ftol3wOYjVCGCaklXQH+DZ/te3U0YlcP++KfchoCbCVh/jHhDT /epp3QgBFn3xdyXX1fjFT8teFdtQTzG91DBCJkzhYHc7fcbd9zLOfk2gN5JUoj0nn4Cx ACWlnMWXiP8Bify8SEuVa+Qt2Ucs2kYmv6ZbvLcSjGH4mMprs/N2Km4wFvjaZ5rzcUwy twbdBVuTB1uttovsgFk/ZZ1+YtdM5Ne//yiCL4uT6wHBX7ocPV8NVc3Q2ZuPNdzkJ4bV d6QQ== X-Gm-Message-State: AHQUAuY0DWapNlJkHkVC/vNvstMo+2aRFL/UcURp/Ux+9Xl60hCm10iO O5ZAzz8Q2LC7KyT/lSIxXAnaCw== X-Received: by 2002:a7b:c4c6:: with SMTP id g6mr5772441wmk.4.1549536613558; Thu, 07 Feb 2019 02:50:13 -0800 (PST) Received: from localhost ([49.248.196.115]) by smtp.gmail.com with ESMTPSA id q21sm13289929wmc.14.2019.02.07.02.50.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 02:50:13 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v1 03/24] drivers: thermal: tsens: Rename tsens_device Date: Thu, 7 Feb 2019 16:19:21 +0530 Message-Id: <7579d56663c5309d3171130afdf3858b2aaa387c.1549525708.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename to tsens_priv to denote that it is private data for each tsens instance. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-8916.c | 2 +- drivers/thermal/qcom/tsens-8960.c | 14 +++++++------- drivers/thermal/qcom/tsens-8974.c | 2 +- drivers/thermal/qcom/tsens-common.c | 6 +++--- drivers/thermal/qcom/tsens-v2.c | 2 +- drivers/thermal/qcom/tsens.c | 14 +++++++------- drivers/thermal/qcom/tsens.h | 30 ++++++++++++++--------------- 7 files changed, 35 insertions(+), 35 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-8916.c b/drivers/thermal/qcom/tsens-8916.c index 66edcfca1526..7b8f83c9a033 100644 --- a/drivers/thermal/qcom/tsens-8916.c +++ b/drivers/thermal/qcom/tsens-8916.c @@ -39,7 +39,7 @@ #define CAL_SEL_MASK 0xe0000000 #define CAL_SEL_SHIFT 29 -static int calibrate_8916(struct tsens_device *tmdev) +static int calibrate_8916(struct tsens_priv *tmdev) { int base0 = 0, base1 = 0, i; u32 p1[5], p2[5]; diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index f3c3820e6e8e..7e340eea48da 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -56,7 +56,7 @@ #define TRDY_MASK BIT(7) #define TIMEOUT_US 100 -static int suspend_8960(struct tsens_device *tmdev) +static int suspend_8960(struct tsens_priv *tmdev) { int ret; unsigned int mask; @@ -82,7 +82,7 @@ static int suspend_8960(struct tsens_device *tmdev) return 0; } -static int resume_8960(struct tsens_device *tmdev) +static int resume_8960(struct tsens_priv *tmdev) { int ret; struct regmap *map = tmdev->tm_map; @@ -112,7 +112,7 @@ static int resume_8960(struct tsens_device *tmdev) return 0; } -static int enable_8960(struct tsens_device *tmdev, int id) +static int enable_8960(struct tsens_priv *tmdev, int id) { int ret; u32 reg, mask; @@ -138,7 +138,7 @@ static int enable_8960(struct tsens_device *tmdev, int id) return 0; } -static void disable_8960(struct tsens_device *tmdev) +static void disable_8960(struct tsens_priv *tmdev) { int ret; u32 reg_cntl; @@ -162,7 +162,7 @@ static void disable_8960(struct tsens_device *tmdev) regmap_write(tmdev->tm_map, CNTL_ADDR, reg_cntl); } -static int init_8960(struct tsens_device *tmdev) +static int init_8960(struct tsens_priv *tmdev) { int ret, i; u32 reg_cntl; @@ -212,7 +212,7 @@ static int init_8960(struct tsens_device *tmdev) return 0; } -static int calibrate_8960(struct tsens_device *tmdev) +static int calibrate_8960(struct tsens_priv *tmdev) { int i; char *data; @@ -243,7 +243,7 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } -static int get_temp_8960(struct tsens_device *tmdev, int id, int *temp) +static int get_temp_8960(struct tsens_priv *tmdev, int id, int *temp) { int ret; u32 code, trdy; diff --git a/drivers/thermal/qcom/tsens-8974.c b/drivers/thermal/qcom/tsens-8974.c index 5023f20afc14..f983f98f2176 100644 --- a/drivers/thermal/qcom/tsens-8974.c +++ b/drivers/thermal/qcom/tsens-8974.c @@ -91,7 +91,7 @@ #define BIT_APPEND 0x3 -static int calibrate_8974(struct tsens_device *tmdev) +static int calibrate_8974(struct tsens_priv *tmdev) { int base1 = 0, base2 = 0, i; u32 p1[11], p2[11]; diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 78652cac7f3d..128ee3621b41 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -46,7 +46,7 @@ char *qfprom_read(struct device *dev, const char *cname) * and offset values are derived from tz->tzp->slope and tz->tzp->offset * resp. */ -void compute_intercept_slope(struct tsens_device *tmdev, u32 *p1, +void compute_intercept_slope(struct tsens_priv *tmdev, u32 *p1, u32 *p2, u32 mode) { int i; @@ -95,7 +95,7 @@ static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) return degc; } -int get_temp_common(struct tsens_device *tmdev, int id, int *temp) +int get_temp_common(struct tsens_priv *tmdev, int id, int *temp) { struct tsens_sensor *s = &tmdev->sensor[id]; u32 code; @@ -127,7 +127,7 @@ static const struct regmap_config tsens_srot_config = { .reg_stride = 4, }; -int __init init_common(struct tsens_device *tmdev) +int __init init_common(struct tsens_priv *tmdev) { void __iomem *tm_base, *srot_base; struct resource *res; diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index cc98a61e093b..d812fd3f4567 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -12,7 +12,7 @@ #define LAST_TEMP_MASK 0xfff #define STATUS_VALID_BIT BIT(21) -static int get_temp_tsens_v2(struct tsens_device *tmdev, int id, int *temp) +static int get_temp_tsens_v2(struct tsens_priv *tmdev, int id, int *temp) { struct tsens_sensor *s = &tmdev->sensor[id]; u32 code; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 065ec2189bd3..074fbb4d70f2 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -15,7 +15,7 @@ static int tsens_get_temp(void *data, int *temp) { const struct tsens_sensor *s = data; - struct tsens_device *tmdev = s->tmdev; + struct tsens_priv *tmdev = s->tmdev; return tmdev->ops->get_temp(tmdev, s->id, temp); } @@ -23,7 +23,7 @@ static int tsens_get_temp(void *data, int *temp) static int tsens_get_trend(void *p, int trip, enum thermal_trend *trend) { const struct tsens_sensor *s = p; - struct tsens_device *tmdev = s->tmdev; + struct tsens_priv *tmdev = s->tmdev; if (tmdev->ops->get_trend) return tmdev->ops->get_trend(tmdev, s->id, trend); @@ -33,7 +33,7 @@ static int tsens_get_trend(void *p, int trip, enum thermal_trend *trend) static int __maybe_unused tsens_suspend(struct device *dev) { - struct tsens_device *tmdev = dev_get_drvdata(dev); + struct tsens_priv *tmdev = dev_get_drvdata(dev); if (tmdev->ops && tmdev->ops->suspend) return tmdev->ops->suspend(tmdev); @@ -43,7 +43,7 @@ static int __maybe_unused tsens_suspend(struct device *dev) static int __maybe_unused tsens_resume(struct device *dev) { - struct tsens_device *tmdev = dev_get_drvdata(dev); + struct tsens_priv *tmdev = dev_get_drvdata(dev); if (tmdev->ops && tmdev->ops->resume) return tmdev->ops->resume(tmdev); @@ -76,7 +76,7 @@ static const struct thermal_zone_of_device_ops tsens_of_ops = { .get_trend = tsens_get_trend, }; -static int tsens_register(struct tsens_device *tmdev) +static int tsens_register(struct tsens_priv *tmdev) { int i; struct thermal_zone_device *tzd; @@ -101,7 +101,7 @@ static int tsens_probe(struct platform_device *pdev) int ret, i; struct device *dev; struct device_node *np; - struct tsens_device *tmdev; + struct tsens_priv *tmdev; const struct tsens_plat_data *data; const struct of_device_id *id; u32 num_sensors; @@ -174,7 +174,7 @@ static int tsens_probe(struct platform_device *pdev) static int tsens_remove(struct platform_device *pdev) { - struct tsens_device *tmdev = platform_get_drvdata(pdev); + struct tsens_priv *tmdev = platform_get_drvdata(pdev); if (tmdev->ops->disable) tmdev->ops->disable(tmdev); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 232376c690cc..936bdc7b1bc2 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -12,7 +12,7 @@ #include -struct tsens_device; +struct tsens_priv; /** * struct tsens_sensor - data for each sensor connected to the tsens device @@ -25,7 +25,7 @@ struct tsens_device; * @status: 8960-specific variable to track 8960 and 8660 status register offset */ struct tsens_sensor { - struct tsens_device *tmdev; + struct tsens_priv *tmdev; struct thermal_zone_device *tzd; int offset; int id; @@ -47,15 +47,15 @@ struct tsens_sensor { */ struct tsens_ops { /* mandatory callbacks */ - int (*init)(struct tsens_device *); - int (*calibrate)(struct tsens_device *); - int (*get_temp)(struct tsens_device *, int, int *); + int (*init)(struct tsens_priv *); + int (*calibrate)(struct tsens_priv *); + int (*get_temp)(struct tsens_priv *, int, int *); /* optional callbacks */ - int (*enable)(struct tsens_device *, int); - void (*disable)(struct tsens_device *); - int (*suspend)(struct tsens_device *); - int (*resume)(struct tsens_device *); - int (*get_trend)(struct tsens_device *, int, enum thermal_trend *); + int (*enable)(struct tsens_priv *, int); + void (*disable)(struct tsens_priv *); + int (*suspend)(struct tsens_priv *); + int (*resume)(struct tsens_priv *); + int (*get_trend)(struct tsens_priv *, int, enum thermal_trend *); }; enum reg_list { @@ -87,7 +87,7 @@ struct tsens_context { }; /** - * struct tsens_device - private data for each instance of the tsens IP + * struct tsens_priv - private data for each instance of the tsens IP * @dev: pointer to struct device * @num_sensors: number of sensors enabled on this device * @tm_map: pointer to TM register address space @@ -99,7 +99,7 @@ struct tsens_context { * @ops: pointer to list of callbacks supported by this device * @sensor: list of sensors attached to this device */ -struct tsens_device { +struct tsens_priv { struct device *dev; u32 num_sensors; struct regmap *tm_map; @@ -112,9 +112,9 @@ struct tsens_device { }; char *qfprom_read(struct device *, const char *); -void compute_intercept_slope(struct tsens_device *, u32 *, u32 *, u32); -int init_common(struct tsens_device *); -int get_temp_common(struct tsens_device *, int, int *); +void compute_intercept_slope(struct tsens_priv *, u32 *, u32 *, u32); +int init_common(struct tsens_priv *); +int get_temp_common(struct tsens_priv *, int, int *); /* TSENS v1 targets */ extern const struct tsens_plat_data data_8916, data_8974, data_8960; From patchwork Thu Feb 7 10:49:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 157693 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp488283jaa; Thu, 7 Feb 2019 02:50:30 -0800 (PST) X-Google-Smtp-Source: AHgI3IbMzJHK3jZjjkDB5I0bJHIEA0kro2T2oCIoJMuX9OolH+J5pBvrFDzs9E0v4093XWO9xVjR X-Received: by 2002:a17:902:f01:: with SMTP id 1mr15387293ply.143.1549536630755; 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Remove a stray space while we're at it. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 4582d2b30e94..0b5be08d515f 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -20,13 +20,13 @@ static int tsens_get_temp(void *data, int *temp) return priv->ops->get_temp(priv, s->id, temp); } -static int tsens_get_trend(void *p, int trip, enum thermal_trend *trend) +static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend) { - const struct tsens_sensor *s = p; + const struct tsens_sensor *s = data; struct tsens_priv *priv = s->priv; if (priv->ops->get_trend) - return priv->ops->get_trend(priv, s->id, trend); + return priv->ops->get_trend(priv, s->id, trend); return -ENOTSUPP; } From patchwork Thu Feb 7 10:49:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 157744 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp611341jaa; Thu, 7 Feb 2019 04:57:53 -0800 (PST) X-Google-Smtp-Source: AHgI3IY5Qs+eF/D9AVwLXJ1+DaZie0hXsx9JzJ3iVaxMawUsKFLLABWm2YJUADkBhDRaeGPWeel6 X-Received: by 2002:a17:902:f08b:: with SMTP id go11mr850034plb.115.1549544273660; Thu, 07 Feb 2019 04:57:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549544273; cv=none; d=google.com; s=arc-20160816; b=sIYtNokxBcM/YQ77LIAVC7uqZGbaWkYsDbejm+VFICvGZYIxEFSmsDAuMcFHhHXIMT z7zS17hTkMc9854kf76oVCy1F8Ahb9ZoAr3S0kqk9e8+egIkVv39b5+SYjv4iUN9eV91 SXI+emrT/I9JUpjmH5yzdXvjtpGJpORuQcokKEm5wkhBS+RjFPaInawUe/M3xrUF9n/0 pp+hOxwE+b9py9tjvFV2PzWpvfCc3PRQwBPOW3aiYU/+8b5KQsa2G1HrtffyTk/oHcgR MefaxGwPsv7ZRer2qnTEzsCE4yvMpGT0h6N8qQaUOMo1wAK+TbpvisdKykHI5STkcaca Q5YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=TBXOh+qCZb1AbvhplyZXyYZ1SSUAH9q1meg8o/qp39A=; b=slw/UtLaWTHjBrLevWPKmekxiAZPQmP5V+PGuEPSwwr9w+r2msEys5urDGNJrBPMci na6mEiWBCD3r+myxVRLR2a3Pgcq6LvoDwKMnK7WKCB3+M7mixjkVkAOBM2TsS2Us8Ivx sUz9t2kvx1qvaS9k8WWACK44u10z2twgU9xKcIwaWwQ40jqVsAYc68N+4YN/f2/t3bDK OQg3SMosw0yg4YKuZs1YdLK9pLEwvg3UeLbLERSihRYPioPRmXQVIkPpfm2Fuja+GLd1 AI/nhkY+KHKLfQw2BzTPsQhFV9mO1qkbvuP5fgHMnMecpfNjCraPnipEJidf0Oj7bJ1L 9rZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dxv12iw1; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 61ca2905ee7a..4d6a406f8dca 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -47,15 +47,15 @@ struct tsens_sensor { */ struct tsens_ops { /* mandatory callbacks */ - int (*init)(struct tsens_priv *); - int (*calibrate)(struct tsens_priv *); - int (*get_temp)(struct tsens_priv *, int, int *); + int (*init)(struct tsens_priv *priv); + int (*calibrate)(struct tsens_priv *priv); + int (*get_temp)(struct tsens_priv *priv, int i, int *temp); /* optional callbacks */ - int (*enable)(struct tsens_priv *, int); - void (*disable)(struct tsens_priv *); - int (*suspend)(struct tsens_priv *); - int (*resume)(struct tsens_priv *); - int (*get_trend)(struct tsens_priv *, int, enum thermal_trend *); + int (*enable)(struct tsens_priv *priv, int i); + void (*disable)(struct tsens_priv *priv); + int (*suspend)(struct tsens_priv *priv); + int (*resume)(struct tsens_priv *priv); + int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend); }; enum reg_list { @@ -111,10 +111,10 @@ struct tsens_priv { struct tsens_sensor sensor[0]; }; -char *qfprom_read(struct device *, const char *); -void compute_intercept_slope(struct tsens_priv *, u32 *, u32 *, u32); -int init_common(struct tsens_priv *); -int get_temp_common(struct tsens_priv *, int, int *); +char *qfprom_read(struct device *dev, const char *cname); +void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); +int init_common(struct tsens_priv *priv); +int get_temp_common(struct tsens_priv *priv, int i, int *temp); /* TSENS v1 targets */ extern const struct tsens_plat_data data_8916, data_8974, data_8960; From patchwork Thu Feb 7 10:49:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 157747 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp611528jaa; Thu, 7 Feb 2019 04:58:07 -0800 (PST) X-Google-Smtp-Source: AHgI3IY9hDMSy88uEHWvQ0X/unTDA4WOCrt/AV8meYeSRTD9FnE6cQT1o/+HmMs7tMYGMp5J+q57 X-Received: by 2002:a63:2501:: with SMTP id l1mr14429703pgl.144.1549544287648; Thu, 07 Feb 2019 04:58:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549544287; cv=none; d=google.com; s=arc-20160816; b=kqy2RZLEZ3xTcliKTf6ZBPV/TO6ZyPRql8nKPlnU3TVqQjjFpQuOvx7J4uvkjkFo7j hlMW0izKbMCrg9jIi5+7KB6lke/65HEUlzFIMfDoerx25jaP3lnvT8Nqqu41eMCiMGFA pVh+Q6Qr2REXiHtYcFHe/PvepwNGx/Bfaro2PaPHKGAGi+4q6halBCecfS5Pdb70wEUi OrikknpeBbOGysVHvTgYqi73n/7+jNTMlezPsPZo+q4Yap2rEv6mVuLHG5kWGWFLXWJc a+042DhJHLLQpseVn08LibgXTX3LPzrVFB8jV3dpFi/PSW+8Q9bbHwGNxJvcYAMXoaB5 p0eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=GQERaam7BX0uQrRP6UmIWBlFpeXRfuuGSf7vQIQdfq0=; b=s/FtdFugyn+Ik5SjMSpM7bhw/XbAkMY/jRUlkSnqln5FxoKDp0wu8slIt7kE4Zf3L/ 2ZU8FRIGMHaVXKF53XWLJsWISpQ5LEbVX+ySZwHO4+avBT3Xwz1pr7YNN3HEFyWvVIXA qGw3ER8mq1mlqeb6lnkiNiyPqM8GsGxK/vQZ3QxfrGuwACrbilQLOdhoKqrhWM5JRun3 yCoYAm5iz/r3zdVuUuULz5kXNzWIiHFE4GYZj7eF0pq5HKxm5fanHUsDIUuFe58fcnhO YLBLCIK5u00E/WTnn5MIrGwac9D4/hRt5RYVEGvL25x4XXMpn2djSiibKRJdkC2bzhjj 1UXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vJKRJiJI; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n3si9014712plk.328.2019.02.07.04.58.07; Thu, 07 Feb 2019 04:58:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vJKRJiJI; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726979AbfBGM6G (ORCPT + 15 others); Thu, 7 Feb 2019 07:58:06 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:41948 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727574AbfBGM6G (ORCPT ); Thu, 7 Feb 2019 07:58:06 -0500 Received: by mail-pg1-f194.google.com with SMTP id m1so4452195pgq.8 for ; Thu, 07 Feb 2019 04:58:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=GQERaam7BX0uQrRP6UmIWBlFpeXRfuuGSf7vQIQdfq0=; b=vJKRJiJIeiRit9jzYbDlSS4ecb//rSX/xIEZ19PqkbIUK6Nkr1r3z2CzV1r9vY5bzm oJpWEn39NJwtttdYmAKFoOZCbsEblrTUR1kFVKngcqyHxjnZf/sdqjIA81ZSmbuii79U oEvgSgPAlsqKyF8jLLJQr9yuzBx65hczyS+sAjkbR2R08uI9KLLdvHrqNSiHiYFbrNpb RHW+IxiprT038cV/t62wPiQsjx4S1Gy3PckhGuTD9X0dM9r+WpD/hQLs7ZwtqweAOBKC qO5dawb8IfWr2GpvMIYb6Cc2toQ686TzxOpjpERrTXTjj7pzrcBcqJZP6rCeByELGwEc Cwdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=GQERaam7BX0uQrRP6UmIWBlFpeXRfuuGSf7vQIQdfq0=; b=XJvrX5O8YcRIp0t9KKzdrzqUn2nV4AlZtXBS/nMGUqQRKJ0lQc8IkvnaX/plffkKko QIMxfg33kDJ84TFR/aqA2v6JsFaSqA1qyZn5I+IOdUJ5+xo/nOvAntB5oy2mpFchyjbz wgFw82dUfozCS+KJurEC2Ru9XRmed01Oq8upz/JKDGJvv7WVvJS2PczMMSGYv7H2KgSy Y4jR8YBEyf6fOWXH+ECMXf5Vnp83nGp8/+dadouhCJcvHhurUaZNQAq2Amu/jXGdmdVL PaJCNorSmn7p4Tcf1UkDtvQ6rr5VKvMUOrlLscPPZiwxSqz6bLaMOe37ybq+H4uxQZaD ZnjQ== X-Gm-Message-State: AHQUAubp+KFSMtSxr/qarvDEuF2loExGs78dUESytEo5H0xqxfGPE9nD FvNha5pm+HKYc/YvfSYRf5aYgQ== X-Received: by 2002:a63:111c:: with SMTP id g28mr14434796pgl.85.1549544284801; Thu, 07 Feb 2019 04:58:04 -0800 (PST) Received: from localhost ([2402:3a80:c80:4138:75dd:3900:1d90:762f]) by smtp.gmail.com with ESMTPSA id v70sm12338415pfa.152.2019.02.07.04.58.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 04:58:04 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v1 09/24] drivers: thermal: tsens: Merge tsens-8974 into tsens-v0_1 Date: Thu, 7 Feb 2019 16:19:27 +0530 Message-Id: <36047c52f0e3e49b797cd4c9a7c064f4b6689b98.1549525708.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org 8974 and 8916 have the same version of the TSENS IP. Merge the files to allow for better code reuse. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/Makefile | 2 +- drivers/thermal/qcom/tsens-8974.c | 236 ------------------------------ drivers/thermal/qcom/tsens-v0_1.c | 229 +++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.h | 8 +- 4 files changed, 236 insertions(+), 239 deletions(-) delete mode 100644 drivers/thermal/qcom/tsens-8974.c -- 2.17.1 diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 1f2fafd43dff..7fa3cadce760 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o tsens-8974.o tsens-8960.o tsens-v2.o +qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o tsens-8960.o tsens-v2.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o diff --git a/drivers/thermal/qcom/tsens-8974.c b/drivers/thermal/qcom/tsens-8974.c deleted file mode 100644 index 303157fd00be..000000000000 --- a/drivers/thermal/qcom/tsens-8974.c +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#include -#include "tsens.h" - -/* eeprom layout data for 8974 */ -#define BASE1_MASK 0xff -#define S0_P1_MASK 0x3f00 -#define S1_P1_MASK 0xfc000 -#define S2_P1_MASK 0x3f00000 -#define S3_P1_MASK 0xfc000000 -#define S4_P1_MASK 0x3f -#define S5_P1_MASK 0xfc0 -#define S6_P1_MASK 0x3f000 -#define S7_P1_MASK 0xfc0000 -#define S8_P1_MASK 0x3f000000 -#define S8_P1_MASK_BKP 0x3f -#define S9_P1_MASK 0x3f -#define S9_P1_MASK_BKP 0xfc0 -#define S10_P1_MASK 0xfc0 -#define S10_P1_MASK_BKP 0x3f000 -#define CAL_SEL_0_1 0xc0000000 -#define CAL_SEL_2 0x40000000 -#define CAL_SEL_SHIFT 30 -#define CAL_SEL_SHIFT_2 28 - -#define S0_P1_SHIFT 8 -#define S1_P1_SHIFT 14 -#define S2_P1_SHIFT 20 -#define S3_P1_SHIFT 26 -#define S5_P1_SHIFT 6 -#define S6_P1_SHIFT 12 -#define S7_P1_SHIFT 18 -#define S8_P1_SHIFT 24 -#define S9_P1_BKP_SHIFT 6 -#define S10_P1_SHIFT 6 -#define S10_P1_BKP_SHIFT 12 - -#define BASE2_SHIFT 12 -#define BASE2_BKP_SHIFT 18 -#define S0_P2_SHIFT 20 -#define S0_P2_BKP_SHIFT 26 -#define S1_P2_SHIFT 26 -#define S2_P2_BKP_SHIFT 6 -#define S3_P2_SHIFT 6 -#define S3_P2_BKP_SHIFT 12 -#define S4_P2_SHIFT 12 -#define S4_P2_BKP_SHIFT 18 -#define S5_P2_SHIFT 18 -#define S5_P2_BKP_SHIFT 24 -#define S6_P2_SHIFT 24 -#define S7_P2_BKP_SHIFT 6 -#define S8_P2_SHIFT 6 -#define S8_P2_BKP_SHIFT 12 -#define S9_P2_SHIFT 12 -#define S9_P2_BKP_SHIFT 18 -#define S10_P2_SHIFT 18 -#define S10_P2_BKP_SHIFT 24 - -#define BASE2_MASK 0xff000 -#define BASE2_BKP_MASK 0xfc0000 -#define S0_P2_MASK 0x3f00000 -#define S0_P2_BKP_MASK 0xfc000000 -#define S1_P2_MASK 0xfc000000 -#define S1_P2_BKP_MASK 0x3f -#define S2_P2_MASK 0x3f -#define S2_P2_BKP_MASK 0xfc0 -#define S3_P2_MASK 0xfc0 -#define S3_P2_BKP_MASK 0x3f000 -#define S4_P2_MASK 0x3f000 -#define S4_P2_BKP_MASK 0xfc0000 -#define S5_P2_MASK 0xfc0000 -#define S5_P2_BKP_MASK 0x3f000000 -#define S6_P2_MASK 0x3f000000 -#define S6_P2_BKP_MASK 0x3f -#define S7_P2_MASK 0x3f -#define S7_P2_BKP_MASK 0xfc0 -#define S8_P2_MASK 0xfc0 -#define S8_P2_BKP_MASK 0x3f000 -#define S9_P2_MASK 0x3f000 -#define S9_P2_BKP_MASK 0xfc0000 -#define S10_P2_MASK 0xfc0000 -#define S10_P2_BKP_MASK 0x3f000000 - -#define BKP_SEL 0x3 -#define BKP_REDUN_SEL 0xe0000000 -#define BKP_REDUN_SHIFT 29 - -#define BIT_APPEND 0x3 - -static int calibrate_8974(struct tsens_priv *priv) -{ - int base1 = 0, base2 = 0, i; - u32 p1[11], p2[11]; - int mode = 0; - u32 *calib, *bkp; - u32 calib_redun_sel; - - calib = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(calib)) - return PTR_ERR(calib); - - bkp = (u32 *)qfprom_read(priv->dev, "calib_backup"); - if (IS_ERR(bkp)) - return PTR_ERR(bkp); - - calib_redun_sel = bkp[1] & BKP_REDUN_SEL; - calib_redun_sel >>= BKP_REDUN_SHIFT; - - if (calib_redun_sel == BKP_SEL) { - mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT; - p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT; - p2[1] = (bkp[3] & S1_P2_BKP_MASK); - p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT; - p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT; - p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT; - p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT; - p2[6] = (calib[5] & S6_P2_BKP_MASK); - p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT; - p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT; - p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT; - p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT; - /* Fall through */ - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = bkp[0] & BASE1_MASK; - p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (bkp[1] & S4_P1_MASK); - p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT; - p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT; - p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT; - break; - } - } else { - mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT; - p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT; - p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT; - p2[2] = (calib[3] & S2_P2_MASK); - p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT; - p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT; - p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT; - p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT; - p2[7] = (calib[4] & S7_P2_MASK); - p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT; - p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT; - p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT; - /* Fall through */ - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = calib[0] & BASE1_MASK; - p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (calib[1] & S4_P1_MASK); - p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT; - p1[9] = (calib[2] & S9_P1_MASK); - p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT; - break; - } - } - - switch (mode) { - case ONE_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) - p1[i] += (base1 << 2) | BIT_APPEND; - break; - case TWO_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) { - p2[i] += base2; - p2[i] <<= 2; - p2[i] |= BIT_APPEND; - } - /* Fall through */ - case ONE_PT_CALIB2: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] += base1; - p1[i] <<= 2; - p1[i] |= BIT_APPEND; - } - break; - default: - for (i = 0; i < priv->num_sensors; i++) - p2[i] = 780; - p1[0] = 502; - p1[1] = 509; - p1[2] = 503; - p1[3] = 509; - p1[4] = 505; - p1[5] = 509; - p1[6] = 507; - p1[7] = 510; - p1[8] = 508; - p1[9] = 509; - p1[10] = 508; - break; - } - - compute_intercept_slope(priv, p1, p2, mode); - - return 0; -} - -static const struct tsens_ops ops_8974 = { - .init = init_common, - .calibrate = calibrate_8974, - .get_temp = get_temp_common, -}; - -const struct tsens_plat_data data_8974 = { - .num_sensors = 11, - .ops = &ops_8974, - .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, -}; diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 30909594b1cf..a6e26be1234f 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -39,6 +39,91 @@ #define MSM8916_CAL_SEL_MASK 0xe0000000 #define MSM8916_CAL_SEL_SHIFT 29 +/* eeprom layout data for 8974 */ +#define BASE1_MASK 0xff +#define S0_P1_MASK 0x3f00 +#define S1_P1_MASK 0xfc000 +#define S2_P1_MASK 0x3f00000 +#define S3_P1_MASK 0xfc000000 +#define S4_P1_MASK 0x3f +#define S5_P1_MASK 0xfc0 +#define S6_P1_MASK 0x3f000 +#define S7_P1_MASK 0xfc0000 +#define S8_P1_MASK 0x3f000000 +#define S8_P1_MASK_BKP 0x3f +#define S9_P1_MASK 0x3f +#define S9_P1_MASK_BKP 0xfc0 +#define S10_P1_MASK 0xfc0 +#define S10_P1_MASK_BKP 0x3f000 +#define CAL_SEL_0_1 0xc0000000 +#define CAL_SEL_2 0x40000000 +#define CAL_SEL_SHIFT 30 +#define CAL_SEL_SHIFT_2 28 + +#define S0_P1_SHIFT 8 +#define S1_P1_SHIFT 14 +#define S2_P1_SHIFT 20 +#define S3_P1_SHIFT 26 +#define S5_P1_SHIFT 6 +#define S6_P1_SHIFT 12 +#define S7_P1_SHIFT 18 +#define S8_P1_SHIFT 24 +#define S9_P1_BKP_SHIFT 6 +#define S10_P1_SHIFT 6 +#define S10_P1_BKP_SHIFT 12 + +#define BASE2_SHIFT 12 +#define BASE2_BKP_SHIFT 18 +#define S0_P2_SHIFT 20 +#define S0_P2_BKP_SHIFT 26 +#define S1_P2_SHIFT 26 +#define S2_P2_BKP_SHIFT 6 +#define S3_P2_SHIFT 6 +#define S3_P2_BKP_SHIFT 12 +#define S4_P2_SHIFT 12 +#define S4_P2_BKP_SHIFT 18 +#define S5_P2_SHIFT 18 +#define S5_P2_BKP_SHIFT 24 +#define S6_P2_SHIFT 24 +#define S7_P2_BKP_SHIFT 6 +#define S8_P2_SHIFT 6 +#define S8_P2_BKP_SHIFT 12 +#define S9_P2_SHIFT 12 +#define S9_P2_BKP_SHIFT 18 +#define S10_P2_SHIFT 18 +#define S10_P2_BKP_SHIFT 24 + +#define BASE2_MASK 0xff000 +#define BASE2_BKP_MASK 0xfc0000 +#define S0_P2_MASK 0x3f00000 +#define S0_P2_BKP_MASK 0xfc000000 +#define S1_P2_MASK 0xfc000000 +#define S1_P2_BKP_MASK 0x3f +#define S2_P2_MASK 0x3f +#define S2_P2_BKP_MASK 0xfc0 +#define S3_P2_MASK 0xfc0 +#define S3_P2_BKP_MASK 0x3f000 +#define S4_P2_MASK 0x3f000 +#define S4_P2_BKP_MASK 0xfc0000 +#define S5_P2_MASK 0xfc0000 +#define S5_P2_BKP_MASK 0x3f000000 +#define S6_P2_MASK 0x3f000000 +#define S6_P2_BKP_MASK 0x3f +#define S7_P2_MASK 0x3f +#define S7_P2_BKP_MASK 0xfc0 +#define S8_P2_MASK 0xfc0 +#define S8_P2_BKP_MASK 0x3f000 +#define S9_P2_MASK 0x3f000 +#define S9_P2_BKP_MASK 0xfc0000 +#define S10_P2_MASK 0xfc0000 +#define S10_P2_BKP_MASK 0x3f000000 + +#define BKP_SEL 0x3 +#define BKP_REDUN_SEL 0xe0000000 +#define BKP_REDUN_SHIFT 29 + +#define BIT_APPEND 0x3 + static int calibrate_8916(struct tsens_priv *priv) { int base0 = 0, base1 = 0, i; @@ -91,6 +176,138 @@ static int calibrate_8916(struct tsens_priv *priv) return 0; } +static int calibrate_8974(struct tsens_priv *priv) +{ + int base1 = 0, base2 = 0, i; + u32 p1[11], p2[11]; + int mode = 0; + u32 *calib, *bkp; + u32 calib_redun_sel; + + calib = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(calib)) + return PTR_ERR(calib); + + bkp = (u32 *)qfprom_read(priv->dev, "calib_backup"); + if (IS_ERR(bkp)) + return PTR_ERR(bkp); + + calib_redun_sel = bkp[1] & BKP_REDUN_SEL; + calib_redun_sel >>= BKP_REDUN_SHIFT; + + if (calib_redun_sel == BKP_SEL) { + mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; + mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; + + switch (mode) { + case TWO_PT_CALIB: + base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT; + p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT; + p2[1] = (bkp[3] & S1_P2_BKP_MASK); + p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT; + p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT; + p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT; + p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT; + p2[6] = (calib[5] & S6_P2_BKP_MASK); + p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT; + p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT; + p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT; + p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT; + /* Fall through */ + case ONE_PT_CALIB: + case ONE_PT_CALIB2: + base1 = bkp[0] & BASE1_MASK; + p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (bkp[1] & S4_P1_MASK); + p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT; + p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT; + p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT; + break; + } + } else { + mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; + mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; + + switch (mode) { + case TWO_PT_CALIB: + base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT; + p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT; + p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT; + p2[2] = (calib[3] & S2_P2_MASK); + p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT; + p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT; + p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT; + p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT; + p2[7] = (calib[4] & S7_P2_MASK); + p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT; + p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT; + p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT; + /* Fall through */ + case ONE_PT_CALIB: + case ONE_PT_CALIB2: + base1 = calib[0] & BASE1_MASK; + p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (calib[1] & S4_P1_MASK); + p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT; + p1[9] = (calib[2] & S9_P1_MASK); + p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT; + break; + } + } + + switch (mode) { + case ONE_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p1[i] += (base1 << 2) | BIT_APPEND; + break; + case TWO_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) { + p2[i] += base2; + p2[i] <<= 2; + p2[i] |= BIT_APPEND; + } + /* Fall through */ + case ONE_PT_CALIB2: + for (i = 0; i < priv->num_sensors; i++) { + p1[i] += base1; + p1[i] <<= 2; + p1[i] |= BIT_APPEND; + } + break; + default: + for (i = 0; i < priv->num_sensors; i++) + p2[i] = 780; + p1[0] = 502; + p1[1] = 509; + p1[2] = 503; + p1[3] = 509; + p1[4] = 505; + p1[5] = 509; + p1[6] = 507; + p1[7] = 510; + p1[8] = 508; + p1[9] = 509; + p1[10] = 508; + break; + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + static const struct tsens_ops ops_8916 = { .init = init_common, .calibrate = calibrate_8916, @@ -103,3 +320,15 @@ const struct tsens_plat_data data_8916 = { .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, .hw_ids = (unsigned int []){0, 1, 2, 4, 5 }, }; + +static const struct tsens_ops ops_8974 = { + .init = init_common, + .calibrate = calibrate_8974, + .get_temp = get_temp_common, +}; + +const struct tsens_plat_data data_8974 = { + .num_sensors = 11, + .ops = &ops_8974, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, +}; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 4d6a406f8dca..27b8f74829d9 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -116,8 +116,12 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo int init_common(struct tsens_priv *priv); int get_temp_common(struct tsens_priv *priv, int i, int *temp); -/* TSENS v1 targets */ -extern const struct tsens_plat_data data_8916, data_8974, data_8960; +/* TSENS target */ +extern const struct tsens_plat_data data_8960; + +/* TSENS v0.1 targets */ +extern const struct tsens_plat_data data_8916, data_8974; + /* TSENS v2 targets */ extern const struct tsens_plat_data data_8996, data_tsens_v2; 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[209.132.180.67]) by mx.google.com with ESMTP id a11si9338061pla.20.2019.02.07.04.56.19; Thu, 07 Feb 2019 04:56:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PKclIgRj; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726949AbfBGM4T (ORCPT + 15 others); Thu, 7 Feb 2019 07:56:19 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:35810 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726844AbfBGM4T (ORCPT ); Thu, 7 Feb 2019 07:56:19 -0500 Received: by mail-pl1-f196.google.com with SMTP id p8so4746376plo.2 for ; Thu, 07 Feb 2019 04:56:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=IMOq2Akho+4m31uQd4WeKnRvq63fThBL3U3/6BakR0U=; b=PKclIgRj5qFjo8HkiY9vUen1nTxxtJ/v8aVnsKPwXq9MJ6+0VZkc7lAT4jY7aokXG6 htrP6kt4lR4PwjHD3XcGchoGyxNuRWZJxfJbeMsXcweTXpOrm6ySHdA3ZwDrIknVSz8e VNxfsLquNary7T6P9pXTHNbMoN/KBPQUVFXeyqOAYV7hRv/Jc9WOwdBSw+UrG93FgrzS jwNd9vkjZTiazewwhNhkCo+mMBhcEut8o9zjJJVNHt+EAmBwvnCgesYHC5kQtzeqm8AE D8GHidEm7FKVk/h1PvY/gn9p+c2lgbdlDJXAqrxIcCn6wcgXMjrGlImuR1xW7tpT/PYr CWGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=IMOq2Akho+4m31uQd4WeKnRvq63fThBL3U3/6BakR0U=; b=dTGs1FF9rZrPlcSePcqFrphp3M30EVN67x9/7oFgcsqy+i4otqeuL5fDhYDcWhZInb rsVD9eKPx/B69IpJGxK7m16jiGG3xWf762bPgF4QXJN0+4ORpxQjL7ZLCkwQw89WifO7 Xl+pU/RIv++S32P/mrhqlQLn2pV6sP1DJ4cWfQcXRu4ofhoG7xD5/UETwWZ58nCp6XcI BFbKE3WF2JzYJvvkYM/LZBpBuQhiM+k4Batm9w7ogYETY1fWqCQUBCsEvBy9sx8G+Eb2 VH8JOzhkdRpsN3xcY5oQ8sKVFXJOoqN+7RfBV1r66WazpMrB5XjTe5Yu9xJVtdSaI/lr T6Ow== X-Gm-Message-State: AHQUAuY3yPbbJIIp575hEKXikgrBZRuJi8MV2L4dI9iIplGgGXd8h7rG Hc7X9/XQuVDr5pssBTNTt6/gzQ== X-Received: by 2002:a17:902:2ec1:: with SMTP id r59mr16575570plb.254.1549544178148; Thu, 07 Feb 2019 04:56:18 -0800 (PST) Received: from localhost ([2402:3a80:c80:4138:75dd:3900:1d90:762f]) by smtp.gmail.com with ESMTPSA id n186sm11863521pfn.137.2019.02.07.04.56.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 04:56:17 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v1 14/24] drivers: thermal: tsens: Add new operation to check if a sensor is enabled Date: Thu, 7 Feb 2019 16:19:32 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org is_sensor_enabled() checks if the sensors are enabled on this platform. It is possible that the SoC might choose not to enable all the sensors that the IP block is capable of supporting. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 14 ++++++++++++++ drivers/thermal/qcom/tsens-v0_1.c | 1 + drivers/thermal/qcom/tsens-v2.c | 1 + drivers/thermal/qcom/tsens.c | 5 +++++ drivers/thermal/qcom/tsens.h | 1 + 5 files changed, 22 insertions(+) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 39cd5733fd44..020409d8daf0 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -69,6 +69,20 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, } } +bool is_sensor_enabled(struct tsens_priv *priv, u32 hw_id) +{ + u32 val; + int ret; + + if ((hw_id > (priv->num_sensors - 1)) || (hw_id < 0)) + return -EINVAL; + ret = regmap_field_read(priv->rf[SENSOR_EN], &val); + if (ret) + return ret; + + return val & (1 << hw_id); +} + static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 02907751c201..ad1052e05e45 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -332,6 +332,7 @@ const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { /* CTRL_OFFSET */ [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13), /* ----- TM ------ */ /* UPPER_LOWER_INTERRUPT_CTRL */ diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 962e47c54dca..e0aac59d72ec 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -99,6 +99,7 @@ const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* CTRL_OFF */ [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 18), /* ----- TM ------ */ /* INTERRUPT ENABLE */ diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 057b33353ba3..fc44cac31fa5 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -82,6 +82,11 @@ static int tsens_register(struct tsens_priv *priv) struct thermal_zone_device *tzd; for (i = 0; i < priv->num_sensors; i++) { + if (!is_sensor_enabled(priv, priv->sensor[i].hw_id)) { + dev_err(priv->dev, "sensor %d: disabled\n", + priv->sensor[i].hw_id); + continue; + } priv->sensor[i].priv = priv; priv->sensor[i].id = i; tzd = devm_thermal_zone_of_sensor_register(priv->dev, i, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 20d89f8a6c3e..da4cfb23dfe9 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -254,6 +254,7 @@ char *qfprom_read(struct device *dev, const char *cname); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); int init_common(struct tsens_priv *priv); int get_temp_common(struct tsens_priv *priv, int i, int *temp); +bool is_sensor_enabled(struct tsens_priv *priv, u32 hw_id); /* TSENS target */ extern const struct tsens_plat_data data_8960; From patchwork Thu Feb 7 10:49:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 157735 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp610213jaa; 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[209.132.180.67]) by mx.google.com with ESMTP id q2si8787138pll.343.2019.02.07.04.56.34; Thu, 07 Feb 2019 04:56:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XvkPpY9t; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727261AbfBGM4e (ORCPT + 15 others); Thu, 7 Feb 2019 07:56:34 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:39062 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727138AbfBGM4e (ORCPT ); Thu, 7 Feb 2019 07:56:34 -0500 Received: by mail-pl1-f193.google.com with SMTP id 101so4747600pld.6 for ; Thu, 07 Feb 2019 04:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=QM6AyIeFhqZF+Crf5VtmkjaF1HKzGjJgsV+pTA3g5qA=; b=XvkPpY9t/wv6a6ikREXghG0cLkZ/Cv5jBfBIgOU7lwF5usRmxlds3hPtbFN9LncouH I8o9F6YztPDf39ZbYzuGoTPaHfqfdDCkMnvrLDG7hHNIdjErE1N2hqacQQPWysixODmp tOVep90ZPAB6fw8nlvMxi7tdUKPcxgxigcf2/q1m2L7LGcBwaSHyGZeOeHfBQxAuc0kT 299c9OLb6K/jgaJfdK6S1unB9SE1vaIIoURghoEcLdfOgv5mqbqhFtW8yDhGUdCwifPP HdUm2CZ63I3SWbCFjGitXsdKrY/wI8SuqoZSTv9Jbi2eD675PDPTq+lBPUM4WAVvbWBt /56Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=QM6AyIeFhqZF+Crf5VtmkjaF1HKzGjJgsV+pTA3g5qA=; b=sCkYa2ZaCO4jxjaGwhdO5JjkXS6RPHiic0yI/vAoOEPv3JHtiBN+V3OuTInjrtDjVH WRhozegkYNE7syZue9oOgLdvaJpdEtTTa4WhkBef+IM9BnzRprheL4cakBSlR2rrtWhV jKkp8GDGAZe6TQQ5v9H91ip93COFkc2xiywzOMCQdnFqow+MdDfsI9B9ptltN5VHmRfD StVldsl0Ikpo8qKirZgkuhD3QdfAtYI9Mt+CbAJmpOGWKtAUmSCZo2eHlvKYOHhzPeLD jZObk3gIagYyBq5hSmKy63n7CPo+XFzMSPmkHPeXszq3pAuQu+BZDDHVjY9AFCCrGaO8 J/Mw== X-Gm-Message-State: AHQUAuYzXzHeuWVoIWHbrgkYcjUfmZ4B6xfOfq3MsQACvnlgBaTwh8bJ mkwuEyAa+NnpuhR3GPJTuFknag== X-Received: by 2002:a17:902:622:: with SMTP id 31mr16034547plg.171.1549544193284; Thu, 07 Feb 2019 04:56:33 -0800 (PST) Received: from localhost ([2402:3a80:c80:4138:75dd:3900:1d90:762f]) by smtp.gmail.com with ESMTPSA id c7sm14985464pfa.24.2019.02.07.04.56.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 04:56:32 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v1 16/24] drivers: thermal: tsens: Introduce IP-specific max_sensor count Date: Thu, 7 Feb 2019 16:19:34 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The IP can support 'm' sensors while the platform can enable 'n' sensors of the 'm' where n <= m. Track maximum sensors supported by the IP so that we can correctly track what subset of the sensors are supported on the platform. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 4 ++-- drivers/thermal/qcom/tsens-v0_1.c | 1 + drivers/thermal/qcom/tsens-v2.c | 1 + drivers/thermal/qcom/tsens.h | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 020409d8daf0..d981effed493 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -208,13 +208,13 @@ int __init init_common(struct tsens_priv *priv) return PTR_ERR(priv->rf[SENSOR_EN]); /* now alloc regmap_fields in tm_map */ - for (i = 0, j = LAST_TEMP_0; i < priv->num_sensors; i++, j++) { + for (i = 0, j = LAST_TEMP_0; i < priv->feat->max_sensors; i++, j++) { priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[j]); if (IS_ERR(priv->rf[j])) return PTR_ERR(priv->rf[j]); } - for (i = 0, j = VALID_0; i < priv->num_sensors; i++, j++) { + for (i = 0, j = VALID_0; i < priv->feat->max_sensors; i++, j++) { priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[j]); if (IS_ERR(priv->rf[j])) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index ad1052e05e45..4f17b4b781b0 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -324,6 +324,7 @@ const struct tsens_features tsens_v0_1_feat = { .crit_int = 0, .adc = 1, .srot_split = 1, + .max_sensors = 11, }; /* v0.1: 8916, 8974 */ diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index e0aac59d72ec..8052266447f5 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -88,6 +88,7 @@ const struct tsens_features tsens_v2_feat = { .crit_int = 1, .adc = 0, .srot_split = 1, + .max_sensors = 16, }; const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index e0c1ca1a7467..9db89dffb719 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -189,12 +189,14 @@ enum regfield_ids { * @adc: do the sensors only output adc code (instead of temperature)? * @srot_split: does the IP neatly splits the register space into SROT and TM, * with SROT only being available to secure boot firmware? + * @max_sensors: maximum sensors supported by this version of the IP */ struct tsens_features { unsigned int ver_info:1; unsigned int crit_int:1; unsigned int adc:1; unsigned int srot_split:1; + unsigned int max_sensors; }; /** From patchwork Thu Feb 7 10:49:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 157736 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp610622jaa; Thu, 7 Feb 2019 04:57:01 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia2WVEhPN10P4WKmtLaTP5w+xg4TGT/biPC5/yney435GZ7R6Pl3tIoV0j97sr6E3/a3/wf X-Received: by 2002:a65:64c8:: with SMTP id t8mr4291966pgv.31.1549544221578; Thu, 07 Feb 2019 04:57:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549544221; cv=none; d=google.com; s=arc-20160816; b=V47tCUNSjTzWXGdy/r3WgPcRyzqUflhS7xay6R+5i4mg7HA5gWIUMUOV6MDkIjFz5x /YJkNuwhdMkHwks5Ca2CcKTXPN4NmoYpQKDrkr48IZhWVJVQOPjn2I/ba3Tp26IOmSqZ XfMCZ5T19QFMFkPcEmqih/MP1mMh/PqRCQBXBW3lEYUWRbtEjRRHkHcyUmFRDRRL/v74 Hly2JpvGPKyIvk3+athmuOVSq1z6LcdSb6O7yjbWRtPPcssyh0Gb97c9cng1R25DMWY1 I3fLNz4JL/6yD5YGpknMypFZDswXZShX/1wgw9dt53zb+2efN6lnjGMidPQQ0UPJY+aw rkHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=mSp0BJaAkKriZPizUSoQw+VR9SnVdso3SWK1GQEdFzY=; b=vlYQ94IfHJpduvP+kksgKfEFfMNFU6WCE1tX9huUEvC1mrP4QBblno+wGI4W1KdhJ1 +3jNzY8rU7NkEw+E2iB2E43Lpujg9x9Ud9I4hGVQl9hY/5NbQRcweQhsV1QeYT8P1suc z7y6qVsHe/Ec/OJ0BAkbCBZ1aafP7/58591bpCeae47PbZJv2ahBfU2uuP7TmFj6jKDn /wakp+RWLe+I5BLSarUje61L+DFwnVfVho6rOthvZP+3TrfB2G2XV6ql4KRwOvttL93T rxe/zEfu/6plsHBgz7ATxoE9l8kq/3T7qOiLUcXdXJaQrNxJaMTkueN2LbCyqkN6bJ3t p8Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rw4Veysd; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j91si3759161pld.395.2019.02.07.04.57.01; Thu, 07 Feb 2019 04:57:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rw4Veysd; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727211AbfBGM5A (ORCPT + 15 others); Thu, 7 Feb 2019 07:57:00 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:42898 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727173AbfBGM5A (ORCPT ); Thu, 7 Feb 2019 07:57:00 -0500 Received: by mail-pg1-f194.google.com with SMTP id d72so4449875pga.9 for ; Thu, 07 Feb 2019 04:56:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=mSp0BJaAkKriZPizUSoQw+VR9SnVdso3SWK1GQEdFzY=; b=Rw4VeysdYDxv46ohT/hQhRZ61k/cyvNP2LNx3OQuYGCjF6+NpvEGujKlN1blLXLjZr SavbJH9YLLXqOeQEbyAhBTX57keBIhBZFLYmqFBWd4Q3t4rAuy/jvjhQMRZZiy6JQJnW onbViFZNGbmr1Pv4AO7/DN5T9SxP5uvvRZ4Q3COF9RbvCnYlL74oQe9IzyFTljMUAQTM YxdBrngtI98QAfWZiI6sHzXRzxWrQ0oZYfUCRvif/s6i44V5D32clZtKy8bR8zyJLKcm ww9JST7zgyGPimH8hUVLBlOHbSJq9O3mMDj3FyJ0ODxRHMQV4y3RrXvq+rD5OuNs509a pbDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=mSp0BJaAkKriZPizUSoQw+VR9SnVdso3SWK1GQEdFzY=; b=o62QUK++8/Wh4ERjc3dKMZc/LQLG2po6Vb6z7c1atbv7W1B0VBqgV/1hFq7pTaAn4s b1d5NcmjTkwUm11qQ4H9Y81CC6/RBRbR3ViiGqU1UShAsJDOSLKXoA9Q6jxiYjUKUgOM EBlGMspkeAVTOgz2UHeiZhgXd7mDi5x21GXa3BYBj7T+iXtL4P6oDdCJba7biCPxrroS n65/SZ6FeIqox4OGoVy/OxsbeOX79gUXRz5bpksIvUCAN4s7Hq/cJQk/7YC1Ess1Yy90 A47adkjWcPgGBDV3U8J1Wo85drEVd3ikuvSeAXkIZ/0lRI91zoG7XPm3kIJL3FeJBAMX CxMA== X-Gm-Message-State: AHQUAubE/fnWaE6F5HvqSTqCxLDbUgUOyd25C8kXMWOVUP/a3hAyyNsO 8yCTGika9e+AYUZ/8LE0Oe7Vkg== X-Received: by 2002:a63:2406:: with SMTP id k6mr14174003pgk.229.1549544219356; Thu, 07 Feb 2019 04:56:59 -0800 (PST) Received: from localhost ([2402:3a80:c80:4138:75dd:3900:1d90:762f]) by smtp.gmail.com with ESMTPSA id z14sm10034958pgv.47.2019.02.07.04.56.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 04:56:58 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v1 17/24] drivers: thermal: tsens: simplify get_temp_tsens_v2 routine Date: Thu, 7 Feb 2019 16:19:35 +0530 Message-Id: <9ee687bdeb1c0529038be823947da02f7d368f53.1549525708.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The current implementation is based on an algorithm published in the docs. Instead of reading the temperature thrice w/o any explanation, improve the algorithm. This will become the basis for a common get_temp routine in the future. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-v2.c | 55 ++++++++++----------------------- 1 file changed, 17 insertions(+), 38 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 8052266447f5..0ea93b89bc65 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -25,58 +25,37 @@ #define TM_Sn_STATUS_OFF 0x00a0 #define TM_TRDY_OFF 0x00e4 -#define LAST_TEMP_MASK 0xfff - -static int get_temp_tsens_v2(struct tsens_priv *priv, int id, int *temp) +static int get_temp_tsens_v2(struct tsens_priv *priv, int i, int *temp) { - struct tsens_sensor *s = &priv->sensor[id]; + struct tsens_sensor *s = &priv->sensor[i]; u32 temp_idx = LAST_TEMP_0 + s->hw_id; u32 valid_idx = VALID_0 + s->hw_id; - u32 last_temp = 0, last_temp2 = 0, last_temp3 = 0, valid; + u32 last_temp = 0, valid, mask; int ret; - ret = regmap_field_read(priv->rf[temp_idx], &last_temp); - if (ret) - return ret; - ret = regmap_field_read(priv->rf[valid_idx], &valid); if (ret) return ret; - - if (valid) - goto done; - - /* Try a second time */ - ret = regmap_field_read(priv->rf[valid_idx], &valid); - if (ret) - return ret; - ret = regmap_field_read(priv->rf[temp_idx], &last_temp2); - if (ret) - return ret; - if (valid) { - last_temp = last_temp2; - goto done; + while (!valid) { + /* Valid bit is 0 for 6 AHB clock cycles. + * At 19.2MHz, 1 AHB clock is ~60ns. + * We should enter this loop very, very rarely. + */ + ndelay(400); + ret = regmap_field_read(priv->rf[valid_idx], &valid); + if (ret) + return ret; } - /* Try a third/last time */ - ret = regmap_field_read(priv->rf[valid_idx], &valid); - if (ret) - return ret; - ret = regmap_field_read(priv->rf[temp_idx], &last_temp3); + /* Valid bit is set, OK to read the temperature */ + ret = regmap_field_read(priv->rf[temp_idx], &last_temp); if (ret) return ret; - if (valid) { - last_temp = last_temp3; - goto done; - } - if (last_temp == last_temp2) - last_temp = last_temp2; - else if (last_temp2 == last_temp3) - last_temp = last_temp3; -done: + mask = GENMASK(priv->fields[LAST_TEMP_0].msb, + priv->fields[LAST_TEMP_0].lsb); /* Convert temperature from deciCelsius to milliCelsius */ - *temp = sign_extend32(last_temp, fls(LAST_TEMP_MASK) - 1) * 100; + *temp = sign_extend32(last_temp, fls(mask) - 1) * 100; return 0; } From patchwork Thu Feb 7 10:49:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 157740 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp610946jaa; Thu, 7 Feb 2019 04:57:24 -0800 (PST) X-Google-Smtp-Source: AHgI3IaiSp38M8FXRcWslHZMu7H658N4+24fRHuuU6xqKiH9ewCazHPMG/B3Ppy0Bwfz/p+Zaa5P X-Received: by 2002:a63:f047:: with SMTP id s7mr14618205pgj.441.1549544244373; Thu, 07 Feb 2019 04:57:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549544244; cv=none; d=google.com; s=arc-20160816; b=Ji9YW6FCl7/2Y2Q1YnYyRHVrrlIhf0EPo8B8dp+FfrNNXD3LDkdZb25+Ss1tE13zQe zkB354mL9N8Ofaph8PW1ytfrlzEFtaJP9aRB9J9s6LN1MHjLr5roT9jrmkC0hFmA2/wq 5R9IC7E9buHC3FH/D3fZtpiQe4zvYKEq66eSeHZaAjXN5WRCVQYBgwwf0+TfEdUaaMOG V1C+yZPq0WS4ulGQ3uXGtcJQkgMIbYANESMOOvUacXb0RBPXyAkrcomFZnnTyS1q+fNR zqAWHygQi/wgbKXH4BQOmJ6Cv3nx117huW1hslphKNPI75UqovZlGLaazQgYTGJNI3Wc SgIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=6PCi5eYMw4qWyRgkEj4qId78p2VfZS5nls7Zkts8vCY=; b=xisaPT9dN3AYSlN6yn8aSWuiCM6qcsA7MEaqbAB2hLKkmOKlidbxNtMbLvh6LuTW88 b5iPc0Qz38ERtW2CiaMem0g2DogwWf8NRWl9/FAbJYcrP5RANtwIslEeHNWqk7XcW499 +B5Ve9Mm8uhpGHpfBYqjiN/aj91S5TgEJC7GKculXqFUSxHU+G3iDlkcTRJ6oBtrw4nu BsDtTwBngHjmXLqRvSovaQLXCIGZlME0LoWRX6BiqQpZGYlt2K4GYTZSMgeem8+4DneV afqtHCGK7BcLq3LdIIm3cxltusg53ganBIbO1/vRYXTanuuGIKYmfEg3fyAk68goQNv8 Y7YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aQatSRbr; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c8si9335634pfe.243.2019.02.07.04.57.24; Thu, 07 Feb 2019 04:57:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aQatSRbr; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727236AbfBGM5X (ORCPT + 15 others); Thu, 7 Feb 2019 07:57:23 -0500 Received: from mail-pf1-f194.google.com ([209.85.210.194]:42265 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727139AbfBGM5W (ORCPT ); Thu, 7 Feb 2019 07:57:22 -0500 Received: by mail-pf1-f194.google.com with SMTP id m6so1296404pfa.9 for ; Thu, 07 Feb 2019 04:57:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=6PCi5eYMw4qWyRgkEj4qId78p2VfZS5nls7Zkts8vCY=; b=aQatSRbrB0FweDebRpfFc5vyG9K5I4A7aB2gXEhpn/MmW4sqMtWMHxbPd6DNrUWd2r gJLuen5AXOAU/FuZjaEQXrgallfcgKvbbatF2jtFAn3DphuGI+ROMMAbzeh4O8Y+RITk DqDdZWZ4ys9UQUDFidhZO55oTmfv2eyNZBfpjYo1nNBycPUBjTruOCTqx3i2hX/rpJ8X NZWbJ+YZxZ5l2qSMKgkh1VzDsBdbmgs+elQg7iq4+lCEC5P2yYc6Uimg7LHltDkVcXt7 k8uAISCgTAZP3c1a6pE9qmqj8ck7qI5/OISGlenkjtHBFHO+8NYJFB77Xr70AbjLfvIJ c6pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=6PCi5eYMw4qWyRgkEj4qId78p2VfZS5nls7Zkts8vCY=; b=tQ8czCYdvyQ4uZirFiqacx+ntY4i5EbY8qJSDhlcDkXD3idZ9O6xeKdmsfgyjNzvF3 XpDDnAHpa+ITBnr/0lL/rC/75cAKaxAEa9xKHCAm0NnfX2J4yZsxjD77mrpNm05pvvIr 1FjmNp25g0exklTer30nGyutNC3rC1Kr5c+lhpTR2zcg8yu8yvYZDOJeWGB7CylyQG5d S7k4FALfHv0ZI+DOW2Km+fDNOQWv8fE8Wr7t+oTeBtHxoOixiLB9O+i7p1ivaiXrMIOu kaLsiDolg0qbXzsvs+/bOXInkErsBHxOXLNQqMFLSK/LFKyPEBrpfEBSueetTxGrBbGO 6wMg== X-Gm-Message-State: AHQUAuZAoXYzFY8TXCBkYx5efdp8PWe1WOGKN4fuB5Q5oarrEeQXKRRU CDmeAlHP2P8ZMH+aji2wS5AXTg== X-Received: by 2002:a65:490e:: with SMTP id p14mr10029555pgs.373.1549544241144; Thu, 07 Feb 2019 04:57:21 -0800 (PST) Received: from localhost ([2402:3a80:c80:4138:75dd:3900:1d90:762f]) by smtp.gmail.com with ESMTPSA id q75sm14915389pfa.38.2019.02.07.04.57.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Feb 2019 04:57:20 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v1 21/24] drivers: thermal: tsens: Add generic support for TSENS v1 IP Date: Thu, 7 Feb 2019 16:19:39 +0530 Message-Id: <8ecbfecbcd509b6285b8b74d217c17f118cf6816.1549525708.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4 of the TSENS IP, functionality for which is encapsulated inside the qcom,tsens-v1 compatible. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/Makefile | 4 +- drivers/thermal/qcom/tsens-v1.c | 229 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 + drivers/thermal/qcom/tsens.h | 3 + 4 files changed, 238 insertions(+), 1 deletion(-) create mode 100644 drivers/thermal/qcom/tsens-v1.c -- 2.17.1 diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 7fa3cadce760..fc6fe50cdde4 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,3 +1,5 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o tsens-8960.o tsens-v2.o + +qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \ + tsens-8960.o tsens-v2.o tsens-v1.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c new file mode 100644 index 000000000000..417e2c2de1a1 --- /dev/null +++ b/drivers/thermal/qcom/tsens-v1.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Limited + */ + +#include +#include +#include +#include "tsens.h" + +/* ----- SROT ------ */ +#define SROT_HW_VER_OFF 0x0000 +#define SROT_CTRL_OFF 0x0004 + +/* ----- TM ------ */ +#define TM_INT_EN_OFF 0x0000 +#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004 +#define TM_Sn_STATUS_OFF 0x0044 +#define TM_TRDY_OFF 0x0084 + +/* eeprom layout data for qcs404/405 (v1) */ +#define BASE0_MASK 0x000007f8 +#define BASE1_MASK 0x0007f800 +#define BASE0_SHIFT 3 +#define BASE1_SHIFT 11 + +#define S0_P1_MASK 0x0000003f +#define S1_P1_MASK 0x0003f000 +#define S2_P1_MASK 0x3f000000 +#define S3_P1_MASK 0x000003f0 +#define S4_P1_MASK 0x003f0000 +#define S5_P1_MASK 0x0000003f +#define S6_P1_MASK 0x0003f000 +#define S7_P1_MASK 0x3f000000 +#define S8_P1_MASK 0x000003f0 +#define S9_P1_MASK 0x003f0000 + +#define S0_P2_MASK 0x00000fc0 +#define S1_P2_MASK 0x00fc0000 +#define S2_P2_MASK_1_0 0xc0000000 +#define S2_P2_MASK_5_2 0x0000000f +#define S3_P2_MASK 0x0000fc00 +#define S4_P2_MASK 0x0fc00000 +#define S5_P2_MASK 0x00000fc0 +#define S6_P2_MASK 0x00fc0000 +#define S7_P2_MASK_1_0 0xc0000000 +#define S7_P2_MASK_5_2 0x0000000f +#define S8_P2_MASK 0x0000fc00 +#define S9_P2_MASK 0x0fc00000 + +#define S0_P1_SHIFT 0 +#define S0_P2_SHIFT 6 +#define S1_P1_SHIFT 12 +#define S1_P2_SHIFT 18 +#define S2_P1_SHIFT 24 +#define S2_P2_SHIFT_1_0 30 + +#define S2_P2_SHIFT_5_2 0 +#define S3_P1_SHIFT 4 +#define S3_P2_SHIFT 10 +#define S4_P1_SHIFT 16 +#define S4_P2_SHIFT 22 + +#define S5_P1_SHIFT 0 +#define S5_P2_SHIFT 6 +#define S6_P1_SHIFT 12 +#define S6_P2_SHIFT 18 +#define S7_P1_SHIFT 24 +#define S7_P2_SHIFT_1_0 30 + +#define S7_P2_SHIFT_5_2 0 +#define S8_P1_SHIFT 4 +#define S8_P2_SHIFT 10 +#define S9_P1_SHIFT 16 +#define S9_P2_SHIFT 22 + +#define CAL_SEL_MASK 7 +#define CAL_SEL_SHIFT 0 + +static int calibrate_v1(struct tsens_priv *priv) +{ + u32 base0 = 0, base1 = 0; + u32 p1[10], p2[10]; + u32 mode = 0, lsb = 0, msb = 0; + u32 *qfprom_cdata; + int i; + + qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(qfprom_cdata)) + return PTR_ERR(qfprom_cdata); + + mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + switch (mode) { + case TWO_PT_CALIB: + base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; + p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; + p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; + msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; + p2[2] = msb << 2 | lsb; + p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; + p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; + p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; + p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; + msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; + p2[7] = msb << 2 | lsb; + p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; + p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; + for (i = 0; i < priv->num_sensors; i++) + p2[i] = ((base1 + p2[i]) << 2); + /* Fall through */ + case ONE_PT_CALIB2: + base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; + p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; + p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; + p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; + for (i = 0; i < priv->num_sensors; i++) + p1[i] = (((base0) + p1[i]) << 2); + break; + default: + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + break; + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + +/* v1.x: qcs404,405 */ + +const struct tsens_features tsens_v1_feat = { + .ver_info = 1, + .crit_int = 0, + .adc = 1, + .srot_split = 1, + .max_sensors = 11, +}; + +const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { + /* ----- SROT ------ */ + /* VERSION */ + [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31), + [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27), + [VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15), + /* CTRL_OFFSET */ + [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), + [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13), + + /* ----- TM ------ */ + /* UPPER_LOWER_INTERRUPT_CTRL */ + [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* Sn_UPPER_LOWER_STATUS_CTRL */ + REG_BANK(LOW_THRESH, 0, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_BANK(LOW_THRESH, 1, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 4, 0, 9), + REG_BANK(LOW_THRESH, 2, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 8, 0, 9), + REG_BANK(LOW_THRESH, 3, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 12, 0, 9), + REG_BANK(LOW_THRESH, 4, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 16, 0, 9), + REG_BANK(LOW_THRESH, 5, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 20, 0, 9), + REG_BANK(LOW_THRESH, 6, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 24, 0, 9), + REG_BANK(LOW_THRESH, 7, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 28, 0, 9), + REG_BANK(LOW_THRESH, 8, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 32, 0, 9), + REG_BANK(LOW_THRESH, 9, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 36, 0, 9), + REG_BANK(LOW_THRESH, 10, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 40, 0, 9), + REG_BANK(UP_THRESH, 0, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + REG_BANK(UP_THRESH, 1, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 4, 10, 19), + REG_BANK(UP_THRESH, 2, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 8, 10, 19), + REG_BANK(UP_THRESH, 3, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 12, 10, 19), + REG_BANK(UP_THRESH, 4, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 16, 10, 19), + REG_BANK(UP_THRESH, 5, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 20, 10, 19), + REG_BANK(UP_THRESH, 6, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 24, 10, 19), + REG_BANK(UP_THRESH, 7, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 28, 10, 19), + REG_BANK(UP_THRESH, 8, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 32, 10, 19), + REG_BANK(UP_THRESH, 9, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 36, 10, 19), + REG_BANK(UP_THRESH, 10, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF + 40, 10, 19), + /* Sn_STATUS */ + REG_BANK(LAST_TEMP, 0, TM_Sn_STATUS_OFF, 0, 9), + REG_BANK(LAST_TEMP, 1, TM_Sn_STATUS_OFF + 4, 0, 9), + REG_BANK(LAST_TEMP, 2, TM_Sn_STATUS_OFF + 8, 0, 9), + REG_BANK(LAST_TEMP, 3, TM_Sn_STATUS_OFF + 12, 0, 9), + REG_BANK(LAST_TEMP, 4, TM_Sn_STATUS_OFF + 16, 0, 9), + REG_BANK(LAST_TEMP, 5, TM_Sn_STATUS_OFF + 20, 0, 9), + REG_BANK(LAST_TEMP, 6, TM_Sn_STATUS_OFF + 24, 0, 9), + REG_BANK(LAST_TEMP, 7, TM_Sn_STATUS_OFF + 28, 0, 9), + REG_BANK(LAST_TEMP, 8, TM_Sn_STATUS_OFF + 32, 0, 9), + REG_BANK(LAST_TEMP, 9, TM_Sn_STATUS_OFF + 36, 0, 9), + REG_BANK(LAST_TEMP, 10, TM_Sn_STATUS_OFF + 40, 0, 9), + REG_BANK(VALID, 0, TM_Sn_STATUS_OFF, 14, 14), + REG_BANK(VALID, 1, TM_Sn_STATUS_OFF + 4, 14, 14), + REG_BANK(VALID, 2, TM_Sn_STATUS_OFF + 8, 14, 14), + REG_BANK(VALID, 3, TM_Sn_STATUS_OFF + 12, 14, 14), + REG_BANK(VALID, 4, TM_Sn_STATUS_OFF + 16, 14, 14), + REG_BANK(VALID, 5, TM_Sn_STATUS_OFF + 20, 14, 14), + REG_BANK(VALID, 6, TM_Sn_STATUS_OFF + 24, 14, 14), + REG_BANK(VALID, 7, TM_Sn_STATUS_OFF + 28, 14, 14), + REG_BANK(VALID, 8, TM_Sn_STATUS_OFF + 32, 14, 14), + REG_BANK(VALID, 9, TM_Sn_STATUS_OFF + 36, 14, 14), + REG_BANK(VALID, 10, TM_Sn_STATUS_OFF + 40, 14, 14), + /* TRDY */ + [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), +}; + +static const struct tsens_ops ops_generic_v1 = { + .init = init_common, + .calibrate = calibrate_v1, + .get_temp = get_temp_tsens_valid, +}; + +const struct tsens_plat_data data_tsens_v1 = { + .ops = &ops_generic_v1, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index fc44cac31fa5..36b0b52db524 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -63,6 +63,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, + }, { + .compatible = "qcom,tsens-v1", + .data = &data_tsens_v1, }, { .compatible = "qcom,tsens-v2", .data = &data_tsens_v2, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 4b3d71b26c97..4ed07e607cbc 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -265,6 +265,9 @@ extern const struct tsens_plat_data data_8960; /* TSENS v0.1 targets */ extern const struct tsens_plat_data data_8916, data_8974; +/* TSENS v1 targets */ +extern const struct tsens_plat_data data_tsens_v1; + /* TSENS v2 targets */ extern const struct tsens_plat_data data_8996, data_tsens_v2; From patchwork Thu Feb 7 10:49:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 157743 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp611189jaa; Thu, 7 Feb 2019 04:57:43 -0800 (PST) X-Google-Smtp-Source: AHgI3IbfoXJxMCxh2DKVCOuB5UTjxZn9SF7+kCx3fYfQnw4uA6aaXi3SBzLjXAF/63SX8HmG0Mki X-Received: by 2002:a65:40ca:: with SMTP id u10mr14772243pgp.321.1549544262980; Thu, 07 Feb 2019 04:57:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549544262; cv=none; d=google.com; s=arc-20160816; b=sWbEiFDARINroDtgSdpDO2Vy2Jkwjx5rIc4XJw6IcuXTlFE63xDCGGhkjpbGtaDTNJ vZ4LmYeaJJ/6brxFtde5nNTi7tXXyKVUwgYlnxWVG9NE1H7dLth1k3KoA8tWA4swXOdc yNnT3FiYudP06GfDUGBFbFYGQaGRVHsRTWyD4pZ4PdE2M6PSFRdyOwsgPN/barw/vf7Y Pi77Mb9h/SSqZA0wAkzFwpkFj9J4mjowGqpPTM0RYJ8DNdXcEhTtzRqNFkjbMK4qv8Hw T/602tqNOTTHNzgqub9gotTu/YERmIYHQRMqn47jgrtgz8lOmZ9kZJZ0iUZyj8onvbp0 36bw== ARC-Message-Signature: i=1; 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Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 5 ----- drivers/thermal/qcom/tsens.h | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index a935d2335eea..35e82aaaef59 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -12,11 +12,6 @@ #include #include "tsens.h" -#define CAL_DEGC_PT1 30 -#define CAL_DEGC_PT2 120 -#define SLOPE_FACTOR 1000 -#define SLOPE_DEFAULT 3200 - char *qfprom_read(struct device *dev, const char *cname) { struct nvmem_cell *cell; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 4ed07e607cbc..8a747ab892f5 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -9,6 +9,11 @@ #define ONE_PT_CALIB 0x1 #define ONE_PT_CALIB2 0x2 #define TWO_PT_CALIB 0x3 +#define CAL_DEGC_PT1 30 +#define CAL_DEGC_PT2 120 +#define SLOPE_FACTOR 1000 +#define SLOPE_DEFAULT 3200 + #include #include