From patchwork Fri Feb 8 12:25:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157823 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1891566jaa; Fri, 8 Feb 2019 04:25:10 -0800 (PST) X-Google-Smtp-Source: AHgI3IboDQRfVYnVv25tRvKGsBMRYoVi7psO95wUV5V4PvRJ/IKxH0sSDSbHKOKcIQzA94hyrT2F X-Received: by 2002:a63:ef04:: with SMTP id u4mr20339016pgh.197.1549628710890; Fri, 08 Feb 2019 04:25:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549628710; cv=none; d=google.com; s=arc-20160816; b=mUo4DKlUsnOQsDAZpDU7neHQLa6ZKPBTEhsCeqa0OLYRmv5KgtRunvZcagLKLQiLSV 4t40zqfedkB6mO9lqd8Iua3Qwqf3nTLWCZlSDOQEjAg+QLEvY/ocrwlf2k1RmFc45EOk erqDqGefmD6auSRsHlJ8dusNp6sTYrPmn41HkioiT7uUQ5jw3yX80/5oIas6GCXW8M7y 68ywCrEmOnhaVlgqW/RPADekxdQakKnI262+GWC3VbLehXgnDObS+OzbuGh4NK7Ts5lI sFNMcKjIt8q4r8y+ZSZDgFVsI6BsTx0lqFOKaRYIs6hkhr49WYGjkXqU4Xgczlu/eup3 1bpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=mMH+5TKDF/9A/q5BRd8niXDyG3dMd/8VQ3eNRUAsq4g=; b=VE+pH0VuzoPJS7kFtljkguiH68xCCktdGPjwbSUbf2GME0tXv1ahXXhURJ+rrEbqor VzqK1wz43sYeJKC7QS5v6xXVEkok0AAfFE4xLjHQpEWjx366OLWXYGxzGghLGHraa2nv e4v8bp33VUIYFKvKxE4ldWRNx+55mlNxIwLVsDiV0PRd//qqh56N7hrSom6rx7q3MiRv zS9phZtDGQ+AlE4W5t3F8fDnddimalIwqy8P2J3RqIzasV5j/B8SWTOlzofF1cpTB0c3 javG/x7e5BA5Wa7SEXZJPaLlOOPZLvBO5nOM8XYM2x93m67Q+X64Y8pViWX6uhutha/5 My5g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l24si2035964pgj.171.2019.02.08.04.25.10; Fri, 08 Feb 2019 04:25:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726585AbfBHMZK (ORCPT + 7 others); Fri, 8 Feb 2019 07:25:10 -0500 Received: from mx.socionext.com ([202.248.49.38]:27741 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726547AbfBHMZK (ORCPT ); Fri, 8 Feb 2019 07:25:10 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:25:08 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 8028760062; Fri, 8 Feb 2019 21:25:08 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:25:08 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 2AEBC4036D; Fri, 8 Feb 2019 21:25:08 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 17DA11202F1; Fri, 8 Feb 2019 21:25:08 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 02/15] dt-bindings: arm: Add SMP enable-method for Milbeaut Date: Fri, 8 Feb 2019 21:25:49 +0900 Message-Id: <1549628749-30379-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b..365dcf3 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: From patchwork Fri Feb 8 12:26:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157824 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1891812jaa; Fri, 8 Feb 2019 04:25:24 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia0Ym9g5iJL+CSbCScryorxXLffsKoMffhcP/azQxw4iRdrx9eXiRKHW3yn0W4pO+dffwUR X-Received: by 2002:a17:902:690c:: with SMTP id j12mr22225789plk.206.1549628724265; Fri, 08 Feb 2019 04:25:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549628724; cv=none; d=google.com; s=arc-20160816; b=rrA4JmkT1dAjkOJ38MfvzrViHmfH/3yURJrwtkKT7v+EsA3hYdHKQMXTQYk62SeYIn 7wxnAH3Sd+2xg3CNElrBCv7n2ylToSVhdzoRY2g1ypoZdWWHDCioj+yUeYqxIdfgjDsC 14WlyLHyt5LOUO7q2vaGWkBvqxgOhh/THtL9DZXXR5If11pirCZgpa3RFsz//7m74t+h LMzGDB3h7wSVWKoGYlXgUdLo5WzOYS9otde5P3VnnrZP41myiDWpJJpUMKj4b59CoxMi 6xcjDgci2vDjqjN9TrT1azccHGy7wQ8xzQjnNtvTUvck+xqQO4EmxXei0wh1XJpTCZ22 0ZlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=Hi1H325GeaFi8pKSKsroz/RIfD0a9v9g+sjUonmsThU=; b=PWZOFPq5llY6DZYCd/HRaBKVWBfEnzx3cdEOMeeGfp9t2hav4gMBj7E0L9+lKiI8JY 4rLq3ujCFJ1+u9xPr1gyeKFVAJMNP5tCsra3WJnuRjQ04EmlUSxdR6I7WdSfNeR0j62I FPo5ZM5j4lCEZSPv+qjM40+BYGt+sR9KKnvIYRZ88NEwLcxo2kZ0Fhml9n99I6OCnn7y wR6b8QD74oWaQdL+/xuODss6suMa9efSIbTmMh62RK0S0MgEIxjfqEGU7OKWFDRjaAM7 UyDGMK6nA9GOLkyFcqTjEUwyZxAYa6ixrTQfMh3cAM7Y26Awxn6cw4zPrgZD8o5Z4/AA buGg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f35si982046plh.399.2019.02.08.04.25.24; Fri, 08 Feb 2019 04:25:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726465AbfBHMZX (ORCPT + 7 others); Fri, 8 Feb 2019 07:25:23 -0500 Received: from mx.socionext.com ([202.248.49.38]:27747 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726456AbfBHMZX (ORCPT ); Fri, 8 Feb 2019 07:25:23 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:25:22 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 8D6F860062; Fri, 8 Feb 2019 21:25:22 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:25:22 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 1DE9E1A04E1; Fri, 8 Feb 2019 21:25:22 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 090FC1202F1; Fri, 8 Feb 2019 21:25:22 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 03/15] dt-bindings: Add documentation for Milbeaut SoCs Date: Fri, 8 Feb 2019 21:26:04 +0900 Message-Id: <1549628764-30587-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- Documentation/devicetree/bindings/arm/milbeaut.txt | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/milbeaut.txt b/Documentation/devicetree/bindings/arm/milbeaut.txt new file mode 100644 index 0000000..9fd053a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/milbeaut.txt @@ -0,0 +1,6 @@ +Milbeaut platforms device tree bindings +--------------------------------------- + +- Milbeaut M10V Evaluation Board + Required root node properties: + - compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; From patchwork Fri Feb 8 12:26:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157826 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1892318jaa; Fri, 8 Feb 2019 04:25:55 -0800 (PST) X-Google-Smtp-Source: AHgI3IYq+Bt+KTkDW942lLQ190Z3rNgJrcjdyAWwZxkeGhlhW86xd1NqpVwiDtFDwwhTtihOXXa8 X-Received: by 2002:a62:2082:: with SMTP id m2mr21520245pfj.163.1549628755525; Fri, 08 Feb 2019 04:25:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549628755; cv=none; d=google.com; s=arc-20160816; b=ptY86f2tEmBYdJAjqBpJYIVBurFxwm1I6JFw8lfCrVoGqYVbWwQE+8lwFQhEpFCmaa GzwjBqF2tqOKyeerZpk7E+MP7XPFZwCgzeinQg2NYhXB0M978onWpEyCNMw3XtA+Gual AH1qwVTo/7FAdkf+R1ZY/SW3mc1QhOSek9l2Vo/IkCK0X819rWgGk2xi2qUpQoSeOIiB pRhaImdzr9ZloxkYnRp2ltAQIhhV5xt7L6tucG2qD4pykdbQegAhKHQMI+5/V1hSUS9p WZ38YL72ZAm+sxzBS4JKdpGIj9ZmE2DSEQW/kJKXSmsaoN2I1ntoDeXtscPxwNL0IZp1 55ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=HwhjQY0L6nxg/1AENXsUQXcpDaV8GeADMe8TvCXy1n0=; b=r9ANu9F8G3hsvoNOoZBGOXkUO/A2wd9S+Ssnwdw/wr2R/eW/eWypSXjzJnsirerGTs C8IMoqeUp8A2Gipa5JX6wGIdXoqChXAjbYj2DjdpU9RBYSfezuFa6k6rV6KNH9XwC7we fTAVoSohe+5ml4IG9U5TVw7TXU0Dp87zIgSl4EUL8AX0quH65ymhoqfYSLvNlqVIgf41 4o3zbBp71o7QhgI5cI/XyJpNXNkBgczPj7A73GtFUYDGMkFeLWHwy09JNy1qpezvakIe PoHdwh5SByi4DwGMx+CSlQIH9W/HQsQVtBr8HN/kDV8Hh5UwjCQS5klI+b8fzu4vEU3Q C1UA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t5si1973790pgm.79.2019.02.08.04.25.55; Fri, 08 Feb 2019 04:25:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726567AbfBHMZy (ORCPT + 7 others); Fri, 8 Feb 2019 07:25:54 -0500 Received: from mx.socionext.com ([202.248.49.38]:27760 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726456AbfBHMZy (ORCPT ); Fri, 8 Feb 2019 07:25:54 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:25:53 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 8B115180D62; Fri, 8 Feb 2019 21:25:53 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:25:53 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 355291A04E1; Fri, 8 Feb 2019 21:25:53 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 1DC471202F1; Fri, 8 Feb 2019 21:25:53 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 05/15] dt-bindings: timer: Add Milbeaut M10V timer description Date: Fri, 8 Feb 2019 21:26:30 +0900 Message-Id: <1549628790-30960-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt -- 1.9.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 0000000..ac44c4b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer. +- clocks: phandle to the input clk. + +Example: + +timer { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20> + interrupts = <0 91 4>; + clocks = <&clk 4>; +}; From patchwork Fri Feb 8 12:27:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157828 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1892686jaa; Fri, 8 Feb 2019 04:26:21 -0800 (PST) X-Google-Smtp-Source: AHgI3IYFjVU/6uZSVQ+jyzNvEZ1HwOqfDbNO/QNujInrab2gUZKCLESqrJXC/1ECxJYksIk1wyuU X-Received: by 2002:a17:902:33c1:: with SMTP id b59mr22214671plc.220.1549628781832; Fri, 08 Feb 2019 04:26:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549628781; cv=none; d=google.com; s=arc-20160816; b=0HK8fmGqa7Bs8YWwtT3ow/lcrFQHApQHmk/Bjajn9k+EO0IqbWJvSfSr5x/ts2+lOI swe3zXTxv7RVCVKZqFOm+cOrrVOn+METazUb3jMqNKj+bbp9V5Wr5bwV7VvO8oyUR22c Uo31MHZ6Ty3yUIxAKH1sWS/+kTUlX6enYLHCErFQ37bSuretmMeJ2OFKX4ghXMmoGypS XCU4TRJMsZ/68kJxuc5Hx/qUrLIiexG2Ljv+/0/MqF6uaaN4yet3awEXBUWZQPF9J18L n+cZ33LK3oV95QWW0/djb58b0jXl8Q1Ss3CupXeRMw68kc8gOti5ndlP3PehMdDxLIT1 BXpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=Yj4kEwJIUquUDD8RV//075Xtny1YuWNOlvpbn/CR698=; b=0P0C53GU0sfF5DJO+z7bcSZtHJcT3H+hZ04oNy3y5LaCYlwpbmFgXN5qIWIOr7DBVc 1hhATngjS26wgLXK9ziRSVvHltRLo/tMh8A4j9iRTjlTgrB3GGe8U4vcA5gt3zvGtj1T 115/QoIyR4D61PHQ/NEBLh9xuNhCJ+wL+EODc2xWYxlVXeIp/xhLhdJU6WXcLkI4W5Cn 22kIbcKAXoQqFyq6qcRmIrHEWRjGJ8OaKiuKKp2YCB81sbzg+JZisT7GjgbZpq3wZi5C RnkYsH1d+/9N8FOerSyTltlK5E/YSqSNjWcKeDuztb7vYERbhguPQ7CAIK9LSqm2EZnQ 24zQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 61si2035970plc.364.2019.02.08.04.26.21; Fri, 08 Feb 2019 04:26:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726700AbfBHM0U (ORCPT + 7 others); Fri, 8 Feb 2019 07:26:20 -0500 Received: from mx.socionext.com ([202.248.49.38]:27777 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726565AbfBHM0U (ORCPT ); Fri, 8 Feb 2019 07:26:20 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:26:18 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id D2CCD60062; Fri, 8 Feb 2019 21:26:18 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:26:18 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id AA4EA4036D; Fri, 8 Feb 2019 21:26:18 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 874BD1202F1; Fri, 8 Feb 2019 21:26:18 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 07/15] ndings: clock: milbeaut: add Milbeaut clock description Date: Fri, 8 Feb 2019 21:27:03 +0900 Message-Id: <1549628823-31388-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Milbeaut clock. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/clock/milbeaut-clock.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.txt b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt new file mode 100644 index 0000000..bcfc5df --- /dev/null +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt @@ -0,0 +1,49 @@ +Milbeaut SoCs Clock Controller Binding +---------------------------------------- +Milbeaut SoCs Clock controller is an integrated clock controller, which +generates and supplies to all modules. + +This binding uses common clock bindings +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: should be one of the following: + "socionext,milbeaut-m10v-ccu" - for M10V SoC +- reg: shall contain base address and length of clock registers +- #clock-cells: shall be 1 +- clocks: shall be an external clock + +Example: Clock controller node: + + clk: m10v-clk-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-clk-ccu"; + reg = <0x1d021000 0x4000>; + #clock-cells = <1> + clocks = <&clki40mhz> + }; + +Example: Required an external clock for Clock controller node: + + clocks { + clki40mhz: clki40mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + /* other clocks */ + }; + +The clock consumer shall specify the desired clock-output of the clock +controller as below by specifying output-id in its "clk" phandle cell. +2: uart +4: 32-bit timer + +Example: uart1 node: + uart1: serial@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + }; From patchwork Fri Feb 8 12:27:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157830 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1893065jaa; Fri, 8 Feb 2019 04:26:48 -0800 (PST) X-Google-Smtp-Source: AHgI3IagtmDvZcCrzkLMM/Ze871vJ8Cap9Nqan0GGIOf6FRHF3ifMpxCzaTW2qnLUoEQEdXOtRxn X-Received: by 2002:a63:fa06:: with SMTP id y6mr20231492pgh.177.1549628808005; Fri, 08 Feb 2019 04:26:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549628808; cv=none; d=google.com; s=arc-20160816; b=ilCM7ikLsjJN8c9wyVl7fdQPWpwrcaG97zb84Vd+48gwVZ3KQ9hUiNaWKHWfH2UoTF y0Z3Cqy4vjrWQtXJ6G5cCvmsMYAZlh33baw3oF/3sndTMV45b+63bxG+29EJquzE5BpS 0mzNd78+rCYT2QufFPbJaLB20rZ54o58g93fj7FXrp0Mepx2vaBXUIOOJlzxYXUjWgRe PAmoEwI3VX+eD55Q/UJn2ehJRDMChMpCpfjmMiri9DHIYBj2sm3dkL5xj4zaCgJWmsWX csOHNg7aUsSp7C5KPdvZoSD1c5guWu5cAqcRURGIv+nM6QzINmEvqmqj4StIO/9Rh0Lq /Myg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=7+LBuUjcJaEpoKGwsgMF3Lp7u7qcO/g5cpFKRMR6xgI=; b=OQaMDIJWgpcGmAnPSuRvjsnuL1MHhOqSQXg7XDRNZjnPGbol3mX2YNFZASn2aZGNYl hIyNsjPKaDVG2JGJAsrmvJYaD26Du0Ed7/HxxJNHUboCiwYiKCL4Qut/o3yItzlAiKlL pfL8/Ytmd7mIXDxqUGi9HCBhlku6K0tsWzOfG6w7TrwqqXcqDVeXV8bqtjkc3I8HuQtF HRY+s9GxU35x4JLhL4voLN3jgBGSZYSR5MXLA5pgAx+Xv+UpCIpmYScFFudXfO5EXOER Jj4rcK+qgv1W/NRhT7zcn9Te6A3nRFLhvBPi1robkfbGBEjm6L6ZojusQS2gZJIiSz3J m/WQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v35si2342771pgl.130.2019.02.08.04.26.47; Fri, 08 Feb 2019 04:26:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726565AbfBHM0r (ORCPT + 7 others); Fri, 8 Feb 2019 07:26:47 -0500 Received: from mx.socionext.com ([202.248.49.38]:27802 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727139AbfBHM0r (ORCPT ); Fri, 8 Feb 2019 07:26:47 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:26:45 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 6C62F180D62; Fri, 8 Feb 2019 21:26:45 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:26:45 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 4FAA31A04E1; Fri, 8 Feb 2019 21:26:45 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 380C51202F1; Fri, 8 Feb 2019 21:26:45 +0900 (JST) From: Sugaya Taichi To: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 09/15] dt-bindings: serial: Add Milbeaut serial driver description Date: Fri, 8 Feb 2019 21:27:29 +0900 Message-Id: <1549628849-31726-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Milbeaut serial driver. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/serial/milbeaut-uart.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt new file mode 100644 index 0000000..8f61c38 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt @@ -0,0 +1,21 @@ +Socionext Milbeaut UART controller + +Required properties: +- compatible: should be "socionext,milbeaut-usio-uart". +- reg: offset and length of the register set for the device. +- interrupts: two interrupts specifier. +- clocks: phandle to the input clock. +- interrupt-names: should be "rx", "tx". + +Optional properties: +- uart-flow-enable: flow control enable. + +Example: + usio1: usio_uart@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + uart-flow-enable; + }; From patchwork Fri Feb 8 12:28:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157833 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1894025jaa; Fri, 8 Feb 2019 04:28:03 -0800 (PST) X-Google-Smtp-Source: AHgI3IY6Pi5kZksuqAfLeUxqj7OzPGaQT2Aoua4PyhSf2hR/cgOJE33e3eGatq3QBym5hFHTBTk4 X-Received: by 2002:a17:902:848f:: with SMTP id c15mr21765276plo.119.1549628883668; Fri, 08 Feb 2019 04:28:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549628883; cv=none; d=google.com; s=arc-20160816; b=QnwAivN3ruNKCMtbUV0kDxfutDjsj0AHsSA/Bklj4q/vN9QXia/EBPo/irbgFovdrG MTkusAh07l1gDEiCVfk1a41pQnDjglNNgGbmYY0mbiLyndYIn3FmLJB63z95KtGXXWti PkAmBTf8JFGPS8sQ4Wwn3QJDDVi4jtYKpSmckWEggP60Jw0MHUQdQbt+6iWHYP+S4WwO vLD5sK9uLkFnu8DybczPXWD5fqSXe1K4EQoX96Y9JzTEBw/mKp1WcsbEn4knu05FzNSA 3PM13cuZznqggxEdLg7VBrUCFLYq+xJDzV2Nh7sVNqN/DwyZdOwMLaCRNv4BE5A3omgW aNfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=wc1r8YOeKvl4Jj0+TX/IuLkiWwv7yU+HPLhYs/MN/yg=; b=t2oadGr+Krue1zImLW/BDh8FFjEVaiwUQObCxUWnhL7DMKWaVsFHQv0LGONOCfJ+Kt LuEXjCb/t5VlZHYqRh8eRJLM3ilamSiGMNBxzIFiw7PVSnkC0MvAxsVrg216FqfT6nM1 /JNWflIxXS4IF8pf6CvSUUwpQNHo8/mspzHrksrIpuune+LryhYcbZ9Bmb8amLGn03wx /5Q+HcrH57e7CRFWXA9snGad/FW7ZRPWR0fI3GmEda1O5DfHI6VC8xRKqvdiJRKRc83H xePhU38KnC6MwIyeeP7FlYnQzcGoaOLJInjU+tMWui34q6ra9gJENBBoUDaWy9jLZ3VX MpJg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m75si2201925pfj.53.2019.02.08.04.28.03; Fri, 08 Feb 2019 04:28:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727467AbfBHM2C (ORCPT + 7 others); Fri, 8 Feb 2019 07:28:02 -0500 Received: from mx.socionext.com ([202.248.49.38]:27821 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726522AbfBHM2C (ORCPT ); Fri, 8 Feb 2019 07:28:02 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:28:00 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 6D48A60062; Fri, 8 Feb 2019 21:28:00 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:28:00 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 070411A04E1; Fri, 8 Feb 2019 21:28:00 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id DC9571202F1; Fri, 8 Feb 2019 21:27:59 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 13/15] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Date: Fri, 8 Feb 2019 21:28:40 +0900 Message-Id: <1549628920-32623-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree for Milbeaut M10V SoC and M10V Evaluation board. Signed-off-by: Sugaya Taichi --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 ++++++++ arch/arm/boot/dts/milbeaut-m10v.dtsi | 131 ++++++++++++++++++++++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi -- 1.9.1 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148..f697d87 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts new file mode 100644 index 0000000..59e8d73 --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Socionext Milbeaut M10V Evaluation Board */ +/dts-v1/; +#include "milbeaut-m10v.dtsi" + +/ { + model = "Socionext M10V EVB"; + compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; + + aliases { + serial1 = &uart1; + }; + + chosen { + bootargs = "init=/sbin/finit rootwait earlycon"; + stdout-path = "serial1:115200n8"; + }; + + clocks { + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi new file mode 100644 index 0000000..4fc2f8b --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include + +/ { + compatible = "socionext,sc2000a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,milbeaut-m10v-smp"; + cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { /* The Generic Timer */ + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <40000000>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&gic>; + + gic: interrupt-controller@1d000000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1d001000 0x1000>, + <0x1d002000 0x1000>; /* CPU I/f base and size */ + }; + + clk: m10v-clock-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-ccu"; + #clock-cells = <1>; + reg = <0x1d021000 0x1000>; + clocks = <&uclk40xi>; + }; + + timer@1e000050 { /* 32-bit Reload Timers */ + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + clocks = <&clk 4>; + }; + + pinctrl: pinctrl@1d022000 { + compatible = "socionext,milbeaut-m10v-pinctrl"; + reg = <0x1d022000 0x1000>, + <0x1c26f000 0x1000>; + reg-names = "pinctrl", "exiu"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk 4>; + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>, + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>, + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>, + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>; + interrupt-names = "pin-48", "pin-49", "pin-50", + "pin-51", "pin-52", "pin-53", + "pin-54", "pin-55", "pin-56", + "pin-57", "pin-58", "pin-59", + "pin-60", "pin-61", "pin-62", + "pin-63"; + + usio1pins: usio1pins { + pins = "PE4", "PE5", "P87"; + function = "usio1"; + }; + }; + + uart1: serial@1e700010 { /* PE4, PE5 */ + /* Enable this as ttyUSI0 */ + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + }; + + }; + + sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; +};