From patchwork Tue Aug 30 16:58:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3067BC3DA6B for ; Tue, 30 Aug 2022 16:58:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230488AbiH3Q6u (ORCPT ); Tue, 30 Aug 2022 12:58:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231199AbiH3Q6t (ORCPT ); Tue, 30 Aug 2022 12:58:49 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33198B14C7 for ; Tue, 30 Aug 2022 09:58:48 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id p8-20020a17090ad30800b001fdfc8c7567so1675666pju.1 for ; Tue, 30 Aug 2022 09:58:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=gbwg87hG3tf6Wqw8hsoPn0QdO74QME7etMAVFms+/pw=; b=rGdcnEx5mVRMRbRAmSUEw4c5Jk5Kni1WJSvZVgMsW5hol47AAPyc8g+IcPBJ3Ngv+g Z/As66hGpY/53FTdpnikonp0vOM9xlBZDHGTkpeuCV4SRaCntxbe+VWpV/k2SMOEm6La 34XAKW5/6F4EqnGdXGTOuqve0eJltrdu7qWqXwfsT+ygVNwyn8BFywzOX0FpMMEUMTOT lMhuy6aPUbZ1VxLym/YRrPqzQ2uo5GNf73m6O9ZAHB46GH7ph/v07GAylEEzFkoOVfm4 E7VQTrQN4yNOVcCFcTGGwj/3fwkcFf8Xu0nGWBFNI2Ez9f1ow/28tAwgdb3ISBH1bw5w Sc8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=gbwg87hG3tf6Wqw8hsoPn0QdO74QME7etMAVFms+/pw=; b=JDKA/qlGdKZ8MiAIeNJ1rZPYsNL0s72KmM4nPpuoX/r6dUncW280/A0Z50oJBad4B9 YMb/RX8b+sJuF6SaLmnnIVCyjRkWfP1HpCaxPPZ8bboul+6mH+Y4HK+/05riBoEvSsmE wgOIJc2gS4Gvr5rLQ+oX8ZVRAIN18zRDxhcLNc6QPMw/xFanMnDP8c+4aXAahZ4xsG9v Po3Mjr2DgtjcugJPFUg1bSAD6H11fbBgJxVuK7VXLJAvx+x7XkNBjf9VJZ+d1gcM0MHE rnbUlSJj+rI09BFpdl1fv4zk9KU8pYSFKwqIMBDsZSzXlXoef4HsKGg8IbzQqX+Gx3/J Wtcg== X-Gm-Message-State: ACgBeo3fF0BfsUJ53JqfKIq7X3FAGr4uIp1n0fPgsDBixW7tx1wYXPTh QKahPDLmkkYYFt9FacL/UDB1 X-Google-Smtp-Source: AA6agR4UB0bExNneHRVAvmaritzLE6hDn7Q0sJjqGFMq90N2ed65DimUyZzwRUKSnHX4Cx/U6I/2nA== X-Received: by 2002:a17:90b:4f4e:b0:1f5:8a65:9192 with SMTP id pj14-20020a17090b4f4e00b001f58a659192mr23922544pjb.224.1661878727685; Tue, 30 Aug 2022 09:58:47 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:58:47 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 01/11] PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure Date: Tue, 30 Aug 2022 22:28:07 +0530 Message-Id: <20220830165817.183571-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add kernel-doc for qcom_pcie_ep structure. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 9f92d53da81a..27b7c9710b5f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -140,6 +140,23 @@ static struct clk_bulk_data qcom_pcie_ep_clks[] = { { .id = "slave_q2a" }, }; +/** + * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller + * @pci: Designware PCIe controller struct + * @parf: Qualcomm PCIe specific PARF register base + * @elbi: Designware PCIe specific ELBI register base + * @perst_map: PERST regmap + * @mmio_res: MMIO region resource + * @core_reset: PCIe Endpoint core reset + * @reset: PERST# GPIO + * @wake: WAKE# GPIO + * @phy: PHY controller block + * @perst_en: Flag for PERST enable + * @perst_sep_en: Flag for PERST separation enable + * @link_status: PCIe Link status + * @global_irq: Qualcomm PCIe specific Global IRQ + * @perst_irq: PERST# IRQ + */ struct qcom_pcie_ep { struct dw_pcie pci; From patchwork Tue Aug 30 16:58:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73421ECAAD1 for ; Tue, 30 Aug 2022 16:59:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229569AbiH3Q7H (ORCPT ); Tue, 30 Aug 2022 12:59:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230503AbiH3Q65 (ORCPT ); Tue, 30 Aug 2022 12:58:57 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0294B6D1C for ; Tue, 30 Aug 2022 09:58:54 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id l65so1567619pfl.8 for ; Tue, 30 Aug 2022 09:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=26/uwpg877kUcP36OEZ2fnl1A+0pDTFxJzbD+WiV7CI=; b=i8e6sP2Y8Docm66LdDaQdv4DRn9gJu1+qSc50GmbXZp0bE/imrG+OAvUy2sjxxvfvZ u5/pm1+RifQipRyfTN3/7bhfU6YS09f+g5+6/pRhsYogVgWtuwSiySj1tiy0WlYNYeQ4 n9IDiuVTm3A2CbQsdv6ptN7F2E5xpc5rnc1FSRY59B5shYSNTXYueOLI1DJFJU0g5Y3E yTh3Dy6i/575OB+aqvTPZOIB4X9icWam9IUvCCvPI2q9nEhopls4vTVIw23zDGRff8v+ LV4awYbiu0eDsR+C3ZDNTZ/LewUNYVmrm13EEo0YZ24OM7lSe2ii2Xk52u0+bBPV3SGD n3Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=26/uwpg877kUcP36OEZ2fnl1A+0pDTFxJzbD+WiV7CI=; b=oIgSK2YlzaV6431lkeL4zBjbwlFeB6F9XXPtppv7OLbwJjIPzCw6m9dmS2Z8Ehx5Ba sCIeQYe7p1N1SNlBINaJK/lCShrjJ9olJ6/laiTUPGqpTICFS20+FDm+1a9bDOmakYmU LnL7vT5HSkWFGn+qlp/0h9skzWvUaBvqbvbU3qeTrkD0If0RpIWVnm2pnB2EQmlpBB+j jx+ScOpHYN91dvZ/NM2H1auHl74Mgw7VMhlQ7M2ReanfShxidtnXZGwkcy1NGNcu3qZ4 mQafbUTiT7YYeHOGZPgbxM6e9NJKTKFy/aU9I6ENfIe63VjMJtsiEC8qhzh/Jng8sHiP q9fw== X-Gm-Message-State: ACgBeo0zj1KWj8VSvAFdYnRxzrP5cAEvGOqMnA1qpPcmQKGilukZxYRl QVHshVGFLrdvPIMvFBW28BMp X-Google-Smtp-Source: AA6agR6A57E+jhcVSk0MIoxD9Gl7X2cRLTAlcV2H/cO1MwqANKqc9CRckbkoOiDz1IgMMipx3Fqo6A== X-Received: by 2002:a05:6a00:14c2:b0:53a:a5bc:a2ec with SMTP id w2-20020a056a0014c200b0053aa5bca2ecmr65216pfu.27.1661878733397; Tue, 30 Aug 2022 09:58:53 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:58:53 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 02/11] PCI: qcom-ep: Do not use hardcoded clks in driver Date: Tue, 30 Aug 2022 22:28:08 +0530 Message-Id: <20220830165817.183571-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Generally, device drivers should just rely on the platform data like devicetree to supply the clocks required for the functioning of the peripheral. There is no need to hardcode the clk info in the driver. So get rid of the static clk info and obtain the platform supplied clks. The total number of clocks supplied is obtained using the devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_ APIs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 33 +++++++++-------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 27b7c9710b5f..34c498d581de 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -130,16 +130,6 @@ enum qcom_pcie_ep_link_status { QCOM_PCIE_EP_LINK_DOWN, }; -static struct clk_bulk_data qcom_pcie_ep_clks[] = { - { .id = "cfg" }, - { .id = "aux" }, - { .id = "bus_master" }, - { .id = "bus_slave" }, - { .id = "ref" }, - { .id = "sleep" }, - { .id = "slave_q2a" }, -}; - /** * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller * @pci: Designware PCIe controller struct @@ -151,6 +141,8 @@ static struct clk_bulk_data qcom_pcie_ep_clks[] = { * @reset: PERST# GPIO * @wake: WAKE# GPIO * @phy: PHY controller block + * @clks: PCIe clocks + * @num_clks: PCIe clocks count * @perst_en: Flag for PERST enable * @perst_sep_en: Flag for PERST separation enable * @link_status: PCIe Link status @@ -170,6 +162,9 @@ struct qcom_pcie_ep { struct gpio_desc *wake; struct phy *phy; + struct clk_bulk_data *clks; + int num_clks; + u32 perst_en; u32 perst_sep_en; @@ -244,8 +239,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) { int ret; - ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); + ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); if (ret) return ret; @@ -266,8 +260,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) err_phy_exit: phy_exit(pcie_ep->phy); err_disable_clk: - clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); + clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); return ret; } @@ -276,8 +269,7 @@ static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { phy_power_off(pcie_ep->phy); phy_exit(pcie_ep->phy); - clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); + clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); } static int qcom_pcie_perst_deassert(struct dw_pcie *pci) @@ -495,10 +487,11 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, return ret; } - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(qcom_pcie_ep_clks), - qcom_pcie_ep_clks); - if (ret) - return ret; + pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); + if (pcie_ep->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return pcie_ep->num_clks; + } pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); if (IS_ERR(pcie_ep->core_reset)) From patchwork Tue Aug 30 16:58:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FD77ECAAD8 for ; Tue, 30 Aug 2022 16:59:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231166AbiH3Q7N (ORCPT ); Tue, 30 Aug 2022 12:59:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231181AbiH3Q7H (ORCPT ); Tue, 30 Aug 2022 12:59:07 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73990B9FAD for ; Tue, 30 Aug 2022 09:59:00 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id y1so9852088plb.2 for ; Tue, 30 Aug 2022 09:58:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=cXVSIoAXy4k6GvjO7JA/nhvOJMAK8QRnMR9+cTCkOGs=; b=F4+Mue9z8/NIh0/+GyY0e1oPUlENhniRHuhgypYQDNG726pVNN9PqSm0K9SII7gpmW CnTBN3cXEHt8anqhFTIaybBZcnVpabrwDqr6mStCTpsoGan5/mUAgYkNRAdib1/sb9Pe sT7yBAPlpoZFu+hXmRCqH7FrOlfCObGN7G8+d/zSHgHuAbV9LSZSn6trx0qiiKE+CQyJ NrkBTa+dhvfcQk0Mw68TxLWCSSSkcRegu3a+VZ89gLktL/mRNc2P4d4lT8PU+u6bbaOJ yyDFWju7dO7pJrfmFpNSs1VWvLZYplYUnkY9ZoidMR0YRK+Z3LbNl2mg5hUpwV3VA4Di dAJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=cXVSIoAXy4k6GvjO7JA/nhvOJMAK8QRnMR9+cTCkOGs=; b=e4OqxUFyI7cvoFy5LzWZHd2Nb+xft2utwLxW/vtg8SKAWJriFoXb0OpsCGKcMQHOso ojEp5QhO1x0tJkYiQWNHjTa9ejiJ6La5hbdwB6gbNP/A8tNxEGJpuYRIjc0c5w4vh5eK GLjl3oX8Aa5hAn6RuBt8W4aW3HI+/rUTQdftMyQZLT/ypSALQdlNrd95V2xNS6GIgEW1 rmuLLeFOmqIdWB25SHt57kqI5+poEM2o8KSeZ3Wcz0ljyHVP3QPCd/mo04Dco2XNc0o/ X9Mt+bAwVLVZgRResyE77+ECfDYKaTzUXPJCR+KeyrbvLKcvhIGYwu0v5y9h0LyXf1lw YI1A== X-Gm-Message-State: ACgBeo35waOl7SMPR8kR4ZGPfIRTzSlzMnG8eYvVcvny25V9s157tscR hb8UfqCSaLSjsQm2YJE2jcni X-Google-Smtp-Source: AA6agR6OpJc0TAmDAvBCfMYtPNFVC1gjNXQxUiq1H+/Y8Gzp6uHO29zaPd5s51mVRE7Jt2R0MdqJ1Q== X-Received: by 2002:a17:90a:318f:b0:1fa:a374:f565 with SMTP id j15-20020a17090a318f00b001faa374f565mr24569940pjb.146.1661878739057; Tue, 30 Aug 2022 09:58:59 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:58:58 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 03/11] PCI: qcom-ep: Make use of the cached dev pointer Date: Tue, 30 Aug 2022 22:28:09 +0530 Message-Id: <20220830165817.183571-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the qcom_pcie_ep_get_resources() function, dev pointer is already cached in a local variable. So let's make use of it instead of getting the dev pointer again from pdev struct. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 34c498d581de..1e09eca5b3b2 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -483,7 +483,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); if (ret) { - dev_err(&pdev->dev, "Failed to get io resources %d\n", ret); + dev_err(dev, "Failed to get io resources %d\n", ret); return ret; } @@ -505,7 +505,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, if (IS_ERR(pcie_ep->wake)) return PTR_ERR(pcie_ep->wake); - pcie_ep->phy = devm_phy_optional_get(&pdev->dev, "pciephy"); + pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); if (IS_ERR(pcie_ep->phy)) ret = PTR_ERR(pcie_ep->phy); From patchwork Tue Aug 30 16:58:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0BCDECAAD1 for ; Tue, 30 Aug 2022 16:59:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231231AbiH3Q7Y (ORCPT ); Tue, 30 Aug 2022 12:59:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231176AbiH3Q7O (ORCPT ); Tue, 30 Aug 2022 12:59:14 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CEDEC0E47 for ; Tue, 30 Aug 2022 09:59:06 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id p18so11699881plr.8 for ; Tue, 30 Aug 2022 09:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=D+t611tSeFJdlaRBUeL7QdiZitvDcGQkCQ8fo5d53SM=; b=kVeAYgVIcvh9Y1/Dc5SFOsOvikyDlpNBLkrRVGrv9gm9jXQGoT7GTinYbkd9qBEZlh 27DPUG7O9g76tKSxBD2+yCMNRcKC1BMvhZKK1mFmvtu6stdpSzpBatZRP0JnsbNHs8sz MCfnUPsSqJyVzSVLyoJTgT5l297iEgGdhSEc/buN8sdJ4owfv7szNB/hbgWt6aTdQwfj Wc/Cb4+43iMZ+BY9pOw3FBYRufacY20pShc9kUeKspFB9qKKfbdshFh7cjVpxt0G2FFe 6uzLFSIST4AAWuWFv56YS1M1boqWV5TKM0QXq6ByQr7owX0Lmz5QPcwKVfgiAklxPkhx TT2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=D+t611tSeFJdlaRBUeL7QdiZitvDcGQkCQ8fo5d53SM=; b=DhrjZTT8m8/K74ZHVrXDP1+yy4GsJMbB+e9uFMb1G7S7/g6v/FSTNPyMN/jmDLvGYN Z2z2e/HJuBBMNB2huWgRM3mNZAbynNkuTLCDsUS+y0L1xr3caeLqhSZLizc1FDR2f9g/ oC3/PFwbdlYdq2a9/mkhKE3MVCRsTPWGOIfoouJJeR/n1sKbGxwMPhtS05GHtQEm03l1 yNuVppgvELWCqvoV1GHaqmKIaALg8panRKPn/jnx2nusDdtPrU3H7AaXn61xgXMvX47X LSkM5s2B4uIQAZ9jOPOkT/nkg7nNjsaNLpx1l84MPFeKobqBZJ+vdzkdwKbgcnN83rwy WpUA== X-Gm-Message-State: ACgBeo3lUKmoaDOzxruskJhpHlQUqYzLwvyz0WtK6OexPMSAtREaL1bv hV7rgSPRFB1/ZUrSPXBforjm X-Google-Smtp-Source: AA6agR4ay617XZEn9BSl4rlfvkGED9InOfI+x47WfduM0tt8NjHbGQqa/9iANW/R64Khr/rI84AVgw== X-Received: by 2002:a17:902:f782:b0:173:1206:cee0 with SMTP id q2-20020a170902f78200b001731206cee0mr21871943pln.130.1661878744651; Tue, 30 Aug 2022 09:59:04 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:04 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 04/11] PCI: qcom-ep: Add eDMA support Date: Tue, 30 Aug 2022 22:28:10 +0530 Message-Id: <20220830165817.183571-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA) peripheral for offloading the data transfer between PCIe bus and memory. Let's add the support for it by enabling the eDMA IRQ in the driver. Rest of the functionality will be handled by the eDMA DMA Engine driver. Since the eDMA on Qualcomm platforms only uses a single IRQ for all channels, use 1 for edma.nr_irqs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 1e09eca5b3b2..54b927adf60a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -66,6 +66,7 @@ #define PARF_INT_ALL_PLS_ERR BIT(15) #define PARF_INT_ALL_PME_LEGACY BIT(16) #define PARF_INT_ALL_PLS_PME BIT(17) +#define PARF_INT_ALL_EDMA BIT(22) /* PARF_BDF_TO_SID_CFG register fields */ #define PARF_BDF_TO_SID_BYPASS BIT(0) @@ -367,7 +368,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | - PARF_INT_ALL_LINK_UP; + PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); @@ -670,6 +671,7 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.dev = dev; pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; + pcie_ep->pci.edma.nr_irqs = 1; platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); From patchwork Tue Aug 30 16:58:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08FB9ECAAD1 for ; Tue, 30 Aug 2022 16:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231226AbiH3Q7j (ORCPT ); Tue, 30 Aug 2022 12:59:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231225AbiH3Q7W (ORCPT ); Tue, 30 Aug 2022 12:59:22 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF830BD77F for ; Tue, 30 Aug 2022 09:59:11 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id m2so11715666pls.4 for ; Tue, 30 Aug 2022 09:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=FMZK2zbDyl55wonvxZo05JFqyO2/6cJpEjPTCWuWIWI=; b=DEZxBEVQDmbO3QSre3sa73s6DhO8qX+KayjAX2fmCbRFwic8NG6XuAuDzC7zXaebzg WzEPgm7lq7KjDM5jCYBNaHzjSHmYLk3ChZbvejiFUfLHeaIdVvFxsDjuCB9L1y3dsP+7 20d5vmUxRfulyomW3kyhiGKJ4lszVGk7V0pEqKOSQWiNpA3ntJ9wPuTpxNl4AEBeCTlL rWormvz1OEV/lItoLy8JbIsH281EPBd8+GyRmDInmwmErudiTLdJbjwhOogR4dd8972U KfyDoAkl2yNWkoXOsOdQZNeLf5ON6WSN3GkT05IabyBynducw9T47J6PnjPOMqIujXV7 dmkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=FMZK2zbDyl55wonvxZo05JFqyO2/6cJpEjPTCWuWIWI=; b=4qHq9t0xOUPZJGgt4U092Ty5HbJjQhOmX9aBknCB5Y5tZDh1gNijtLdKrpeCrB4KTu dJyq39EtpuodR7vGOIbTVTzMEJ1q0JJTK0KuOWJWjTcudT1b9AWori3mk1tbBUphx+w/ 0YLJWcwurJ5cgri+xOOuEaO2FqThrwRuqxReQDaCiKC381lWMhvNiav70XD79+E3rP0r HhmTlYCIMIjXUE/x593dCKBHqCLTbDo/hA/ZzeAxQGL+WDzSgLrYLD8noSM1lnBKityH Y7N5Nt1KanSdBOnZuq6h5X0U8v6GX8l3rhCc3qRpGF/dlaffvdzL1g1ZBIMeoIjar9MG 2UEQ== X-Gm-Message-State: ACgBeo38J6S+uWDaJ72l33BnjA5H01gUR1PukRgKJVAUbb6tWl0vaG4s YWQZK6cBF6ZK3y0rH+e2b3Wz X-Google-Smtp-Source: AA6agR6hP1/3DL9GUw99sS8mR62251oVzQJSTfMrgO+fPtawl5EyLLcsl6sNeP8K2fT/jRRR6D9gUA== X-Received: by 2002:a17:90a:cb14:b0:1fd:c964:f708 with SMTP id z20-20020a17090acb1400b001fdc964f708mr11522996pjt.62.1661878750176; Tue, 30 Aug 2022 09:59:10 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:09 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 05/11] PCI: qcom-ep: Disable IRQs during driver remove Date: Tue, 30 Aug 2022 22:28:11 +0530 Message-Id: <20220830165817.183571-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Disable the Global and PERST IRQs during driver remove to avoid getting spurious IRQs after resource deallocation. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 54b927adf60a..98ef36e3a94d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -586,11 +586,11 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, { int irq, ret; - irq = platform_get_irq_byname(pdev, "global"); - if (irq < 0) - return irq; + pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); + if (pcie_ep->global_irq < 0) + return pcie_ep->global_irq; - ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, qcom_pcie_ep_global_irq_thread, IRQF_ONESHOT, "global_irq", pcie_ep); @@ -700,6 +700,9 @@ static int qcom_pcie_ep_remove(struct platform_device *pdev) { struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev); + disable_irq(pcie_ep->global_irq); + disable_irq(pcie_ep->perst_irq); + if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) return 0; From patchwork Tue Aug 30 16:58:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABBA6ECAAD8 for ; Tue, 30 Aug 2022 16:59:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231294AbiH3Q7u (ORCPT ); Tue, 30 Aug 2022 12:59:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231263AbiH3Q7a (ORCPT ); Tue, 30 Aug 2022 12:59:30 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A61C4D86C5 for ; Tue, 30 Aug 2022 09:59:17 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id q15so6559751pfn.11 for ; Tue, 30 Aug 2022 09:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=raWHLS6gJR669YXmkR8TC0V9o68cfdUpfACEFenHvcM=; b=NxJcYq9P3LwZBjYGtkHgvmxb0nvL7//quN0qEVHrWu7JfOip9zCLrO86OGSA761P6/ e8le0FyIdBiqnZQqePP4DQX8OAnbaFzwWnB4pMfUj4XCO3CtwKK+weTzD8r5yzaTSH8n zMYqYI48jsDal3n+CYTSfXt10FfcbpJWALWVWB8CQrTg3jfRnEZ0IgHTZzZu4JBouQv3 Hq2UMfDTtEYIA0Nqd9cZTWntE29OwRFtVtHMRMZPrB9wKKXhMDIx8Fj0BbIP69SxoDOq Vng25vbcvoIT0OSuPzxt3YVSFovWd5lA1M4Tuof8nh0+eL5td9X1ByAI8pcLoJCbLGsr ctbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=raWHLS6gJR669YXmkR8TC0V9o68cfdUpfACEFenHvcM=; b=C46Nl0V/xCXqTGNXdqWUHWBT1L2kINcpYahgE8jtdZv1cduuzyHIhBFzrFu+2xd5eF JsflcAyNr+O0MNjvPJlrAOqTUbidO6OOIwLB3S3M/opfxMr20ogHeiLLnUos/35MM32e WFA8jt6BvGEPUe0Umtqwe1nLPkoSXX/3hCUq0fP62kk9T2KViXFgCnB/3106UC07LVQ+ iaHjmsT2e6OdQ5mtJ4U3zxzEWbLyBRn/f1ol1PsUXMmIiTx9QKNzop5CevjoHSLP8gns 1Y65PPC9Qd0Uy7rj2NTMmaRhR31gPFaRcOeCZI+Ti4Zyfg2JoFlVhxTLhPdt5Syx9On6 QZug== X-Gm-Message-State: ACgBeo3Kh6BkbTu2Jq618Z63edLbHsmmNPWN6/JiFs51V350hSrtuGug O8PtLPv2ND4ePGm/YMK40ApT X-Google-Smtp-Source: AA6agR7TaQ59DWByOuILG9aKNzvBGq77MNNo7gFGh6q9H/g7RKt1TzFPML4t1WOHoJ9o/53g96tRXw== X-Received: by 2002:a63:5f4c:0:b0:42b:f6bd:47dd with SMTP id t73-20020a635f4c000000b0042bf6bd47ddmr9996765pgb.578.1661878756105; Tue, 30 Aug 2022 09:59:16 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:15 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 06/11] PCI: qcom-ep: Add debugfs support for expose link transition counts Date: Tue, 30 Aug 2022 22:28:12 +0530 Message-Id: <20220830165817.183571-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm PCIe controllers have the debug registers in the MMIO region that counts the PCIe link transitions. Let's expose them over debugfs to userspace to help debugging the low power issues. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 98ef36e3a94d..54ac2fef8b88 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -45,6 +46,11 @@ #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 #define PARF_SRIS_MODE 0x644 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c +#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_CFG 0x2c00 @@ -136,12 +142,14 @@ enum qcom_pcie_ep_link_status { * @pci: Designware PCIe controller struct * @parf: Qualcomm PCIe specific PARF register base * @elbi: Designware PCIe specific ELBI register base + * @mmio: MMIO register base * @perst_map: PERST regmap * @mmio_res: MMIO region resource * @core_reset: PCIe Endpoint core reset * @reset: PERST# GPIO * @wake: WAKE# GPIO * @phy: PHY controller block + * @debugfs: PCIe Endpoint Debugfs directory * @clks: PCIe clocks * @num_clks: PCIe clocks count * @perst_en: Flag for PERST enable @@ -155,6 +163,7 @@ struct qcom_pcie_ep { void __iomem *parf; void __iomem *elbi; + void __iomem *mmio; struct regmap *perst_map; struct resource *mmio_res; @@ -162,6 +171,7 @@ struct qcom_pcie_ep { struct gpio_desc *reset; struct gpio_desc *wake; struct phy *phy; + struct dentry *debugfs; struct clk_bulk_data *clks; int num_clks; @@ -447,6 +457,9 @@ static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio"); + pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); + if (IS_ERR(pcie_ep->mmio)) + return PTR_ERR(pcie_ep->mmio); syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); if (!syscon) { @@ -630,6 +643,37 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, } } +static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) +{ + struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *) + dev_get_drvdata(s->private); + + seq_printf(s, "L0s transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); + + seq_printf(s, "L1 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); + + seq_printf(s, "L1.1 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); + + seq_printf(s, "L1.2 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); + + seq_printf(s, "L2 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); + + return 0; +} + +static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) +{ + struct dw_pcie *pci = &pcie_ep->pci; + + debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs, + qcom_pcie_ep_link_transition_count); +} + static const struct pci_epc_features qcom_pcie_epc_features = { .linkup_notifier = true, .core_init_notifier = true, @@ -662,6 +706,7 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qcom_pcie_ep *pcie_ep; + char *name; int ret; pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); @@ -688,8 +733,21 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) if (ret) goto err_disable_resources; + name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); + if (!name) { + ret = -ENOMEM; + goto err_disable_irqs; + } + + pcie_ep->debugfs = debugfs_create_dir(name, NULL); + qcom_pcie_ep_init_debugfs(pcie_ep); + return 0; +err_disable_irqs: + disable_irq(pcie_ep->global_irq); + disable_irq(pcie_ep->perst_irq); + err_disable_resources: qcom_pcie_disable_resources(pcie_ep); @@ -703,6 +761,8 @@ static int qcom_pcie_ep_remove(struct platform_device *pdev) disable_irq(pcie_ep->global_irq); disable_irq(pcie_ep->perst_irq); + debugfs_remove_recursive(pcie_ep->debugfs); + if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) return 0; From patchwork Tue Aug 30 16:58:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43838C0502C for ; Tue, 30 Aug 2022 17:00:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231210AbiH3RAA (ORCPT ); Tue, 30 Aug 2022 13:00:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231280AbiH3Q7g (ORCPT ); Tue, 30 Aug 2022 12:59:36 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4207AB9F84 for ; Tue, 30 Aug 2022 09:59:22 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id jm11so11686561plb.13 for ; Tue, 30 Aug 2022 09:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=UaIe6nvb9frcJULOPfASw/VY+z26bpOj35NUY7Eb3q4=; b=hitW9hbwLBSxHNayK49JF5ArwQqrJeOxOxW1C+UiyuIgpAH9ZR1mv06WLURY7HQ+VD +2pZ6LIBbNBmyN9zegNKsarW2LgDyAujQ1Wqcp6CQo51mlfZTFGDjlUilznZWQvC2QVd 0Gjw7Y13K5zVXU0gBtq1X1zNQwKba0i/wdTsROv6i3Pk5H39bdGUDrGx9fRmNT0F74I+ m5r2ECNe6eAhJ9nsN4TEhyGj1GRWP9wPRYzLPqPUFaUpkLVFYxxBSc9hPV2KNI43bTyM GZDXy8F/TsxWHb/S5asGuTXjKM9Bs5Dg5J1EnbLTP7Iewva2r33p3c5et+RjpZlGOZ53 1dqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=UaIe6nvb9frcJULOPfASw/VY+z26bpOj35NUY7Eb3q4=; b=7LPZk2Wf8VpJIo1EcTFx79W1jeXK+294EiG7Wx1/J073uU0yzZYENaxPByfHIFrNSF DekYhYCGnpzfJKGUapeFp0yzvk7oy16aAbCoN3XYtiMO9ubUiJG+kfvl93oQA7wj3GWs KflXP3xu3Ijkkp8XPe+7UiZkwxH9MeBDavKt6WC6vM11CiINvapGOywJzp4B513S7nKt O7pdqJnRFvA2ZPONDauWPp1kLA7MOp9qVAU0q/P2nFlxfSFFSMMAyrG2m5MKb1ME0wCR 91q9KqSGvXujQOjpFBezuND+frglBtOasOZhbf+8LUDtUuQGSXJ6zo78TCWAWo4JlcC8 7D1A== X-Gm-Message-State: ACgBeo2DmmuDWHnsC0RCtIVGDAfz5tmmA7xJHB/JWksw9ERwlL8PLLHh gw0X9b3nJKZDXHGu8jcpoWbX X-Google-Smtp-Source: AA6agR6OxuuAcOe3ofjgEL/FypzzZuaumsVigWO3yWd4uCKf96ZKLzSl+8j+IuditYFIgqFzG5WCNw== X-Received: by 2002:a17:902:f68d:b0:172:a34c:ff96 with SMTP id l13-20020a170902f68d00b00172a34cff96mr22025807plg.26.1661878761986; Tue, 30 Aug 2022 09:59:21 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:21 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v2 07/11] dt-bindings: PCI: qcom-ep: Make PERST separation optional Date: Tue, 30 Aug 2022 22:28:13 +0530 Message-Id: <20220830165817.183571-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PERST separation is an optional debug feature used to collect the crash dump from the PCIe endpoint devices by the PCIe host when the endpoint crashes. This feature keeps the PCIe link up by separating the PCIe IP block from the SoC reset logic. So remove the corresponding property "qcom,perst-regs" from the required properties list. Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 3d23599e5e91..b728ede3f09f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -105,7 +105,6 @@ required: - reg-names - clocks - clock-names - - qcom,perst-regs - interrupts - interrupt-names - reset-gpios From patchwork Tue Aug 30 16:58:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 108AFECAAA1 for ; Tue, 30 Aug 2022 17:00:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231286AbiH3RAG (ORCPT ); Tue, 30 Aug 2022 13:00:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231290AbiH3Q7k (ORCPT ); Tue, 30 Aug 2022 12:59:40 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9AFDF7B33 for ; Tue, 30 Aug 2022 09:59:28 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id v5so5497375plo.9 for ; Tue, 30 Aug 2022 09:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=LclRCur2+TmOph0Lw8Vjg5+TpaDfY+BX1hQtzMBpEmo=; b=h07RNOiqIlifbVpVHPhKfocZqgUpN4BvEgeIwwO+HVIgjWt+AZh5u8gy7bLTmU5uxJ NM7+dPKAfaGu5MM2RzTY1UANAfe1XiFA7G1YRTO0fWNgyOZPYgMa98O0R1K4qu6HI9UX MS6Rnea3jJIGCC04cVEMVLRaNQAsGleKSMz5pb1CPwHufS2UQ6CV29dnga0JnQgNIqaA Vm5+k48j5mGsQYBuRyNdmTqR0mrGlBQDjPot5rBL/iym1/6RN6lYnHktNMYf3kgnIkU0 yF+9WQRrUXWx61IGuHeTAWd7IFQcMVfwf+W7t9ly7APLAnL4lVK4HDFz6kgjRmKiSpZL ESxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=LclRCur2+TmOph0Lw8Vjg5+TpaDfY+BX1hQtzMBpEmo=; b=Ie2gKszg4zo8BXYLgR9JfUiPe2la/igJa88WvcAqz37NzCJQb1eVJyLWljclDdYdUB 1sWFPs20+kDiXxAOWfAQP6uJcq7h7XZuCkSNxWima68IAMEwbJx/NuU/zPR6tN/Gaq/X Z5aoExZAqyxeX0XeVYJgtXPRc2pNoSjX/PCaCVhowWGIe/OQHhwvsrS2shhLE7/oNO6A DqH/tsKNcduQFO9FIzIL2KkUMxKySkw12xpfTgTtlbEKpGnliGFt7a53XynsHu4ZOUZj TQYv2iYyT97N1MH22Ja8wrb1CMbfU1GShR/gLHaKcsmPo26e6r/HocVrPmU+QCdogLTd znVA== X-Gm-Message-State: ACgBeo3BwRudIzAGRqzifYAQUuftqJgJPNRp5Pi+iGOUuYa9JaCoVrQ6 EUFTA29VRm3pu0qhvGZy4Aei X-Google-Smtp-Source: AA6agR7rYHw3fJyVkM6r7m08BcCDtw/6FDziPykL8Mdo2fq4v4sP4oTJABmGn0nQ4ZViDEeSi+xc4Q== X-Received: by 2002:a17:902:f651:b0:174:3c03:6be3 with SMTP id m17-20020a170902f65100b001743c036be3mr20369034plg.113.1661878767273; Tue, 30 Aug 2022 09:59:27 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:26 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 08/11] PCI: qcom-ep: Make PERST separation optional Date: Tue, 30 Aug 2022 22:28:14 +0530 Message-Id: <20220830165817.183571-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PERST separation is an optional debug feature used to collect the crash dump from the PCIe endpoint devices by the PCIe host when the endpoint crashes. This feature keeps the PCIe link up by separating the PCIe IP block from the SoC reset logic. Hence, make the property optional in the driver. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 54ac2fef8b88..4908f08bd90b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -216,8 +216,10 @@ static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) */ static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) { - regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); - regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); + if (pcie_ep->perst_map) { + regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); + regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); + } } static int qcom_pcie_dw_link_up(struct dw_pcie *pci) @@ -463,8 +465,8 @@ static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); if (!syscon) { - dev_err(dev, "Failed to parse qcom,perst-regs\n"); - return -EINVAL; + dev_dbg(dev, "PERST separation not available\n"); + return 0; } pcie_ep->perst_map = syscon_node_to_regmap(syscon); From patchwork Tue Aug 30 16:58:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93F82ECAAD1 for ; Tue, 30 Aug 2022 17:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231318AbiH3RAF (ORCPT ); Tue, 30 Aug 2022 13:00:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231286AbiH3Q7j (ORCPT ); Tue, 30 Aug 2022 12:59:39 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FA14B603B for ; Tue, 30 Aug 2022 09:59:35 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id t129so11930650pfb.6 for ; Tue, 30 Aug 2022 09:59:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=+nFPGJL9DaKSTkpdD0XYV1f18/EerKy4FdCtQJJTq78=; b=lfYKqROpmRlpL3DqSB3zms6UXIsfrOhcyDkVHVwWGZBmQJlIujKVnDe0bdyC6sgfRj ftdTGzaBqQWGuuFzl8lPLDYvJjVzlxtjCN+BwQZ7TBAYHiuT4y4OC3g+75WjH9btWhB5 8VdqYpb4VvouExkYDPiys+cnmABpX+b09ekFCYrpw3l46AZtwG/HNFXGGzZGfWBcKiUz XjnV4OfrLh1NkRG3EcSURvdtK36MmvcpRG448GOo51Q2qqp1/CDjK+aC8qFeh27tdUmi hJnXjjJWUZpkuKXakafiA+diQVRNxW72lCGXGj5UGubrUXlirQvHdqqq2CFiSp+jCDX9 fKpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=+nFPGJL9DaKSTkpdD0XYV1f18/EerKy4FdCtQJJTq78=; b=xnWph+HcAOTKeM5bt71Xk9uTvAqbkutUxunRJfhO288exoi3qe+n/DyF0ZCJgBJ+m+ zroRZn8XzF6Cx34oZZMLW5hN1HzYrTEeHeBeK8QvhO+SjE/nqo8NPmV5T/Z4JXEQ4RuN p6Ql6Ig5vh+7B/P+FU5uIrw38x2b9Xgf9v5CrvIa8BxHLmjppWTNpnQ862Scc9U1rl4Q +V0U6jNDcMloXKRgPq+iFBCrHZXZZwWtQtlED4DBnQCMyc+KNvj6wsTszI5Zfbj4cFGk 38sto2hFDzZOdLtV0kxUpoEeA5URQfSLQFs6tHokyxD/wchGw6xiv/3Abe5l7vUXKvO0 Y/yg== X-Gm-Message-State: ACgBeo3HIOPWxPgV6mg0eoGC7Tm/jWAWePikCjsJI0JkG0YrPDzNX54b VgBnJiCC5ydXHZCixN9tQcQT X-Google-Smtp-Source: AA6agR4UjtYECqhqxWpR8YXyyfnUouq0WDy0qcGXLSRGaEeA4KOLING/BPaATbhjwzc+TK8sBdHqCQ== X-Received: by 2002:a62:ed08:0:b0:537:17a6:57aa with SMTP id u8-20020a62ed08000000b0053717a657aamr22483376pfh.6.1661878773041; Tue, 30 Aug 2022 09:59:33 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:32 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 09/11] dt-bindings: PCI: qcom-ep: Define clocks per platform Date: Tue, 30 Aug 2022 22:28:15 +0530 Message-Id: <20220830165817.183571-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation of adding the bindings for future SoCs, let's define the clocks per platform. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 51 ++++++++++++------- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index b728ede3f09f..a15e71491722 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -9,9 +9,6 @@ title: Qualcomm PCIe Endpoint Controller binding maintainers: - Manivannan Sadhasivam -allOf: - - $ref: "pci-ep.yaml#" - properties: compatible: const: qcom,sdx55-pcie-ep @@ -35,24 +32,10 @@ properties: - const: mmio clocks: - items: - - description: PCIe Auxiliary clock - - description: PCIe CFG AHB clock - - description: PCIe Master AXI clock - - description: PCIe Slave AXI clock - - description: PCIe Slave Q2A AXI clock - - description: PCIe Sleep clock - - description: PCIe Reference clock + maxItems: 7 clock-names: - items: - - const: aux - - const: cfg - - const: bus_master - - const: bus_slave - - const: slave_q2a - - const: sleep - - const: ref + maxItems: 7 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -112,6 +95,36 @@ required: - reset-names - power-domains +allOf: + - $ref: pci-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx55-pcie-ep + then: + properties: + clocks: + maxItems: 7 + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Sleep clock + - description: PCIe Reference clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: sleep + - const: ref + unevaluatedProperties: false examples: From patchwork Tue Aug 30 16:58:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43ED7ECAAD1 for ; Tue, 30 Aug 2022 17:00:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231264AbiH3RAi (ORCPT ); Tue, 30 Aug 2022 13:00:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231278AbiH3Q77 (ORCPT ); Tue, 30 Aug 2022 12:59:59 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BD51B6568 for ; Tue, 30 Aug 2022 09:59:40 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id l65so1569785pfl.8 for ; Tue, 30 Aug 2022 09:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=2RJUahJy1CyyeYAGPRglH4WrcYkv62869DWyoQBcRWE=; b=pcwKwURC2Ax+MN6ar7LnswMcMRwZPdCQFe65TAWQheKtwZO3XjYSU96z4atLSX3KjG RJfnEsmo6Z/xpDrewSftEYfuSud4J6JLMW07mnT7sVXNXDi8lAf2l8Mej4hDEjcqsm7z w4fpfQMxz8s7PYFdDI+ivUbzBhSble2UZ3lApsbcp3br9SwMfOi3+1c9rul5LYKDmcKo P34EvaM7ccBRH4cyeFHuJ23e8LRRck8xsWnRn5kFxkuH/MQoWvcVGmz3jTVBE2UOmEZ0 ovr9w8doTI/v1P7R2qB6aOEKj8ij5A3N4lP3cs0mKjPEl2oqVYzjyhQz9qyZmGFlldtr WfkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=2RJUahJy1CyyeYAGPRglH4WrcYkv62869DWyoQBcRWE=; b=MGqRFiOF5/v2qxEmkBuapKl4kCRNsDUUQgViPybfZ5NZTOe8v4/Ee9k9/ZUqx0Z+E5 nYDZgMTkCOomKybkLntd60CG7Swb5yrlsvKmcVGdHUlXp3yf3ua6AJOvQULAofIOf90G B5iSRuBQwFtBeK23qt/v+HJ5yqbumyOIuAZq22KaG8C5QpVOV78q//cRZs0MVaInxRc5 4ao1Xs7saIIlEkx/T1PuRtnbPI1iUc1ghHvKMg5Ecv+rYbGhMSV0WFPmi3dpveB4ixaH Iv/b2rpJDiElgQRWjmy7fATBqjYXg30Au+IYLLDC95gqBBUi+wrQk1hu65A2joPBPyau 4uyg== X-Gm-Message-State: ACgBeo3Ym6yBq4BoX7rxZT/+WpvtX9fUi6T8TIe9lq8gZ6aWyqzKoVuY clpEeVLG+UXP6CVHtKPxAgXZ X-Google-Smtp-Source: AA6agR7tRwab7rC6G1UrdgVxC/KvXmYce/f4rJKit37JFaFDyfHI0nKDM3EUg7fR4CJ8kjOEPuV7qQ== X-Received: by 2002:aa7:8393:0:b0:537:701d:e7f3 with SMTP id u19-20020aa78393000000b00537701de7f3mr22351779pfm.50.1661878778765; Tue, 30 Aug 2022 09:59:38 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:38 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 10/11] dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC Date: Tue, 30 Aug 2022 22:28:16 +0530 Message-Id: <20220830165817.183571-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree bindings support for SM8450 SoC. Only the clocks are different on this platform, rest is same as SDX55. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 40 +++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index a15e71491722..5902b45620ed 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: qcom,sdx55-pcie-ep + enum: + - qcom,sdx55-pcie-ep + - qcom,sm8450-pcie-ep reg: items: @@ -32,10 +34,12 @@ properties: - const: mmio clocks: - maxItems: 7 + minItems: 7 + maxItems: 8 clock-names: - maxItems: 7 + minItems: 7 + maxItems: 8 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -125,6 +129,36 @@ allOf: - const: sleep - const: ref + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-pcie-ep + then: + properties: + clocks: + maxItems: 8 + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Reference clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ref + - const: ddrss_sf_tbu + - const: aggre_noc_axi + unevaluatedProperties: false examples: From patchwork Tue Aug 30 16:58:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86E36ECAAA1 for ; Tue, 30 Aug 2022 17:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229852AbiH3RBF (ORCPT ); Tue, 30 Aug 2022 13:01:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230055AbiH3RA0 (ORCPT ); Tue, 30 Aug 2022 13:00:26 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75C9E6C751 for ; Tue, 30 Aug 2022 09:59:51 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id d12so11705582plr.6 for ; Tue, 30 Aug 2022 09:59:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=7Z3u13rYQpnMB98SibwD18Rv6bC0Tn7F50N9xepOERw=; b=sldTHnD1qgrZpMPHpc1hPZG8EsxLnZF132ClKRNUBn9xjfcdISQUHaSRPsK9Ez7dID n/3DLtYZz6U94P7tTy8lIoUIeJmhhye099Y7QSnwkvm2Ps5EcSj/Uj3WJYiQfm9z78rF CzJmqlgYAMidW9dafxB/dc2n4cHWdgFafkca2xIp9okVB/lNf/bvaa0Lcx0kODBRqo/B WlVqg+vCj0qccdihUJ2pGwdfFz0//9UDH7JCz0e1jU1gYd9ykASqoV1X1NG/IUho3QiU /p4fBEGQSaSprd7VWecqGwzwuJTxcS1DahcaE7vzE6JBBZh0dzsZ8DtLKQGAUOtJ21d8 bbnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=7Z3u13rYQpnMB98SibwD18Rv6bC0Tn7F50N9xepOERw=; b=vWW7ZkPLNWE6axrtVPv4L0f87WJfsopm/by3JtXQrguSVVFx/94EBSBPr60CkyWd7d 5cpuwdiJ6pPsqO91JarCK25ATHeS5NaYRJF9sZ+xcf9Xc7NxllPL9y9fO2HH7kaHcdzp PWOyf+FZ5m0rtzutWWz3T0CR4hQwlGtGemWZlIoVjTBFWAZsclk0uPw2ab0lq1VBPL7J 42QV+VZjWMlHLkzLATqk9CJuoKwmj5SOWkuGkzpJuixqwJsrdfpWcLpAzr5JV5DjdzYS zbqAaLMDXnN5ZXL//vpgEcuzgGUPDL73Sk8RfgPDFqopAl6Bia4m7HeI536Gceq5SkX3 8eIQ== X-Gm-Message-State: ACgBeo0vLEJCCNELlUua90tbH0UJE0LwlA3v3lI0SSsdpCvPTzbU9foD wuTtgbguCWUHLFhW5zhFDkLw X-Google-Smtp-Source: AA6agR4ZLBvQrgM2XBFylZu8fxpCao63txCa2/kmk9jdO5RVB55e818vG7ukPztVNGo9hdb2mz+ZXA== X-Received: by 2002:a17:902:e382:b0:173:36e4:ede6 with SMTP id g2-20020a170902e38200b0017336e4ede6mr21241607ple.139.1661878784846; Tue, 30 Aug 2022 09:59:44 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:44 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 11/11] PCI: qcom-ep: Add support for SM8450 SoC Date: Tue, 30 Aug 2022 22:28:17 +0530 Message-Id: <20220830165817.183571-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for SM8450 SoC to the Qualcomm PCIe Endpoint Controller driver. The driver uses the same config as of the existing SDX55 chipset. So additional settings are not required. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 4908f08bd90b..fa1819c9f667 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -775,6 +775,7 @@ static int qcom_pcie_ep_remove(struct platform_device *pdev) static const struct of_device_id qcom_pcie_ep_match[] = { { .compatible = "qcom,sdx55-pcie-ep", }, + { .compatible = "qcom,sm8450-pcie-ep", }, { } };