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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:04 -0800 Message-Id: <20190211010829.29869-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 01/26] target/arm: Split out arm_sctlr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Minimize the number of places that will need updating when the virtual host extensions are added. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 ++++++++++++++++---------- target/arm/helper.c | 8 ++------ 2 files changed, 18 insertions(+), 16 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 29663a264d..20be9fb53a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2987,11 +2987,20 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) != 0; } +static inline uint64_t arm_sctlr(CPUARMState *env, int el) +{ + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return env->cp15.sctlr_el[1]; + } else { + return env->cp15.sctlr_el[el]; + } +} + + /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - int cur_el; - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { return @@ -3010,15 +3019,12 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) arm_sctlr_b(env) || #endif ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + } else { + int cur_el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, cur_el); + + return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; } - - cur_el = arm_current_el(env); - - if (cur_el == 0) { - return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; - } - - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; } #include "exec/cpu-all.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 520ceea7a4..d4abbb5076 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13796,12 +13796,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } - if (current_el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[current_el]; - } + sctlr = arm_sctlr(env, current_el); + if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether From patchwork Mon Feb 11 01:08:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157940 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2056893jaa; Sun, 10 Feb 2019 17:11:52 -0800 (PST) X-Google-Smtp-Source: AHgI3IbahiVJLDr58TmUl0lqm+H0AopeEnzfVV+8D1AlHQu+FVXk7T2CzKw0h8bta2T3HG2wMkGT X-Received: by 2002:adf:f28d:: with SMTP id k13mr26304206wro.78.1549847512751; Sun, 10 Feb 2019 17:11:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847512; cv=none; d=google.com; s=arc-20160816; b=xvzBJC5fd4xD5w2GGkzB2JNAnp0+3Sk4vDcqe7pGTlzErslYzMAZebkEgwLYo3JLHe 9WvRpyQ0VKsFAr3PSvU36MqULc9BEv2QfaXQCZM6eRYabEY0gEew0/wEL41KXo8dn05d VKOrKQy4ZZAp8f98744jWbTpafalFlMcTEujIvDmU6rWdwPPW0L8qy6VUrKmBxdJ6HHC uVPmZUh3SLqKji4YwcxjR5BbqEcXi2ezHXnNrIHcy2roSEgTKl7H3G5BBR8FKNre3uMr Mj64+RV5NG8sCbqasQ0su2Jh68BLKqI/3FYn+6tQJxD7mDulvI5x/BUXBJscfldscSWk IdbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hbKS6AD3am/sY2oZ+gJOc5vr5/ws9wlGISFwMC+r3mY=; b=XUhqLg8q7ytXQiw1MTfsfDaB8vYwq24XT5a1c2NsYCMO0I8Stg9FcquIYZBJQiM1hD IHTDdDhohCl6pnwBazFb7IHGgn+en3yXi/LctS6KTs0gAOz0o8cVDDgO3hvkQE/wYnL9 fblNIQP/zyYUcnz5iV7H8s1ZmHbWwL8z60XTmm9x/2ppF/vZn9wx1Yf6QcBXTgZeUJiq qPNYA3NtjxTI81asL4wPgz9YL6uXiP+NvN/Wj2b++ILDPTmAMW2PBS2aRY3NSMpL2hNv 33VyMelrEIRZ0CJG+k/c6t7xtANjBXfX0hADOdYOYfjtiHp8KDvG2zKpEpvAUyr5hAYC LJvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=q0QbfSM7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:05 -0800 Message-Id: <20190211010829.29869-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 02/26] target/arm: Split helper_msr_i_pstate into 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The EL0+UMA check is unique to DAIF. While SPSel had avoided the check by nature of already checking EL >= 1, the other post v8.0 extensions to MSR (imm) allow EL0 and do not require UMA. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 3 +++ target/arm/helper.h | 1 - target/arm/internals.h | 15 ++++++++++++++ target/arm/helper-a64.c | 30 +++++++++++++++++++++++++++ target/arm/op_helper.c | 42 -------------------------------------- target/arm/translate-a64.c | 41 ++++++++++++++++++++++--------------- 6 files changed, 73 insertions(+), 59 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index aff8d6c9f3..a915c1247f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,9 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_2(msr_i_spsel, void, env, i32) +DEF_HELPER_2(msr_i_daifset, void, env, i32) +DEF_HELPER_2(msr_i_daifclear, void, env, i32) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..28b1dd6252 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,7 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) -DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) DEF_HELPER_2(get_r13_banked, i32, env, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..587a1ddf58 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); +static inline int exception_target_el(CPUARMState *env) +{ + int target_el = MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + #endif diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 101fa6d3ea..87b8f36122 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -61,6 +61,36 @@ uint64_t HELPER(rbit64)(uint64_t x) return revbit64(x); } +void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) +{ + update_spsel(env, imm); +} + +static void daif_check(CPUARMState *env, uint32_t op, + uint32_t imm, uintptr_t ra) +{ + /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ + if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { + raise_exception_ra(env, EXCP_UDEF, + syn_aa64_sysregtrap(0, extract32(op, 0, 3), + extract32(op, 3, 3), 4, + imm, 0x1f, 0), + exception_target_el(env), ra); + } +} + +void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1e, imm, GETPC()); + env->daif |= (imm << 6) & PSTATE_DAIF; +} + +void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1f, imm, GETPC()); + env->daif &= ~((imm << 6) & PSTATE_DAIF); +} + /* Convert a softfloat float_relation_ (as returned by * the float*_compare functions) to the correct ARM * NZCV flag state. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..c5721a866d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -68,20 +68,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, cpu_loop_exit_restore(cs, ra); } -static int exception_target_el(CPUARMState *env) -{ - int target_el = MAX(1, arm_current_el(env)); - - /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL - * to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { - target_el = 3; - } - - return target_el; -} - uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, uint32_t maxindex) { @@ -875,34 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) return res; } -void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) -{ - /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. - * Note that SPSel is never OK from EL0; we rely on handle_msr_i() - * to catch that case at translate time. - */ - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { - uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3), - extract32(op, 3, 3), 4, - imm, 0x1f, 0); - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)); - } - - switch (op) { - case 0x05: /* SPSel */ - update_spsel(env, imm); - break; - case 0x1e: /* DAIFSet */ - env->daif |= (imm << 6) & PSTATE_DAIF; - break; - case 0x1f: /* DAIFClear */ - env->daif &= ~((imm << 6) & PSTATE_DAIF); - break; - default: - g_assert_not_reached(); - } -} - void HELPER(clear_pstate_ss)(CPUARMState *env) { env->pstate &= ~PSTATE_SS; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 27b90d5778..13e010d27b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1647,29 +1647,38 @@ static void handle_sync(DisasContext *s, uint32_t insn, static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int crm) { + TCGv_i32 t1; int op = op1 << 3 | op2; + + /* End the TB by default, chaining is ok. */ + s->base.is_jmp = DISAS_TOO_MANY; + switch (op) { case 0x05: /* SPSel */ if (s->current_el == 0) { - unallocated_encoding(s); - return; + goto do_unallocated; } - /* fall through */ - case 0x1e: /* DAIFSet */ - case 0x1f: /* DAIFClear */ - { - TCGv_i32 tcg_imm = tcg_const_i32(crm); - TCGv_i32 tcg_op = tcg_const_i32(op); - gen_a64_set_pc_im(s->pc - 4); - gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); - tcg_temp_free_i32(tcg_imm); - tcg_temp_free_i32(tcg_op); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ - gen_a64_set_pc_im(s->pc); - s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); + t1 = tcg_const_i32(crm & PSTATE_SP); + gen_helper_msr_i_spsel(cpu_env, t1); + tcg_temp_free_i32(t1); break; - } + + case 0x1e: /* DAIFSet */ + t1 = tcg_const_i32(crm); + gen_helper_msr_i_daifset(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + + case 0x1f: /* DAIFClear */ + t1 = tcg_const_i32(crm); + gen_helper_msr_i_daifclear(cpu_env, t1); + tcg_temp_free_i32(t1); + /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ + s->base.is_jmp = DISAS_UPDATE; + break; + default: + do_unallocated: unallocated_encoding(s); return; } From patchwork Mon Feb 11 01:08:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157949 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2060740jaa; Sun, 10 Feb 2019 17:17:50 -0800 (PST) X-Google-Smtp-Source: AHgI3IYd8T+8EO/npusv5LfYSkas34Ipinn+jw1VsCWibFm7FMkYeUNQ7R9TQgbM/3pySqEdZ/N6 X-Received: by 2002:a5d:44d1:: with SMTP id z17mr20767914wrr.271.1549847869949; Sun, 10 Feb 2019 17:17:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847869; cv=none; d=google.com; s=arc-20160816; b=RALJFO1Jg6HcApouZTWP3TPmK93LP0qGJOoERuy9O6Uvbx3Gaat3o82ub62d9/cVOE aTmchDzMjK7ITB2uUXsrVjRTQIGWKpHuH1y/bbfBSgO7vjhrr9n3MBSJf85GWAQqrtzD gtVXpt9ceghdAboKIGeITEpyg3o5KW08ICJGIDUG9fI+EKwijD8/jw/Wlm7rtEBDmjO4 8xMn0DlK/LMB7OnNPWhlJgrQxjZpVORaOheKLhyBmP0Pafi2atQEl5yyyZti6QbmatqR ab0T2kB3h3sV+OtW07r+H12OT2/emcAgwmWN18SLeDoF8ObdhMwzQ2cX+VSfq8TQAL6h kD8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ItNJF+IPQ2RCWNqC/N6zjDNVc+cTfSXBzvGik2fXPgw=; b=Khle+JikHqN0exxM5CbqTLDjj8JFlQMQLYx1Ii5BMEuDrakb+1M/fv4nVxzbI5R5iU AcGT3u+wIEv446Har5qK4OHtCzIY2Op685p6ZLnHnpV6bz7o9GBBInlfDVbrtOOwhnHA xHzzXvQI/F0avW/sR1da0oij4JdKh4fXevN7XfMURjRsNttWKU7KxWyv1qr5q7+2cUHe Uz20VGlaFcMj0YkGwy/iD6VWR+c/ZxM2M79g6hH3GzII3M0HGzve/7CKTvFRheHwqqJ2 FR1wmUGnz2nICyDAwsy1YddcD19yBC7x9N1+NlvvAUe3Pojw1MmpXsFV2ZEgnTrK00rC cgPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EQslcFme; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:06 -0800 Message-Id: <20190211010829.29869-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 03/26] target/arm: Add clear_pstate_bits, share gen_ss_advance X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not need an out-of-line helper for clearing bits in pstate. While changing things, share the implementation of gen_ss_advance. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/translate.h | 19 +++++++++++++++++++ target/arm/op_helper.c | 5 ----- target/arm/translate-a64.c | 11 ----------- target/arm/translate.c | 11 ----------- 5 files changed, 19 insertions(+), 29 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.h b/target/arm/helper.h index 28b1dd6252..c21fa2edfe 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,8 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) -DEF_HELPER_1(clear_pstate_ss, void, env) - DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 17748ddfb9..33af50a13f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -202,6 +202,25 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } +/* Clear bits within PSTATE. */ +static inline void clear_pstate_bits(uint32_t bits) +{ + TCGv_i32 p = tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i32(p, p, ~bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + +/* If the singlestep state is Active-not-pending, advance to Active-pending. */ +static inline void gen_ss_advance(DisasContext *s) +{ + if (s->ss_active) { + s->pstate_ss = 0; + clear_pstate_bits(PSTATE_SS); + } +} /* Vector operations shared between ARM and AArch64. */ extern const GVecGen3 bsl_op; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c5721a866d..8698b4dc83 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -861,11 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) return res; } -void HELPER(clear_pstate_ss)(CPUARMState *env) -{ - env->pstate &= ~PSTATE_SS; -} - void HELPER(pre_hvc)(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 13e010d27b..ba139bba26 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -421,17 +421,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, s->base.is_jmp = DISAS_NORETURN; } -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss = 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..baf6068ec1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -298,17 +298,6 @@ static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) tcg_temp_free_i32(tcg_excp); } -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss = 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:07 -0800 Message-Id: <20190211010829.29869-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 04/26] target/arm: Add MTE_ACTIVE to tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE, then arrange to perform the check while stripping the TBI. The check is not yet implemented, just the plumbing to that point. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Clean TBI bits exactly. Fix license to lgpl 2.1. --- target/arm/cpu.h | 12 ++++++++ target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 18 ++++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 51 ++++++++++++++++++++++++++-------- target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++- target/arm/Makefile.objs | 2 +- 8 files changed, 140 insertions(+), 13 deletions(-) create mode 100644 target/arm/mte_helper.c -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 20be9fb53a..2776df6981 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1215,6 +1215,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3071,6 +3072,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 14, 1) static inline bool bswap_code(bool sctlr_b) { @@ -3361,6 +3363,16 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; } +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..fa4c371a47 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,5 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..6c018e773c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -983,4 +983,22 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr != 0; +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index 33af50a13f..5a101e1c6d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -70,6 +70,8 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE tag checks affect the PE. */ + bool mte_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index d4abbb5076..e73bdbf041 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1862,6 +1862,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= SCR_ATA; + } /* Clear all-context RES0 bits. */ value &= valid_mask; @@ -4056,22 +4059,31 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = arm_env_get_cpu(env); - if (raw_read(env, ri) == value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { /* M bit is RAZ/WI for PMSA with no MPU implemented */ value &= ~SCTLR_M; } - raw_write(env, ri, value); + if (!cpu_isar_feature(aa64_mte, cpu)) { + if (ri->opc1 == 6) { /* SCTLR_EL3 */ + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); + + if (raw_read(env, ri) != value) { + /* + * This may enable/disable the MMU, so do a TLB flush. + * Skip the TLB flush if nothing actually changed; + * Linux likes to do a lot of pointless SCTLR writes. + */ + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4564,6 +4576,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= HCR_API | HCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= HCR_ATA; + } /* Clear RES0 bits. */ value &= valid_mask; @@ -13756,6 +13771,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); uint64_t sctlr; + int tbid; *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13764,7 +13780,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; + int tbii; /* FIXME: ARMv8.1-VHE S2 translation regime. */ if (regime_el(env, stage1) < 2) { @@ -13817,6 +13833,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + + /* + * If MTE is enabled, and tag checks affect the PE, + * then we check the tag as we strip the TBI field. + * Note that if TBI is disabled, all accesses are unchecked. + */ + if (tbid + && cpu_isar_feature(aa64_mte, cpu) + && allocation_tag_access_enabled(env, current_el, sctlr) + && !(env->pstate & PSTATE_TCO) + && (sctlr & (current_el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 0000000000..f1174d6f9f --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,57 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) +{ + /* + * We know some TBI is enabled, because MTE is enabled enough to + * arrive here. We simply need to check how to apply the TBI strip. + */ + if (arm_current_el(env) >= 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + /* Only one address space half, and TBI enabled. */ + return extract64(ptr, 0, 56); + } else { + /* + * Two address space halves, but we don't know for sure that + * TBI is enabled for both halves. Check. + */ + uint64_t tcr = env->cp15.tcr_el[1].raw_tcr; + bool tbi = extract64(tcr, 37 + extract64(ptr, 55, 1), 1); + + if (tbi) { + return sextract64(ptr, 0, 56); + } + return ptr; + } +} + +uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) +{ + /* Only unchecked implemented so far. */ + return strip_tbi(env, ptr); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ba139bba26..e782a0e579 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -343,7 +343,13 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean = new_tmp_a64(s); - gen_top_byte_ignore(s, clean, addr, s->tbid); + + /* FIXME: SP+OFS is always unchecked. */ + if (s->tbid && s->mte_active) { + gen_helper_mte_check(clean, cpu_env, addr); + } else { + gen_top_byte_ignore(s, clean, addr, s->tbid); + } return clean; } @@ -14041,6 +14047,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->mte_active = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1a4fc06448..c86cb1af5c 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,7 +8,7 @@ obj-y += translate.o op_helper.o helper.o cpu.o obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o obj-y += gdbstub.o obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-$(TARGET_AARCH64) += pauth_helper.o +obj-$(TARGET_AARCH64) += pauth_helper.o mte_helper.o obj-y += crypto_helper.o obj-$(CONFIG_SOFTMMU) += arm-powerctl.o From patchwork Mon Feb 11 01:08:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157950 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2061186jaa; Sun, 10 Feb 2019 17:18:34 -0800 (PST) X-Google-Smtp-Source: AHgI3IbvzGBI+YqouASE+Z3JkYsqNeseDZgXd3LYI/BjTSYVCHTodDkzgHDN/7O+024HgN2ksMmh X-Received: by 2002:a1c:7710:: with SMTP id t16mr6818296wmi.81.1549847914606; Sun, 10 Feb 2019 17:18:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847914; cv=none; d=google.com; s=arc-20160816; b=RT8fgx07mZfV0Sj5VHKKC9vRQDN8CF4Sbxazy2Af0q0focD29VXp+DKTQOyvQGftgf IAgBbvXmSihERciGywFg1B4uVafHtH0pJOzkyjtB+twbQaYtdmJqY/91uLXt9XWs3TBo 9oYH6hn3u6trl6IjZ/pscrdLH/+xCQ0eqAyRyLYxToug+IAG1z7W/eABlfIRwmqwgf3u 55QipfBFJsBx5ju0qZNuHAglI9ozadfmaAuc2WkZWE3bdwsb2DNFJ1i2IoKyQ9cLz9nV qNxOZK+HbyUy/uWQQNn13mtKx9Q9zMvBSqQRFRClfWxTC/JDDppcNqPQ+g9cpY/41dmf Bb5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sSJPTVVkjcWARcwigg6wJDNen7ofl5R1qSbWzhReSSs=; b=bWJmKSIZzjCSAlmPLT0zIcOileZs7RNmhWEKMWCpe2RTWAlJJsz6AdnmiqC/p1YaYN 2QDbFp1EPQBbN2jvOvDZ1xvg/piUcMsGuFtoT+VN4NGtC2XPhqWD8P50eBUb2ROYK7Nr zRZiNX4TgyYNLE/3mN/zBDiaip4/txbYxq0gR18zsxLjZaf4cZyerSD9oMPnhvQrSnpa FlsQF5jBmCrAWE0y1wFHrzFj+T8h0i4EDWElZ4mNZjM2KXV70ZCuuDX4Y67mQT6KIXyq 2NnE94YoI77OvuOjQETbrylQLwpGeSqgsoWYG4+Pqg10kFwrXQBFraReju4o9zx2WbHw fcxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FQDvJD7X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:08 -0800 Message-Id: <20190211010829.29869-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 05/26] target/arm: Extract TCMA with ARMVAParameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c018e773c..2922324f63 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -959,6 +959,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; diff --git a/target/arm/helper.c b/target/arm/helper.c index e73bdbf041..cbe3500f78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10447,7 +10447,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; /* @@ -10462,11 +10462,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi = tbid = hpd = false; + tbi = tbid = hpd = tcma = false; } else { tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); tbid = extract32(tcr, 29, 1); + tcma = extract32(tcr, 30, 1); } epd = false; } else if (!select) { @@ -10477,6 +10478,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); tbid = extract64(tcr, 51, 1); + tcma = extract64(tcr, 57, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; @@ -10486,6 +10488,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); tbid = extract64(tcr, 52, 1); + tcma = extract64(tcr, 58, 1); } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -10497,6 +10500,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, .tbid = tbid, .epd = epd, .hpd = hpd, + .tcma = tcma, .using16k = using16k, .using64k = using64k, }; From patchwork Mon Feb 11 01:08:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157941 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2057233jaa; Sun, 10 Feb 2019 17:12:21 -0800 (PST) X-Google-Smtp-Source: AHgI3IahNQeKMsvDcGk1ClwMYIPKzQhGBtgD+jwCRcALpGH40XQFhVpNqK1EE71q+AnwCX7wCLDM X-Received: by 2002:a5d:4b07:: with SMTP id v7mr16119475wrq.281.1549847541842; Sun, 10 Feb 2019 17:12:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847541; cv=none; d=google.com; s=arc-20160816; b=0xEwCHpGP1SumebWxbG/fe+CYwVXmzVDPgnXTCjK5rpK0xv7tvR9YnVhTnZSFfyDLj 1VzCD4CMTZoeA3xGKQnW31DOdHTKSPgipjc7Ct9h03mRzOd2T7MAjpC1HwSOod1Wfaet k6GU5b39QVK8gJzGifMJy2UatgmWox/5F+e1dp1Ql8ADvuFaOinUYBCMSc7nW4/qSREy PqRO2H5Qpv460VAgXpXLYlsdl1e5Cx9ru4SbPBJWOHn6RjjAhkKPOSF61XfU0SSEKmuf 2aF3WNMH4vdTadTCh14BY37X5VT2kkiuNNDYSGdKzqSJ7WulP6b2NrpuVzMWFvxb8lyc 3+Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=EkQDtq1xSIGU1XROXRBBDpDZ5vELkcoeXfK8fEl97xA=; b=GDkP+MWVoU75aN5BVQ6Xig98EQg79Ae85+FI6gZEamHLzTIabNUnSeoNpv/vu5yXN5 1ImY1pBuv2fwYrTXcurvL6NQjf55Ne90H0X4Jv+JPifuJZwLgESFse6OqgRYOBkIHOId fFow2SKxdqpZDfCSjw7m+JYAKXVaVkaZRPB4rcDnMPNbHCijU9ivBzo64JETbsoqCkLz 5w3CnFvk77HKxT0dAkZf2k7R/Qf2/dIJg7V3oJM+aUlrmZFf/jDdnBT/Rx+x7YDDyQX1 DKEJ07GlyU8FKIvhgaahuLoaI7plI1UxNWCVmR+b0XgJz5YTz+Z0iRZNJOOOvI24uSGw 1PaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XGdu+rT5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:09 -0800 Message-Id: <20190211010829.29869-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 06/26] target/arm: Add MTE system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/translate.h | 11 ++++++++++ target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 ++++++++++ 4 files changed, 72 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2776df6981..74633a7a78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -495,6 +495,11 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ +#ifdef TARGET_AARCH64 + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; +#endif } cp15; struct { diff --git a/target/arm/translate.h b/target/arm/translate.h index 5a101e1c6d..a24757d3d7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,17 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } +/* Set bits within PSTATE. */ +static inline void set_pstate_bits(uint32_t bits) +{ + TCGv_i32 p = tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i32(p, p, bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + /* Clear bits within PSTATE. */ static inline void clear_pstate_bits(uint32_t bits) { diff --git a/target/arm/helper.c b/target/arm/helper.c index cbe3500f78..2d9c070bb3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5732,6 +5732,48 @@ static const ARMCPRegInfo pauth_reginfo[] = { .fieldoffset = offsetof(CPUARMState, apib_key.hi) }, REGINFO_SENTINEL }; + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) +{ + env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] = { + { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 6, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 6, .opc2 = 0, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, + { .name = "TCO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, + .type = ARM_CP_NO_RAW, + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, + REGINFO_SENTINEL +}; #endif void register_cp_regs_for_features(ARMCPU *cpu) @@ -6577,6 +6619,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e782a0e579..8e9f40f2a6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1672,6 +1672,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_UPDATE; break; + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s); From patchwork Mon Feb 11 01:08:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157943 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2057615jaa; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:10 -0800 Message-Id: <20190211010829.29869-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PATCH v2 07/26] target/arm: Assert no manual change to CACHED_PSTATE_BITS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits are stored elsewhere; changing env->pstate has no effect. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 diff --git a/target/arm/translate.h b/target/arm/translate.h index a24757d3d7..296d1ac72c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -209,6 +209,8 @@ static inline void set_pstate_bits(uint32_t bits) { TCGv_i32 p = tcg_temp_new_i32(); + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ori_i32(p, p, bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); @@ -220,6 +222,8 @@ static inline void clear_pstate_bits(uint32_t bits) { TCGv_i32 p = tcg_temp_new_i32(); + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_andi_i32(p, p, ~bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); From patchwork Mon Feb 11 01:08:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157953 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2063510jaa; Sun, 10 Feb 2019 17:22:23 -0800 (PST) X-Google-Smtp-Source: AHgI3IZIlLoAj2mz4pmPDiW4wOlWApnJX9En2Enq+LzkTiPcDhpOTFa6BaQKD0FxCwLdRBZqzzQB X-Received: by 2002:adf:ec47:: with SMTP id w7mr23242867wrn.8.1549848143546; Sun, 10 Feb 2019 17:22:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848143; cv=none; d=google.com; s=arc-20160816; b=mnf7yLCnKoOwid2RhPsmy/aw6GDJwTT0BWOsh/nsFTJJyw03aSNVJSeIRqnyP7vEOA VcWx/9OO13wNI7tHQWePKg3/m0x7wdpmfdxqSnNR0HQwGy3GWSPBSoMBpbcRsl9+TwaI 6hPsuGc9mNLDjPjZGjZJ/SHNf/Hj6V0eomrBhEPm6EyMR0913WgloM1iCZYKihQAl25f WHbNov1UVlLBGv5pfQNrCxZvPgaq2q+U3/w738ywBwOEe5whzXPPCLXmhBAAnrA9oNjz B8Ha2hvw1aLFtfH9LDXBZmQeQ3onGRUm9VSR1zOeMAQnGoxFTjXJp5uoLpDM4XDmyb7u EpTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=btPp8hltDkFrd7qKQ50LGQORF7TOq+f4+8xGAfmBZ5M=; b=zcAWarDqxyWQsApIH1+QUdK4n2qbjboVNC3ZYTwk7ey7eTZkFwW/Dleb7hEztEV2Rs b4Zv2LHbn5jXmMU2x2jjBuw2V6zwHAwFtlLUNH2QlUHZo0oscW2ih3VbSvR/ngWidDdN KrrGhnmjtVPQiLIwWnp3BOjvWUgmYu/LXVyjbzK/pjJ87wSbQ7iNBSgEYvFh2Qe0Gy2j 9WT1FryZg30dMiK+0ntFdf6n+vMUrntZOZnk4pqUHsdqvSfXVicWkQyG6KG3HNuA+xU6 gmJv3ZK7ee7XyW2u0rzWUWdT0VXdcpFchwSGnj6iUyD81zhpdJUpx6rlbkCpHRYPFTR3 09KQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sJ6MFe1O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:11 -0800 Message-Id: <20190211010829.29869-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PATCH v2 08/26] target/arm: Fill in helper_mte_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already implied by TB_FLAGS_MTE_ACTIVE. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- v2: Fix TFSR update. --- target/arm/mte_helper.c | 94 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index f1174d6f9f..d086925a91 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,6 +25,8 @@ #include "exec/helper-proto.h" +#if 0 +/* Don't break bisect. This will gain another user before we're done. */ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) { /* @@ -49,9 +51,97 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) return ptr; } } +#endif + +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ + return extract64(ptr, 56, 4); +} uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { - /* Only unchecked implemented so far. */ - return strip_tbi(env, ptr); + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, true); + int el = arm_current_el(env); + int ptr_tag, mem_tag; + uintptr_t ra = GETPC(); + + /* + * If TBI is disabled, then the access is unchecked. + * While we filtered out TBI0==0 && TBI1==0 in cpu_get_tb_cpu_state, + * we did not save separate bits for TBI0 != TBI1. + */ + if (!param.tbi) { + /* Do not ignore the top byte. */ + return ptr; + } + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules R0076 & R0077 are written with logical tags, + * and we need the physical tag below anyway. + */ + ptr_tag = allocation_tag_from_addr(ptr); + if (param.tcma && ptr_tag == 0) { + goto pass; + } + + /* + * If an access is made to an address that does not provide tag storage, + * the result is implementation defined (R0006). We choose to treat the + * access as unchecked. + * This is similar to MemAttr != Tagged, which are also unchecked. + */ + mem_tag = get_allocation_tag(env, ptr, ra); + if (mem_tag < 0) { + goto pass; + } + + /* If the tags do not match, the tag check operation fails. */ + if (ptr_tag != mem_tag) { + int tcf; + + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + tcf = extract64(env->cp15.sctlr_el[1], 38, 2); + } else { + tcf = extract64(env->cp15.sctlr_el[el], 40, 2); + } + if (tcf == 1) { + /* + * Tag check fail causes a synchronous exception. + * + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(ENV_GET_CPU(env), ra, true); + env->exception.vaddress = ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11), + exception_target_el(env)); + } else if (tcf == 2) { + /* Tag check fail causes asynchronous flag set. */ + env->cp15.tfsr_el[el] |= 1 << param.select; + } + } + + pass: + /* + * Unchecked, tag check pass, or tag check fail does not trap. + * Ignore the top byte. + */ + if (el >= 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return extract64(ptr, 0, 56); + } else { + return sextract64(ptr, 0, 56); + } } From patchwork Mon Feb 11 01:08:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157944 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2057736jaa; Sun, 10 Feb 2019 17:13:08 -0800 (PST) X-Google-Smtp-Source: AHgI3IbuwRbeVUyX9PmEDlZOh/WillW4kC9PtU2YnpGuFOrZ2WVvtlWUy3nttAQlW5rSyA2k3I2W X-Received: by 2002:adf:edd1:: with SMTP id v17mr12469482wro.300.1549847588204; Sun, 10 Feb 2019 17:13:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847588; cv=none; d=google.com; s=arc-20160816; b=XxOIFAq3cxrQxo/2t5DkChMGBkeq0/RhtETB22fkZV4hXY6idYZoDz8+Ku5YVGLyWS 84GV0nh9LV/OYlCmD86cHF2RHOpGI1Szdnr3DNWNTzZa5cJBy9R5XFfFOhap418yaiwd b2Tlox01AQcO+tnfMek3Gj2zNnqei1idNE8wJDQs1Qtt/gHJKY43F3QbKcsX1U4fn4tl k3sTco2OsWTrZmLmTRLw4DU2AGkJfFbuIj/vZkgaN6S+N2aau2edBnqIcqU3pbmIUOPb ihE0bNlORcKZWLE2SW49py58NvwDGnWxDfgRvEGl1ZDzFs9YuivrhxZRBVd0iev/6/1s 8uzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=EWm2iSaAOLbuCw7Om0ASn9c3AgIfiLyR0Kyc+wT9FkU=; b=vssVWGKM0mnJjNhclv6KC2QFXvpUJxR/Ya8RX8Gs+Ih/k7mLszP7aC/PSwXyjFtuN+ InMNlEfQ3YQCPVX1z4UzpG+aKzIge2Gt/l8NooapCjJteQyJyOqqEZ0hFOWL6NdLKoA1 g2NXdKh9YCTvsASVN+a9AeJUENOCSoeeFZdzA1QUWe2TwHJEfHLJi7t0lTZAIwxtkeW0 yafEpZXxJk4EKiXt6TuhKcBcxwO8XsFjod1SWmVzTEjaVjDVm+YrdDH6c4pe6e/LS9R4 iwUEhgDNAkDukTJzBrfA51mhjqW+1Z/Idzkw8807xa2OjsU4ANl0u+xcacz9cwGFyfKm nOow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lvp2di77; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:12 -0800 Message-Id: <20190211010829.29869-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 09/26] target/arm: Suppress tag check for sp+offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0078 specifies that base register, or base register plus immediate offset, is unchecked when the base register is SP. Signed-off-by: Richard Henderson --- v2: Include writeback addresses as checked. --- target/arm/translate-a64.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8e9f40f2a6..d0f8c314c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -340,12 +340,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) * This is always a fresh temporary, as we need to be able to * increment this independently of a dirty write-back address. */ -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool check) { TCGv_i64 clean = new_tmp_a64(s); - /* FIXME: SP+OFS is always unchecked. */ - if (s->tbid && s->mte_active) { + if (check && s->mte_active) { gen_helper_mte_check(clean, cpu_env, addr); } else { gen_top_byte_ignore(s, clean, addr, s->tbid); @@ -2379,7 +2378,7 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2397,7 +2396,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); if (size == 2) { TCGv_i64 cmp = tcg_temp_new_i64(); @@ -2522,7 +2521,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; @@ -2531,7 +2530,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2551,7 +2550,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2567,7 +2566,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2581,7 +2580,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2599,7 +2598,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2789,7 +2788,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); if (is_vector) { if (is_load) { @@ -2927,7 +2926,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, writeback || rn != 31); if (is_vector) { if (is_store) { @@ -3034,7 +3033,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, true); if (is_vector) { if (is_store) { @@ -3119,7 +3118,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, dirty_addr = read_cpu_reg_sp(s, rn, 1); offset = imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn != 31); if (is_vector) { if (is_store) { @@ -3203,7 +3202,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_rs = read_cpu_reg(s, rs, true); if (o3_opc == 1) { /* LDCLR */ @@ -3265,7 +3264,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, is_wback || rn != 31); tcg_rt = cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, @@ -3425,7 +3424,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) elements = (is_q ? 16 : 8) / ebytes; tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (r = 0; r < rpt; r++) { @@ -3568,7 +3567,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (xs = 0; xs < selem; xs++) { From patchwork Mon Feb 11 01:08:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157956 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2064600jaa; Sun, 10 Feb 2019 17:24:09 -0800 (PST) X-Google-Smtp-Source: AHgI3IYtxa+55R74hv/MFCq1YVYVPg6DMDonENve4acMwJNvUODjiDoMPl4CdgVUv6k0+zf+AUra X-Received: by 2002:a1c:27c7:: with SMTP id n190mr7178894wmn.67.1549848248952; Sun, 10 Feb 2019 17:24:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848248; cv=none; d=google.com; s=arc-20160816; b=CHqHctOEzUCW+EBLLvMK5qwCswidjqPvI8sAJal3Z8fjp15fJqt09VtI1LlTL2+tID yNQWGsI4AARyuPFl29BEtShGGk4ah+d16/b9aPbc+iqHtjCEWrNlZbzuwtqcJWqKLRjc yGfzDX5l+V9rhoiCOODRDM7udO91Jf3hqJs+jJ3ubtAdr4veLG5rZaElW09LLP56Tvot I5oeSGbKCb8JoO23/jAYnr2Ve5pqVQFgZl/3yxku6+G0+AlpL8QGL6rufHsXGBxVbjaU QxREYa26LbwgyBjrxBEH/n21eg3zOQnMD0fn02dKWAiU0FL/1LiMR3TEEHBDk6QqC17d WANQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=3Dd817zt1y/TGuEmTtxVfosE+MfIs8+VAHxl36iblpQ=; b=heRWFt2V4ePbOKWwRF+ZqYIeg0/7aqNALRykpRGTCNd2hI+Ud9kUTi5V8TzzB1c8Mg mwnMSFVYTFvfdCRXgA8GAYN/x+W0iz80toIUNJ/sCRyspgAILdUqKqPKJb63CjADvslY d6RPistgBEWAQRLSy4rBN9TMC2+wOqlO43ZkoiMXrFxURZMfQicme0XicjoXHCp8bzh4 kMzxSOA1gNkNCHDedtn9WzrEN5QWpnywF9dbkwLCPxlyuamWWHlVv7Hfn+Ks4YgvPVkd FAya1vOaPjsi6Sm0iklCyCA6OdJELJXUYPZEz6rYW4S7CiMKvSgY+x4tdedGCmKzqStN SQ1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TwELF4Am; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 10/26] target/arm: Implement the IRG instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Update to 00eac5. Merge choose_random_nonexcluded_tag into helper_irg since that pseudo function no longer exists separately. --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 +++++ 3 files changed, 65 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index fa4c371a47..7a6051fdab 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,3 +104,4 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d086925a91..493c2f7bb2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -65,6 +65,31 @@ static int allocation_tag_from_addr(uint64_t ptr) return extract64(ptr, 56, 4); } +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude == 0xffff) { + return 0; + } + if (offset == 0) { + while (exclude & (1 << tag)) { + tag = (tag + 1) & 15; + } + } else { + do { + do { + tag = (tag + 1) & 15; + } while (exclude & (1 << tag)); + } while (--offset > 0); + } + return tag; +} + +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + rtag -= extract64(ptr, 55, 1); + return deposit64(ptr, 56, 4, rtag); +} + uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); @@ -145,3 +170,35 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) return sextract64(ptr, 0, 56); } } + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + /* + * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if + * GCR_EL1.RRND==0, always producing deterministic results. + */ + uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); + int start = extract32(env->cp15.rgsr_el1, 0, 4); + int seed = extract32(env->cp15.rgsr_el1, 8, 16); + int offset, i; + + /* RandomTag */ + for (i = offset = 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed = (top << 15) | (seed >> 1); + offset |= top << i; + } + rtag = choose_nonexcluded_tag(start, offset, exclude); + + env->cp15.rgsr_el1 = rtag | (seed << 8); + } + + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d0f8c314c9..5e7d7f2d5e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5126,6 +5126,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Mon Feb 11 01:08:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157958 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2064828jaa; Sun, 10 Feb 2019 17:24:31 -0800 (PST) X-Google-Smtp-Source: AHgI3IYVaQdPAnobNbKligUwceOYxC8g5xSBl/GzEhNLU9TOf2Ycj/t1OIUvL/5ZymkIn6IjFlsg X-Received: by 2002:a1c:ed17:: with SMTP id l23mr7447881wmh.51.1549848271907; Sun, 10 Feb 2019 17:24:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848271; cv=none; d=google.com; s=arc-20160816; b=ez727xInWBebN+/I/IBnTNNSoWN0U59z7unED7GqlT9N/B4G63FA1PF+qkpR0AITsW LWQQxiD5k7bdqJbuFxz1YM9zgAkSp8VRuCahcQ/f9Lw4GE2s87dfzU9kUaV/+2Ju/Xvb y83r68t1IY2f75FMacVBuIPUL7wbEmbFqwIGivHA8tmYKEES6/bP+VxWwVf+613QcHSC fYvSQMdPvDYiYVFGI/d7xT7pPMPvW2znxxWbIGCxznMGEwJtA/mt1nqU1t9wO0KgI/E+ PRMCC/Bd3CnaNSP1KihQpdDYjzBEwAqaCssXM6QlcKQkJnMYGkfVT0xkqgJ5hPk0iFkp +i0A== ARC-Message-Signature: i=1; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:14 -0800 Message-Id: <20190211010829.29869-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PATCH v2 11/26] target/arm: Implement ADDG, SUBG instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Shift offset in translate; use extract32. --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 3 ++ target/arm/mte_helper.c | 32 +++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 85 insertions(+), 23 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7a6051fdab..47577207b2 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,5 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2922324f63..a5a249b001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,4 +1002,7 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, return sctlr != 0; } +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 493c2f7bb2..3eb5d622fc 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -202,3 +202,35 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5e7d7f2d5e..3d71a9701f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3672,7 +3672,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3683,10 +3685,10 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) bool setflags = extract32(insn, 29, 1); bool sub_op = extract32(insn, 30, 1); bool is_64bit = extract32(insn, 31, 1); + bool is_tag = false; TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; switch (shift) { case 0x0: @@ -3694,35 +3696,58 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) case 0x1: imm <<= 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag = true; + break; default: + do_unallocated: unallocated_encoding(s); return; } - tcg_result = tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm = tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset = tcg_const_i32(imm & 15); + TCGv_i32 offset = tcg_const_i32((imm >> 6) << LOG2_TAG_GRANULE); - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result = tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm = tcg_const_i64(imm); + tcg_result = new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } /* The input should be a value in the bottom e bits (with higher From patchwork Mon Feb 11 01:08:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157961 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2067741jaa; Sun, 10 Feb 2019 17:29:24 -0800 (PST) X-Google-Smtp-Source: AHgI3IbpjDQNjN6Ek/h2+Yo2e9oiFwtwGT82R7w9WPZ0rk3e7svuP4cmhw+I2p1WJmO1QEqsWJiE X-Received: by 2002:adf:9061:: with SMTP id h88mr24937709wrh.65.1549848564715; Sun, 10 Feb 2019 17:29:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848564; cv=none; d=google.com; s=arc-20160816; b=M1yx5hJayp1F+016obzBPgvhvE3gPxX2miOmWUUZt+V0ZAIQG+ZVFyCrJjA+6OGLsq ymjJYuZoZilKCKIGpy5JkD66r2I2CrjQw5sYpruWjnRSIg7/xlRFZ1+ZXhOtjdKc5a0k H9RXHULWAHFoddCiAhyT4Q6nDmWpzSs4fu6lORadI0pe5u99aL8CRdvwHQtoWuGRUa+B 3fj6RmbMCnJYob+Nbltze30MyozJ5V4AezdMMfJEkuvCmUdLk+sYngc8j/qYH3+nFb2s vfjq4IHQ8QW5SKO1iqMDqOnzl7PAft3stFY8RBVQQNBY8zDAUe/Y9kQ/nBB7M404Buws 3qQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=WSCoDwSU+P+38revDmJNxYHnEDDbY09xYDeZCaGFSLU=; b=dnrElCrjYpFuPz8Wpbi1iqSiCsPiWzRgElXOENICmUgCB3zv8Y6dGiD5Htry0aeoP/ mTWwdOf/krHiCmSFt0Ual9vebV6hcngyx2TsKfVaglNEUJDRp0jU4+BnJLMF0+p9nhK+ pYjyoI9mxLGUOO2JSA+UbtlTQ9b3F9U0DqxMlVMOnpfshoEAsXxMvy1RlYoTJTooYSNn YbdSKgP8YzFEeuulMQf2WBxjIO4hwmnc86kE/I+pkl0l/SITWNmSIAYOrqLGzQNx87ZG q6WzE/StFsYaMRESYIaAY4m4/bjOH5eLpXugfK7lfMufajZ7jeCSOinGLGernRjwviX5 I/Mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mgEUH07+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:15 -0800 Message-Id: <20190211010829.29869-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 12/26] target/arm: Implement the GMI instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 47577207b2..ef340cb6f9 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -107,3 +107,4 @@ DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 3eb5d622fc..fc9e172c95 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -234,3 +234,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag = allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3d71a9701f..2e0d797294 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5158,6 +5158,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Mon Feb 11 01:08:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157952 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2062773jaa; Sun, 10 Feb 2019 17:21:06 -0800 (PST) X-Google-Smtp-Source: AHgI3IbDAk1MXjwhJjKQyuwBgQfr8JC90N/T+kLpm1Gp27u96t+m7jRay0idk/VE5mMQAGB0MB1q X-Received: by 2002:a1c:f901:: with SMTP id x1mr7133380wmh.84.1549848066327; Sun, 10 Feb 2019 17:21:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848066; cv=none; d=google.com; s=arc-20160816; b=vfKij4zSqsrcr+sHKfQareFAueFYwbPkW1aSEYmshMdch0sVAKxnMlKjZir+YOJ6J6 7h9L+3CskRytVJPxZBnklv6Kslh4jdti611ptpdxSZ7Yiq2LyQhcI7bL4C6ruUdkP70+ fj4Z8cIZzvLSJevRFQYxEXJnQt+WZ/uoChoiKp5t81EMlSUmTilSDoZ34OlyXSxvzjcV BX7MD2kn3Onn/vORV4MNh/aLdeqBnp5hH5GWgZswXJDLwsJHjY2NRYJxFiI7Y+PqxNKM vLLLO7T2sqkWMvXa7UAU27oLVLSdE1MeHyTWkCyKmbz9UlKTz51yYAmYmKrPnB/XWzd6 2jkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PJAqbiDKYxYxOSUmg7S9N0tHoZ0pCVJBOmi1qgJP2Co=; b=lnbAfdYVE68dqrEyDAqKaGDWGbAIzII6xuzA+6aF0b3Fpjxtr+szfFIsa1T+uislTh aL0eUIgYVW+sYPiGBwJnwoO5Ie+IHCncNe0+jlU4R5+5f3OHg8L2tO07gHxNWnk1oMTn E+eKb8+9RaEiG0bTaFPiKxWQlTGQ1iV7/ijB9ZUmq/lTVZS+s+bOKPoOQ6zoa6nSRjtK 7yNsQ6olkqBGVCzMNuKPBewxpq64Z+xy2rOD4c9E0vElckt5wrnLraAMarny9wroMFzF zmzF40VjfTT0sSca8dzowAcN8e7lqHV2h5pOIPUOqC8H8X2nKF512g5DcrKEkJD84imS DE/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lofp4ue2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:16 -0800 Message-Id: <20190211010829.29869-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH v2 13/26] target/arm: Implement the SUBP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Fix extraction length. --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2e0d797294..3e46ee6f69 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5132,19 +5132,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf = extract32(insn, 31, 1); + setflag = extract32(insn, 29, 1); rm = extract32(insn, 16, 5); opcode = extract32(insn, 10, 6); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - if (extract32(insn, 29, 1)) { + if (setflag && opcode != 0) { unallocated_encoding(s); return; } switch (opcode) { + case 0: /* SUBP(S) */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n = read_cpu_reg_sp(s, rn, true); + tcg_m = read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); + tcg_d = cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; From patchwork Mon Feb 11 01:08:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157942 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2057312jaa; Sun, 10 Feb 2019 17:12:27 -0800 (PST) X-Google-Smtp-Source: AHgI3IYVQ3M/APLJxeSEbfpC/AVypaKZl2+kTy7nfjJuSCQe7mQvSJ5FxTFUrR0WrBSY+3GiYoPy X-Received: by 2002:a1c:2804:: with SMTP id o4mr7595410wmo.150.1549847547405; Sun, 10 Feb 2019 17:12:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847547; cv=none; d=google.com; s=arc-20160816; b=NNZQUaZoarpg8iAvHZce4X97a/nAZICTGM99hLWEeG+HHhRbqwNzc3XHgU9b7SxKvF KIhVquAiEqwij4Kt730spvG5qMOpxbvRQT23NEghqMq5kDUfttzqNSva+EIe4VGpeIz8 Zvc4QEeknhMPuIBtdCT5FKeFo91cPIxHCy3esyxFoIWED7PYbtH9z7gwiWo9NsmS0oow VwuiX/qD1bGPAyJ9/peQ0C4BVDzKVDM99HdrWg+bWehfpjikQL2GwA8udlzF1a+rjLcr 32Vpi/onq4VNDBNQyZGbDKNxex0Q9Laq4ndMBsezwOaqVr46ftcxQKto/34Vp7mNkahj ay0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AmqIDdbNf59JA1t3/NmXQ2mwEInbv+gIdpyKJXCMyoQ=; b=BJYHEz7V7Kfa4qN9bhF2tdYvpEkXD8E7caWo3m8l1ASZV4TXaJKvVRmbXDjF/127XY FC06MCJT9aAmADl+UJ5G/xx7/jGpxKmazqS5XzIvrW4J7piq6gAEHx8rho0ZVjF7iuSG ZH4RGwPyo3eI3EJ/ySFHL/IdzESFNd6TiQPZihuMWj6lgTcZYcrfo1aF3vvJCAKlzsHF S8YP3YvdMTiD55bk6LbISWK9ZLQHuAq6lCYCNtVc61eUB7XKSF93LtYRAw4P/L7CKUbo VlzibONad4ZYYiZLXVHs0xszs3O58BfuKB7ioMg1n38HvkEa4rlV8lKmOdd19gXjmSAC fxAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B1QiOMZn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:17 -0800 Message-Id: <20190211010829.29869-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 14/26] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will need this to raise unaligned exceptions from user mode. Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) -- 2.17.2 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..d3cf362e4b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -87,8 +87,6 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, return val; } -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -179,6 +177,22 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, raise_exception(env, exc, syn, target_el); } +/* Raise a data fault alignment exception for the specified virtual address */ +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + ARMMMUFaultInfo fi = {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.type = ARMFault_Alignment; + deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); +} + +#ifndef CONFIG_USER_ONLY /* try to fill the TLB and return an exception if error. If retaddr is * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) @@ -200,21 +214,6 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, } } -/* Raise a data fault alignment exception for the specified virtual address */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - ARMCPU *cpu = ARM_CPU(cs); - ARMMMUFaultInfo fi = {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.type = ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); -} - /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort * exception From patchwork Mon Feb 11 01:08:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157962 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2068801jaa; Sun, 10 Feb 2019 17:30:56 -0800 (PST) X-Google-Smtp-Source: AHgI3IYg3Q9fYjWdKcQuHFV8rL07u9cScPtNamPsvoMKKLmD2dmSpooIYg+EAYVz7/oCW5aRYVrF X-Received: by 2002:a1c:f909:: with SMTP id x9mr7108307wmh.108.1549848656338; Sun, 10 Feb 2019 17:30:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848656; cv=none; d=google.com; s=arc-20160816; b=Ns0V/FQ8q82L620b5z5Cm3gxBycYFH8OUQP7cAfBNq2fcTJrjsNC1SxNyWVrShmZnT TMA1Ts6vi0FQJtLqrTWZBv4BiJBhQLmMtvWVXPM8WP2k7k+cGo8STQNmAlWcgHEdhhEb xkdp+0ZVXh3LzP7jAHQ5n4Mk6fcWYsn2sxQhMx4Wf0mC3GuB4NEcj7SnsS+kNc1eSDDn Zc9Jz5Mal51ke0/O8lD+9K0mcSYL3xCywzwFj4XKu6U0cYgvlUVz5zwbi4sGodgN+Te8 bP39/Ce39taBjKJJgxF4ZZROzp1YlF1++I0yNtr6NmKyOT3BoNu1Xgh2uGLFmzM00luQ brLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=dC5MZGfEehm1QYmsC6MCd0iZ0BCsKh0q/AMqCYY4vLc=; b=tKb29vjcQ3H7cvXNeWIiNlT09dNDO3MWA6/y2XWdQzJ5aEfVuTv2RUW7f7QO4Efh+V FeYnNLucVYhVPjjYfSd7VZDBVB8/tfG2J75B8ULNR+JZ0bpv2bMfJ46Ejt9H4PMLkrLH w+0KpfuDX1lS1JkRy0fbw6+/4ALuiD8PxCXEfR04L2qrORKJtjbCiXM7Rj740DDaQrY9 jap+UFLFFvcf2pPk4cB7wRnpmwa6TH6LRhczoJIYMhvkb2Yedai8yEXlTFRrnGdyllh+ 7qqv55ALAKy9bArsthbBS5KTqJNi9GUvrIB5cnPOrRwogo3Puxpkxe4Mzws4y/0I54Jc GN3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vAH1BOLH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:18 -0800 Message-Id: <20190211010829.29869-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 15/26] target/arm: Implement LDG, STG, ST2G instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Split out allocation_tag_mem. Handle atomicity of stores. --- target/arm/helper-a64.h | 5 ++ target/arm/mte_helper.c | 152 ++++++++++++++++++++++++++++++++++++- target/arm/translate-a64.c | 114 ++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+), 3 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ef340cb6f9..a00364fb4c 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -108,3 +108,8 @@ DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(ldg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(stg_parallel, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(st2g_parallel, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index fc9e172c95..13befdbf86 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,8 +25,6 @@ #include "exec/helper-proto.h" -#if 0 -/* Don't break bisect. This will gain another user before we're done. */ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) { /* @@ -51,10 +49,22 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) return ptr; } } -#endif + +static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, + bool write, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return NULL; +} static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) { + uint8_t *mem = allocation_tag_mem(env, ptr, false, ra); + + if (mem) { + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + return extract32(atomic_read(mem), ofs, 4); + } /* Tag storage not implemented. */ return -1; } @@ -240,3 +250,139 @@ uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) int tag = allocation_tag_from_addr(ptr); return mask | (1ULL << tag); } + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag; + + /* Trap if accessing an invalid page. */ + rtag = get_allocation_tag(env, ptr, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + if (rtag < 0 || !allocation_tag_access_enabled(env, el, sctlr)) { + rtag = 0; + } + + return address_with_allocation_tag(ptr, rtag); +} + +static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + if (unlikely(ptr & MAKE_64BIT_MASK(0, LOG2_TAG_GRANULE))) { + arm_cpu_do_unaligned_access(ENV_GET_CPU(env), ptr, MMU_DATA_STORE, + cpu_mmu_index(env, false), ra); + g_assert_not_reached(); + } +} + +/* For use in a non-parallel context, store to the given nibble. */ +static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + uint8_t new = deposit32(old, ofs, 4, tag); + + atomic_set(mem, new); +} + +/* For use in a parallel context, atomically store to the given nibble. */ +static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + + while (1) { + uint8_t new = deposit32(old, ofs, 4, tag); + uint8_t cmp = atomic_cmpxchg(mem, old, new); + if (likely(cmp == old)) { + return; + } + old = cmp; + } +} + +static uint64_t do_stg(CPUARMState *env, uint64_t ptr, uintptr_t ra, + void (*store1)(uint64_t, uint8_t *, int)) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + uint8_t *mem; + + check_tag_aligned(env, ptr, ra); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* Store if page supports tags and access is enabled. */ + if (mem && allocation_tag_access_enabled(env, el, sctlr)) { + store1(ptr, mem, allocation_tag_from_addr(ptr)); + } + + /* Clean the pointer for use by stzg. */ + return strip_tbi(env, ptr); +} + +uint64_t HELPER(stg)(CPUARMState *env, uint64_t ptr) +{ + return do_stg(env, ptr, GETPC(), store_tag1); +} + +uint64_t HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr) +{ + return do_stg(env, ptr, GETPC(), store_tag1_parallel); +} + +static uint64_t do_st2g(CPUARMState *env, uint64_t ptr1, uintptr_t ra, + void (*store1)(uint64_t, uint8_t *, int)) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + uint64_t ptr2 = ptr1 + (1 << LOG2_TAG_GRANULE); + uint8_t *mem1, *mem2; + + check_tag_aligned(env, ptr1, ra); + + /* Trap if accessing an invalid page(s). */ + mem1 = mem2 = allocation_tag_mem(env, ptr1, true, ra); + if (unlikely((ptr1 ^ ptr2) & TARGET_PAGE_MASK)) { + /* The two stores are across two pages. */ + mem2 = allocation_tag_mem(env, ptr2, true, ra); + } + + /* Store if page supports tags and access is enabled. */ + if ((mem1 || mem2) && allocation_tag_access_enabled(env, el, sctlr)) { + int tag = allocation_tag_from_addr(ptr1); + + if (likely(mem1 == mem2)) { + /* The two stores are to the same byte. */ + tag |= tag << 4; + atomic_set(mem1, tag); + } else { + /* The two stores are across two bytes. */ + if (mem1) { + store1(ptr1, mem1, tag); + } + if (mem2) { + store1(ptr2, mem2, tag); + } + } + } + + /* Clean the pointer for use by stz2g. */ + return strip_tbi(env, ptr1); +} + +uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) +{ + return do_st2g(env, ptr, GETPC(), store_tag1); +} + +uint64_t HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr) +{ + return do_st2g(env, ptr, GETPC(), store_tag1_parallel); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3e46ee6f69..539c25a80b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3603,6 +3603,117 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } } +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 = extract32(insn, 10, 3); + int op1 = extract32(insn, 22, 2); + bool is_load = false, is_pair = false, is_zero = false; + int index = 0; + TCGv_i64 dirty_addr, clean_addr; + + if ((insn & 0xff200000) != 0xd9200000 + || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + switch (op1) { + case 0: /* STG */ + if (op2 != 0) { + /* STG */ + index = op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 != 0) { + /* STZG */ + is_zero = true; + index = op2 - 2; + } else { + /* LDG */ + is_load = true; + } + break; + case 2: + if (op2 != 0) { + /* ST2G */ + is_pair = true; + index = op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 != 0) { + /* STZ2G */ + is_pair = is_zero = true; + index = op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + dirty_addr = read_cpu_reg_sp(s, rn, true); + if (index <= 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + + clean_addr = tcg_temp_new_i64(); + if (is_load) { + gen_helper_ldg(cpu_reg(s, rt), cpu_env, dirty_addr); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(clean_addr, cpu_env, dirty_addr); + } else { + gen_helper_stg_parallel(clean_addr, cpu_env, dirty_addr); + } + } else { + if (is_pair) { + gen_helper_st2g(clean_addr, cpu_env, dirty_addr); + } else { + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } + } + + if (is_zero) { + TCGv_i64 tcg_zero = tcg_const_i64(0); + int mem_index = get_mem_index(s); + int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; + + for (i = 0; i < n; i += 8) { + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + tcg_temp_free_i64(tcg_zero); + } + tcg_temp_free_i64(clean_addr); + + if (index != 0) { + /* pre-index or post-index */ + if (index > 0) { + /* post-index */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3627,6 +3738,9 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* Load/store tag */ + disas_ldst_tag(s, insn); + break; default: unallocated_encoding(s); break; From patchwork Mon Feb 11 01:08:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157963 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2069634jaa; Sun, 10 Feb 2019 17:32:13 -0800 (PST) X-Google-Smtp-Source: AHgI3IY9gtHXvmEtJvo38dZHHjZNGdODA1/A8j+gA961qY7+xuq5AzKx00xW+JCZk40lj/jpN4qn X-Received: by 2002:a5d:4ac2:: with SMTP id y2mr3585993wrs.98.1549848733374; Sun, 10 Feb 2019 17:32:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848733; cv=none; d=google.com; s=arc-20160816; b=TRlnXOMMZbu971IWVAzsW4DKOKF6n+EBwWB9B0+ddvU3t+EaeLOFF/VylsZuZzKDvN oo24QE28rkChOZIqkgx95/Z20dm4TFoTh7R/9QyF5nlCbD/eEpKPdfJwYMXfZiFBa9cf UrBIiX0WWqlgG+vE+EhPE6eXexOn2dGlsdE/cW0upqxNFPqv5WY9n6F/nDghQGloOjxp iKYbBmwnYMMc16+NicjytLv6TBwFENvbd5VeRoM/YqnW2kJWH+S+yzS5LIWFnBDqMTKC /DqYzemeNWIcvalc/QLicfpnrLoM2VhNepUIPlUL9mHBcQdgWyIZHAKr+gpCwSzryqES XU0A== ARC-Message-Signature: i=1; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:19 -0800 Message-Id: <20190211010829.29869-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PATCH v2 16/26] target/arm: Implement the STGP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 539c25a80b..9bd68d522c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2701,7 +2701,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2726,6 +2726,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) bool is_signed = false; bool postindex = false; bool wback = false; + bool set_tag = false; TCGv_i64 clean_addr, dirty_addr; @@ -2738,6 +2739,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (is_vector) { size = 2 + opc; + } else if (opc == 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { + unallocated_encoding(s); + return; + } + size = 3; + set_tag = true; } else { size = 2 + extract32(opc, 1, 1); is_signed = extract32(opc, 0, 1); @@ -2788,7 +2797,12 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); + if (set_tag) { + clean_addr = new_tmp_a64(s); + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } else { + clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); + } if (is_vector) { if (is_load) { From patchwork Mon Feb 11 01:08:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157957 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2064652jaa; Sun, 10 Feb 2019 17:24:15 -0800 (PST) X-Google-Smtp-Source: AHgI3IYxzBBuaCM2k8SVZzLEGdRqsjPPPFIVSNVB4qrGughVm4wIXcm39w7uNBu4aNSvry/VD616 X-Received: by 2002:a5d:67cd:: with SMTP id n13mr10365627wrw.316.1549848255265; Sun, 10 Feb 2019 17:24:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848255; cv=none; d=google.com; s=arc-20160816; b=k/KEC42yavnCKrOy+TUAYJiuB0Uc70LGEBFmZ9gLpinXGAwa6TIHoH7l/CQnz39Pmr Ri9i9T6bYqyPduTB8QYBLDEWL1OF1woAmssTjSeuMLlO2ueju0xPUm3oOSG7zOrywH2j z61XLI4tXXG9hLMQY+wOIk4rKa31lP2qrd8BqpW0eyGYmSh1ERJ2kolf1/Uu0MKv8suv a8siMWyVOsIMGQmC0tvwNiwKabd6IVUBDeSj2bpcQSGH+2qHSS4AlwVap/W1yBr/u0Cj 2dboz0ZXNftKhPs53lBKYqHCBr21GChe+XrlZTfgMhdvYDYwtLDIvYksoKz/Zr9CEAkq XFfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7HsOcQyaMevodOsm6h2V5NoXxK7MjvAqlm4dwXNbUE0=; b=JuTc9SOgOGakLV01m/XFnWi94S4uKgfAk9PwY7IMwxaMo6Wu4LiCbi/vg+6RE9jIVR IG0aE9+GLy8V415koxK6Q02j8RzGNChL8qFBPvF+PyoxaRU5HHrqHVJ0vNX25/8EFFM6 rW7vb0lc1Reb6MuFsD08Dl6lDeRBlIN2hJlF2x4oVRcDAjoM7qarkHEmvWR7ZfkKh2rM p47hBvGlg+grgTWFPst7G/noo1RsBr0FWWoKWGAd4/6zJ16/PhFgKngH8vNE3x9rNLOW k/bEVlsdiF4qDvCEiDuxngIuhYjUH5q8E1jphZuJb44/pqgoX9VxfSHdZlRToyPprKOT wBmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hazg7KQh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:20 -0800 Message-Id: <20190211010829.29869-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 17/26] target/arm: Implement the access tag cache flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Like the regular data cache flushes, these are nops within qemu. Signed-off-by: Richard Henderson --- target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d9c070bb3..74bace81e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5772,6 +5772,54 @@ static const ARMCPRegInfo mte_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, .type = ARM_CP_NO_RAW, .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, + { .name = "IGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, REGINFO_SENTINEL }; #endif From patchwork Mon Feb 11 01:08:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157964 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2069849jaa; Sun, 10 Feb 2019 17:32:34 -0800 (PST) X-Google-Smtp-Source: AHgI3IboJ1IPvS0TwtNaWiDqY64cW5/gwQExFhXdjOljSGJYnzBc1fJEOqqpa4aPTx/+qZMhXrSY X-Received: by 2002:adf:f848:: with SMTP id d8mr27066081wrq.178.1549848754383; Sun, 10 Feb 2019 17:32:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848754; cv=none; d=google.com; s=arc-20160816; b=T3GU8u5NAWzYr5mgCeTmA3N1jg9N4s5xkLZ+CdmKYOqqpm5e1sUSqrZdXEpPJJrvoc 6vt5FRKRuDWrdLi/AV/+Ers4Tx9h2iMNIX3ovv2PL36Fd+cCRyqyEPMEiZOmRu1wdlnl aBRQq+49RKIFpkb4vk4zSscd5/+7XZhyMwOD+q9gzUtou6fY3An/pnQiGZhQTiwWOFJT Kme0gBFBvUwInmjLLpA5R0hAuyGrf/+DjhjtblRlUk6BrUQ0s+MaDnwzRtVY/17GNg1e 9jts8D8A9ORnxmA6Le9lpV+J8J/p+JXHAiOghcIRkUF5m/2qXvX7rC8qwPXYBlpD9OL0 SeMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=1ThSYlTjjjdful+PEa+IzVjavr7hehgRai0NxwGpzTA=; b=K3R7rXQlYmcm6JuvkcNeQ2u/ZQPobtJN5sw2a+DYUfzuYA2DEOIdERyofS6z/SXvpV QHkPW/Y3CehKw6e+d9vjf2qpURhJ6+wM+nODSINFq1SIgbfUjIyTZ2VxCn8PzL3Z5bOO mif4cFqEhtHawrx4/Pucf6K7Bm4sq4PEZam+UjiwjQXXtvW57UoXx8AnsD8WTGpeFy2x 4SYNQSKvrBN+t2QYa5WQEURMusEM16dpF5FuAl3wnfCp+m7zSJ3+2JWW8eNtp3GKarFc 6Gw0IUCHqOKp5hEL5HhcfaibjWYNln95uFbESgjtmzJZDVmRfCZurbwwK0PCEuw7b1nB z70w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lb8pLBzY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:21 -0800 Message-Id: <20190211010829.29869-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 18/26] target/arm: Implement data cache set allocation tags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is DC GVA and DC GZVA. Signed-off-by: Richard Henderson --- v2: Use allocation_tag_mem + memset. --- target/arm/cpu.h | 4 +++- target/arm/helper-a64.h | 1 + target/arm/helper.c | 16 ++++++++++++++++ target/arm/mte_helper.c | 26 ++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++++ 5 files changed, 55 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 74633a7a78..ca32939483 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2160,7 +2160,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a00364fb4c..4ad900d36e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -113,3 +113,4 @@ DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(stg_parallel, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g_parallel, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(dc_gva, TCG_CALL_NO_RWG, void, env, i64) diff --git a/target/arm/helper.c b/target/arm/helper.c index 74bace81e4..9fac3628e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5820,6 +5820,22 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "GVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, + .access = PL0_W, .type = ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, + { .name = "GZVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, + .access = PL0_W, .type = ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 13befdbf86..93f7cccee2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -386,3 +386,29 @@ uint64_t HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr) { return do_st2g(env, ptr, GETPC(), store_tag1_parallel); } + +void HELPER(dc_gva)(CPUARMState *env, uint64_t ptr) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + size_t blocklen = 4 << cpu->dcz_blocksize; + uint8_t *mem; + int rtag; + + ptr = QEMU_ALIGN_DOWN(ptr, blocklen); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, GETPC()); + + /* No action if page does not support tags, or if access is disabled. */ + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag = allocation_tag_from_addr(ptr); + rtag |= rtag << 4; + + assert(blocklen % (2 << LOG2_TAG_GRANULE) == 0); + memset(mem, rtag, blocklen / (2 << LOG2_TAG_GRANULE)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bd68d522c..a3bd2e27ef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1811,6 +1811,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_rt = cpu_reg(s, rt); gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + tcg_rt = cpu_reg(s, rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; + case ARM_CP_DC_GZVA: + tcg_rt = cpu_reg(s, rt); + gen_helper_dc_zva(cpu_env, tcg_rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; default: break; } From patchwork Mon Feb 11 01:08:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157959 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2066082jaa; Sun, 10 Feb 2019 17:26:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IZztA281+zrYxFTjCqRebGK/Vc2EFBR09viagbXp0asASsoVWCJTT3PPBISiPz6Dw8MYx5Z X-Received: by 2002:adf:fbc8:: with SMTP id d8mr24679107wrs.318.1549848400644; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:22 -0800 Message-Id: <20190211010829.29869-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PATCH v2 19/26] target/arm: Set PSTATE.TCO on exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0085 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Only set if MTE feature present. --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 9fac3628e5..a3ad5bc54e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9455,6 +9455,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int cur_el = arm_current_el(env); + unsigned int new_pstate; /* * Note that new_el can never be 0. If cur_el is 0, then @@ -9548,7 +9549,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); - pstate_write(env, PSTATE_DAIF | new_mode); + new_pstate = new_mode | PSTATE_DAIF; + if (cpu_isar_feature(aa64_mte, cpu)) { + new_pstate |= PSTATE_TCO; + } + pstate_write(env, new_pstate); env->aarch64 = 1; aarch64_restore_sp(env, new_el); From patchwork Mon Feb 11 01:08:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157955 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2064594jaa; Sun, 10 Feb 2019 17:24:08 -0800 (PST) X-Google-Smtp-Source: AHgI3IaGJRIV/p7IBEpkxcmqJgqsrzfiGIWtswENyttIStX+rPL3penheKf/sg9XU8SHmwqD1N3i X-Received: by 2002:a7b:c399:: with SMTP id s25mr7579708wmj.90.1549848248628; Sun, 10 Feb 2019 17:24:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848248; cv=none; d=google.com; s=arc-20160816; b=IecrM/XAhKrQLgpwK3g/CwFM+4Geb7RkNA9aA6GUJuZTGK9kplyIOsw7SxRF4T2/KK Hqd93zyzX7ybUoZuX+rfOFxRpwlahP7o9wRZakNX+u6YBIqyvYzp3T9BV/TH8WZcCxEa Wa1L0D6t3PGbEfRsKLdkk6jL/To9Dgzmn/95Pj9ngdt/KEbGg7tmWBXxjvQvbX1a+IGT InfGZB5yYiadLPHA+kBip90Rp1hln0l8iLNRy5+4ZXtZOr68ur80DwxDVa4FuI9mOWeC +M92j1OWduEmX8ezAj+uVnRIyaNYddpv6ntPOFutKFWFWORqbDwABWwNb8eOcq3kkVL/ OEXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IYfDmawl379GZgWCUsgON1GHK8BY9wa/LpINsjn/HBc=; b=ilsuOkWChXJ1ckGwe0t73KIPvDeNG7i6HtaqCewSZPyY1FrLbpqn4sVOx6+hBAtC8h vcQEAqPuau5tLRsUYffomu2PmqoZqXXkdd0rCxMtlmZq/j56rsx6RXYjSoJiZhQnF4h3 A8W9IAwbkOwnw03kB1JU3UN1PXK/C2ISZo+tyoqE9Iw2AEG+aBKs2wK7aVvAiITramGi 1bYuoc1gYooCS1IZw2y1qbb1WfyMXq8C246LZhFWX6XD3FqHBFM/F5v6qdzPEVOhKn6L wRqffeGiZr2ZDwevTZia3f7L901DvEkZdiFN4LVi8FHWOdqs7S/ncwf+w8EIQwNzQStt jInw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X+1o0xIl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:23 -0800 Message-Id: <20190211010829.29869-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 20/26] tcg: Introduce target-specific page data for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, remember MAP_SHARED as PAGE_SHARED. When mapping new pages, make sure that old target-specific page data is removed. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 10 ++++++++-- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++++ linux-user/mmap.c | 10 ++++++++-- linux-user/syscall.c | 4 ++-- 4 files changed, 46 insertions(+), 6 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b16c9ec513..e88ecad0b3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -244,10 +244,14 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_ORG 0x0010 /* Invalidate the TLB entry immediately, helpful for s390x * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ -#define PAGE_WRITE_INV 0x0040 +#define PAGE_WRITE_INV 0x0020 +/* Page is mapped shared. */ +#define PAGE_SHARED 0x0040 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif #if defined(CONFIG_USER_ONLY) @@ -260,6 +264,8 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); +void *page_get_target_data(target_ulong address); +void *page_alloc_target_data(target_ulong address, size_t size); #endif CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8f593b926f..6cc266428d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -107,6 +107,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2476,6 +2477,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2492,6 +2494,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) if (flags & PAGE_WRITE) { flags |= PAGE_WRITE_ORG; } + reset_target_data = !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &= ~PAGE_RESET; for (addr = start, len = end - start; len != 0; @@ -2505,10 +2509,34 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data = NULL; + } p->flags = flags; } } +void *page_get_target_data(target_ulong address) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + void *ret = NULL; + + if (p) { + ret = p->target_data; + if (!ret && (p->flags & PAGE_VALID)) { + p->target_data = ret = g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index e0249efe4f..0b786b87a2 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -562,7 +562,11 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, } } the_end1: - page_set_flags(start, start + len, prot | PAGE_VALID); + if ((flags & MAP_TYPE) == MAP_SHARED) { + prot |= PAGE_SHARED; + } + prot |= PAGE_RESET | PAGE_VALID; + page_set_flags(start, start + len, prot); the_end: #ifdef DEBUG_MMAP printf("ret=0x" TARGET_ABI_FMT_lx "\n", start); @@ -754,9 +758,11 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = -1; } else { new_addr = h2g(host_addr); + /* FIXME: Move page flags (and target_data?) for each page. */ prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5bbb72f3d5..9d89b40321 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3884,8 +3884,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_env, raddr=h2g((unsigned long)host_raddr); page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_SHARED | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); for (i = 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { From patchwork Mon Feb 11 01:08:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157954 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2063696jaa; Sun, 10 Feb 2019 17:22:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IY/zdrhJPO+W1m5+FnFp39y1JQT8aZnDCYykQc9Z69I2tVZIKVYHArlpg+b9CEjmEejRzLb X-Received: by 2002:a7b:ce8e:: with SMTP id q14mr7724352wmj.10.1549848160270; Sun, 10 Feb 2019 17:22:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848160; cv=none; d=google.com; s=arc-20160816; b=fCTAS+n9bYM+mOHlY+dYhrL0y4BjhU7vFaHli7Iqri9EB6kCyvriRnPRa/jLib8o5U 0igZl92BzoeOW3IkIa/uU4RRAkYyq8yCsqcZ/KDcgIzjJlshmzlmFp6pRcsYnDggGpMZ 9i8aUufSL63JHuZBSmzOylCTw6VhkTYKx2LKcLmuqpp2nTt5fI3y7TckqTTEvRooBTVr 10DtnPHSLMT4Sd1jn+F6RbISJEXHPbRHRCwDBawJwvGPXxu8gbCqRdKMeZjqLojX7551 0ZIDcEkFfZZlzcS6KEFP3So5EOdUY65dK/T5TD6Gr04tlO0lNwhms+gDk51F6vSMqvGM qvsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=0B3omcAJPniMrgzOgR3FjeAcoYmr0yasFqZ8a7CEW3A=; b=NdyGJPnF4XdinfVl+/vuukujbW6AIP6v03OM9kwAGFr1w0a0Wl+5seAoW2YxWik9PE uuJ19b3NKiMm/zu118nS36YOrYb1Jg9EMixkoUKI/kXilKp6C5h1DlPkdQLVxdj9mkPD smTusxZDejF5KU0d585t7e/8HOuip8erlYYXVWOAFT8sj+AQ01b0UbEay+M5JkSt8snx VAocdz1Z1ZE03lUYLhavFH4sJTe30b2EY6kmXAt0DXNxsC/ErWqdQHuSdO12RrMZ+QB7 Uu06ARb6EXPN9cOcPGiOv6l4M/Zj/HbaPIOMdKIBCucwD0hE0jSWTZghPc5HbiA+ChI7 Zdhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UyE5VRud; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:24 -0800 Message-Id: <20190211010829.29869-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 21/26] target/arm: Cache the Tagged bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index a3ad5bc54e..3d7a51f8a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10719,6 +10719,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; + uint8_t memattr; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10949,17 +10950,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, txattrs->target_tlb_bit0 = true; } + if (mmu_idx == ARMMMUIdx_S2NS) { + memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint64_t mair = env->cp15.mair_el[el]; + memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8); + } + + /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */ + if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) { + txattrs->target_tlb_bit1 = true; + } + if (cacheattrs != NULL) { - if (mmu_idx == ARMMMUIdx_S2NS) { - cacheattrs->attrs = convert_stage2_attrs(env, - extract32(attrs, 0, 4)); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 0, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); - } + cacheattrs->attrs = memattr; cacheattrs->shareability = extract32(attrs, 6, 2); } From patchwork Mon Feb 11 01:08:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157960 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2067305jaa; Sun, 10 Feb 2019 17:28:41 -0800 (PST) X-Google-Smtp-Source: AHgI3IbTQNQTE4JLGMrBfKsijkAmogoI2sUteE21DA7L9tV/brnfk7F3wAlV7QdFCIJc9w1yvq+/ X-Received: by 2002:a1c:a98b:: with SMTP id s133mr2675119wme.129.1549848521438; Sun, 10 Feb 2019 17:28:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848521; cv=none; d=google.com; s=arc-20160816; b=N8hjkrM+c60TDVjs3wiSbCmImiddl/x3Ckoepw4PypzYJpaVWtK7y8bTrtSHNlG7I9 UOdwRyE4OF300VypPWxEcJlDrlfsZ4J2TgvngEj+zSZD0lx6XbISRtTwR8RYVe+ccntz q6FZXaMQDlVuS0vT7TQSnf66rydroRi4TSD3nzGm40yz1FNd49ylGa799XtWyew3njQh aXUFKtcuvy40yrMxXttlTE/kQB6gx7lNwm272JQp83+cuHfb3xOqEPg4RHMLmYqfywcy MzXXf1xENGpkqn9hudnpyMIrxXEdtA3RaWm3TLC7nW4CpRBNPz7qPTxJ8X2iysjRQici F/fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=A8TAMIXN+69/Jk9cvH3CNk1W0843jdUBpea8zUdjfM0=; b=BvdQ3y9N5cBilfImjUXzV46OoYqnJUmcZeSIq+8NqcUw4Kd7aMZYyFG7y2Cw1wGVsU F0WdigHQsTF6RtoL9P0zWpncX+zYFf7IFpt46fV/wUM6ES6tUo0C/1GC7KRVRqBGP4Yy EKqFbRstAjn6q0OV7ZBD09TFXzEj/vxN++PcFxt2LYV6nkTqWL517hMwxN4icfLURmPO A/EyYGRgPmJhyOqX7ynrvepBrEecDeViRR7obBFwgMc50G0gfdsq5VfpzRtpRxST23Nt AyIygZ44IM/hk3NIweRGaVgvuasloP5WoLXbkZywQFxTdByF32mQH+RpoKI2JFXmSJ9T zGlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="HNZ4pg/P"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:25 -0800 Message-Id: <20190211010829.29869-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH v2 22/26] target/arm: Create tagged ram when MTE is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ target/arm/cpu.c | 21 ++++++++++++++++++--- 3 files changed, 55 insertions(+), 3 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca32939483..2626af4a9c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -768,6 +768,9 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; @@ -2850,6 +2853,7 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch); typedef enum ARMASIdx { ARMASIdx_NS = 0, ARMASIdx_S = 1, + ARMASIdx_TAG = 2, } ARMASIdx; /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d..dccd1345a1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1260,6 +1260,21 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } +static void create_tag_ram(VirtMachineState *vms, MachineState *machine, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *tagram = g_new(MemoryRegion, 1); + hwaddr base = vms->memmap[VIRT_MEM].base / 32; + hwaddr size = machine->ram_size / 32; + + memory_region_init_ram(tagram, NULL, "mach-virt.tag", size, &error_fatal); + memory_region_add_subregion(tag_sysmem, base, tagram); + + /* ??? Do we really need an fdt entry, or is MemTag enabled sufficient. */ + /* ??? We appear to need secure tag mem to go with secure mem. */ + /* ??? Does that imply we need a fourth address space? */ +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board = container_of(binfo, VirtMachineState, @@ -1362,6 +1377,7 @@ static void machvirt_init(MachineState *machine) qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *secure_sysmem = NULL; + MemoryRegion *tag_sysmem = NULL; int n, virt_max_cpus; MemoryRegion *ram = g_new(MemoryRegion, 1); bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); @@ -1518,6 +1534,20 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } + /* + * The cpu adds the property iff MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem = g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + } + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + } + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } @@ -1540,6 +1570,9 @@ static void machvirt_init(MachineState *machine) create_secure_ram(vms, secure_sysmem); create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } + if (tag_sysmem) { + create_tag_ram(vms, machine, tag_sysmem); + } vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..decf95de3e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -851,6 +851,18 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); + } +#endif } static void arm_cpu_finalizefn(Object *obj) @@ -1164,16 +1176,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) init_cpreg_list(cpu); #ifndef CONFIG_USER_ONLY + cs->num_ases = 1; if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { cs->num_ases = 2; - if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases = 1; + } + if (cpu->tag_memory != NULL) { + cs->num_ases = 3; + cpu_address_space_init(cs, ARMASIdx_TAG, "cpu-tag-memory", + cpu->tag_memory); } cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); From patchwork Mon Feb 11 01:08:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157965 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2070265jaa; Sun, 10 Feb 2019 17:33:18 -0800 (PST) X-Google-Smtp-Source: AHgI3IYs0yp0uCZ9WyhmX3CZqcxxkESJ5UFKGJ7eVSYEWD+Z3QB8Wcj0rEyJCB9UgqHsS0buVvjx X-Received: by 2002:adf:f8cf:: with SMTP id f15mr25086955wrq.265.1549848797957; Sun, 10 Feb 2019 17:33:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848797; cv=none; d=google.com; s=arc-20160816; b=woaxxcoC/YmMNPUPRsGJEVJOnsZPtTV0EpWI1oo9+WtBa2FSdPjs4sBIvbyvDQDfsd McyNayQfTMRktPJZftBmFcOU10jga8hthxqWtsl8Afd1RZfOIHJlaQHHXA1elKDzr3PY nSJj/2G2LdhneGLQRRxLuB719wZFs73B3DzL1oiW+ScOs0kZGuB2/pFfvR/SJLsw88wd F/JpYi6nwcKcjKnmYObITTjNHJ/kvfRM/dgjynohfzuRUZKyPKto/8iVXacNRDKbC2H+ K/RyLsuR6+0KA1wrvNnmx3fCFZUJpAV8YpWCejSDJTVb51QnFfDRkHIkfLmLit2+jBSd UtVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ymaxv9zbXnQNBLMQJfCDWxjmtO7rlV16zaXGdm7o62o=; b=bzerg8rS0io1tlUCIp5tvfCMNexNq0zoKW0fXvj3GNsUV0DdvfibYubU0Aiu5C2sB3 FE5UIILSflQQbRqnWRjpB4peMYRpjGmbU2K2jYqzX3d2m6AiOE+2wnWXxBFuQWtxNnKi GRVHSRNfi81ZIX4UGevsbRJBjr0hLgJX+2ti0+Kdcl7/Vcfnf/Oc1LlX8ZJdgm4jJvZ8 C5CijUHz9XnFJL0nlz3p5sAAz2NHk49a8hUT6Q67msogu8JaxwAqmeOhXGo6JQyCcIvD Uc5mZG279CVqEMgeULMEahrypbeUZZ445gDaHfrlFOajZCSIWxVITESuJK5pXxrU0kMg JPRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kNaBYver; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:26 -0800 Message-Id: <20190211010829.29869-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 23/26] target/arm: Add allocation tag storage for user mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Control this with x-tagged-pages, which is off by default. The limitation to non-shared pages is not part of a future kernel API, but a limitation of linux-user not being able to map virtual pages back to physical pages. Signed-off-by: Richard Henderson --- v2: Add the x-tagged-pages cpu property --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 18 ++++++++++++++++++ target/arm/mte_helper.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2626af4a9c..ec5ddfbacc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -910,6 +910,7 @@ struct ARMCPU { #ifdef CONFIG_USER_ONLY bool guarded_pages; + bool tagged_pages; #endif QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c5675fe7d1..53a7d92c95 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -293,6 +293,18 @@ static void aarch64_cpu_set_guarded_pages(Object *obj, bool val, Error **errp) ARMCPU *cpu = ARM_CPU(obj); cpu->guarded_pages = val; } + +static bool aarch64_cpu_get_tagged_pages(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu->tagged_pages; +} + +static void aarch64_cpu_set_tagged_pages(Object *obj, bool val, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + cpu->tagged_pages = val; +} #endif /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); @@ -380,6 +392,12 @@ static void aarch64_max_initfn(Object *obj) aarch64_cpu_set_guarded_pages, NULL); object_property_set_description(obj, "x-guarded-pages", "Set on/off GuardPage bit for all pages", NULL); + + object_property_add_bool(obj, "x-tagged-pages", + aarch64_cpu_get_tagged_pages, + aarch64_cpu_set_tagged_pages, NULL); + object_property_set_description(obj, "x-tagged-pages", + "Set on/off MemAttr Tagged for all pages", NULL); #endif cpu->sve_max_vq = ARM_MAX_VQ; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 93f7cccee2..ad2902472d 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -53,8 +53,45 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + ARMCPU *cpu = arm_env_get_cpu(env); + uint64_t clean_ptr = strip_tbi(env, ptr); + uint8_t *tags; + uintptr_t index; + int flags; + + flags = page_get_flags(clean_ptr); + + if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ))) { + /* SIGSEGV */ + env->exception.vaddress = ptr; + cpu_restore_state(CPU(cpu), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + + if (!cpu->tagged_pages) { + /* Tag storage is disabled. */ + return NULL; + } + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return NULL; + } + + tags = page_get_target_data(clean_ptr); + if (tags == NULL) { + size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(clean_ptr, alloc_size); + assert(tags != NULL); + } + + index = extract32(clean_ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; +#else /* Tag storage not implemented. */ return NULL; +#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) From patchwork Mon Feb 11 01:08:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157947 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2059696jaa; Sun, 10 Feb 2019 17:16:08 -0800 (PST) X-Google-Smtp-Source: AHgI3IaO85+jp/8xM1dABZxka/ZGTQyNpoZmRKC/5v/o219r2wXCY0DVCWvMuJW781fMjXBi9y12 X-Received: by 2002:a1c:342:: with SMTP id 63mr6916609wmd.34.1549847768277; Sun, 10 Feb 2019 17:16:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847768; cv=none; d=google.com; s=arc-20160816; b=r+egUuk9BJefDJhw6abPSLgnN3QFT6+AEZb8QA4aFrw7AuB7jJ78h1DEzedDg+91P5 f8mBQ3VBzEQUEeUjw2ATdka/WuAHINmDj+4m/7h8Mh0wzxAofO9ArvRwRp0ZDL+92pa7 v/rzh2gur4G1XkQNgZAAdwQTMWHN9FORLG1bRiCDamcUGeJdz/GS7S4r9qTH1UCeD2B9 ShMqGe3gYcQfY8qZY728gNpR5CtEoQxc7LI7Umkd/yBihR1p4w4SLoWttOzFFTWPFnq8 fNbXNrV2WXzZ6rzrtHJurCC4hQeOTztLqAn44zuPlYv7KyAysPE69XTHmNwr2Df7WCBz wa7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=MvaIKsOMPQ7hbRMjemvvtwhP7sBFQA2Gv3Y/7+kAWX0=; b=eQl7K7F3tXE8TtIgu/V7GceaNavOIIeSyRoFod+fz9HMNset/5ZJYEkUTu4qFEh8z1 uQvEpaLC9smh2mv2unYP3s1YAE/vaYuP/p+uTHbomGBLIBSR6V16k9Kt+jgXqcZ+y0mP BfocfBUAoIUJ+b360at/ArYXhBdLN2+MrlSF4NukdlE0qcHIqn2O/TTks7sKNLk3W5YI gu3kILNof+WFCkbS3V078zWLdbRtAmmfVLZLH0hMe2p1dm2HjErOVvJHKnv0pY5H6y6O 1xx5eTAU5HO1mJVxayk4l+GRvn2gV2FlPG422AAOdEVV7z5Avsvo0H6m1Pdu5+65sZ7c 0ahQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OeNmJRWY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:27 -0800 Message-Id: <20190211010829.29869-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 24/26] target/arm: Add allocation tag storage for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 96 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 87 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index ad2902472d..3abed62018 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -53,19 +53,19 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { -#ifdef CONFIG_USER_ONLY ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); uint64_t clean_ptr = strip_tbi(env, ptr); uint8_t *tags; uintptr_t index; - int flags; - flags = page_get_flags(clean_ptr); +#ifdef CONFIG_USER_ONLY + int flags = page_get_flags(clean_ptr); if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ))) { /* SIGSEGV */ env->exception.vaddress = ptr; - cpu_restore_state(CPU(cpu), ra, true); + cpu_restore_state(cs, ra, true); raise_exception(env, EXCP_DATA_ABORT, 0, 1); } @@ -82,16 +82,94 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, if (tags == NULL) { size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); tags = page_alloc_target_data(clean_ptr, alloc_size); - assert(tags != NULL); + } +#else + int mmu_idx; + AddressSpace *as; + CPUTLBEntry *te; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + MemoryRegion *mr; + FlatView *fv; + hwaddr physaddr, tag_physaddr, tag_len, xlat; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + */ + mmu_idx = cpu_mmu_index(env, false); + index = tlb_index(env, mmu_idx, clean_ptr); + te = tlb_entry(env, mmu_idx, clean_ptr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, clean_ptr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, ptr, 16, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + index = tlb_index(env, mmu_idx, clean_ptr); + te = tlb_entry(env, mmu_idx, clean_ptr); } + /* If the virtual page MemAttr != Tagged, nothing to do. */ + iotlbentry = &env->iotlb[mmu_idx][index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* If the board did not allocate tag memory, nothing to do. */ + as = cpu_get_address_space(cs, ARMASIdx_TAG); + if (!as) { + return NULL; + } + + /* Find the physical address for the virtual access. */ + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + clean_ptr + + section->offset_within_address_space + - section->offset_within_region); + + /* Convert to the physical address in tag space. */ + tag_physaddr = physaddr >> (LOG2_TAG_GRANULE + 1); + tag_len = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + + /* + * Find the tag physical address within the tag address space. + * + * ??? Create a new mmu_idx to cache the rest of this. + * + * ??? If we were assured of exactly one block of normal ram, + * and thus exactly one block of tag ram, then we could validate + * section->mr as ram, use the section offset vs cpu->tag_memory, + * and finish with memory_region_get_ram_ptr. + */ + rcu_read_lock(); + fv = address_space_to_flatview(as); + mr = flatview_translate(fv, tag_physaddr, &xlat, &tag_len, + write, MEMTXATTRS_UNSPECIFIED); + if (!memory_access_is_direct(mr, write)) { + /* + * This would seem to imply that the guest has marked a + * virtual page as Tagged when the physical page is not RAM. + * Should this raise some sort of bus error? + */ + rcu_read_unlock(); + qemu_log_mask(LOG_GUEST_ERROR, "Tagged virtual page 0x%" PRIx64 + " maps to physical page 0x%" PRIx64 " without RAM\n", + clean_ptr, physaddr); + return NULL; + } + rcu_read_unlock(); + + /* The board should have created tag ram sized correctly. */ + assert(tag_len == TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)); + + /* FIXME: Mark the tag page dirty for migration. */ + + tags = qemu_map_ram_ptr(mr->ram_block, xlat); +#endif + + assert(tags != NULL); index = extract32(clean_ptr, LOG2_TAG_GRANULE + 1, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); return tags + index; -#else - /* Tag storage not implemented. */ - return NULL; -#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) From patchwork Mon Feb 11 01:08:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157951 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2062342jaa; Sun, 10 Feb 2019 17:20:20 -0800 (PST) X-Google-Smtp-Source: AHgI3IbG/mnesWLojORN6CrWMTJNLInRzJMSCuLKUYcMCCgH22l166wTv0yv1w0Qg4GKCsA6U+YD X-Received: by 2002:a5d:614c:: with SMTP id y12mr23695198wrt.106.1549848020562; Sun, 10 Feb 2019 17:20:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549848020; cv=none; d=google.com; s=arc-20160816; b=t0GURjKAKmZ0WSjgmedXQoVYyipUT5in4Ao+1FPJfiiVbKqTztp2XGaYoqLyJla9fY 44wGee/TmE5mOo3bCtmw3tTPmiMoC7xd4dNcoiOUhC2Ff+UTTB/KcNC5A8XWh7SmdsJ4 mNJ/m+vSqJ63sb3jDMiA5p9PzaaAGoAUtMAepBk+2KsUG4SJSq7nRNnn5INpGcyP1C8h 41qeTs4HAJU2MvI3Ia0BKuJRjCfMSE7EPJeTL1+apY5u4z5a+OPQFlPhFYyBvl5nAjIt GbcHkPGGE+ZF4PqozxeZfWvGWccgRhxVclni0R64s6Kp3RP/5ZXF0S1Qlh+n/1KtDkCs P8VA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=g7oNh1d8VWGEQw+YCuZLsLZ9OlLSdLVyb8nPu7OZ0AM=; b=upLwpwxiFbc7jlRaiYd9Z1AgieVXu/GwD0EwxPZC3inkFcsbniAuRDV3fDQfzPl+OF WC18Vqj2dAGCYhvd6imGRBDxMa5PsZEXU8iVd5kkTMW7hM14fwJPqv8p+ZSC10JOt3n7 1Cd428CUBT2JLSUq/MaDe7Q07L5NWTDFQ+0AffZfNZBPghjQuvpqIl9GRrN5r9H0O9K3 X23zzdLImZmM1ZwvmjJhnrdL3W3KQoZeKHz0zMa91SV2d2SoFNSVKhNdKkHMxDyVri/E +0xDLYnvsOlc6Wrctsl8+jL/xrGwIDItKTyoz+p1XH7xoIPBiL56AZH4AZtmNDY9E7hp tO/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Mou86ucX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:28 -0800 Message-Id: <20190211010829.29869-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 25/26] target/arm: Enable MTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 10 ++++++++++ target/arm/cpu64.c | 1 + 2 files changed, 11 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index decf95de3e..a5599ae19f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -206,6 +206,16 @@ static void arm_cpu_reset(CPUState *s) * make no difference to the user-level emulation. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); + /* Enable MTE allocation tags. */ + env->cp15.hcr_el2 |= HCR_ATA; + env->cp15.scr_el3 |= SCR_ATA; + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* Enable synchronous tag check failures. */ + env->cp15.sctlr_el[1] |= 1ull << 38; +#ifdef TARGET_AARCH64 + /* Set MTE seed to non-zero value, otherwise RandomTag fails. */ + env->cp15.rgsr_el1 = 0x123400; +#endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 53a7d92c95..7bd761b8f5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -352,6 +352,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr1; From patchwork Mon Feb 11 01:08:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157946 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2059396jaa; Sun, 10 Feb 2019 17:15:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IZz6dqByGyLoRDB54p5LSwO28WhYb+LByIenO9vVm4gLYTBzqUOd7vXlSos6tjdx+D68TY7 X-Received: by 2002:adf:bc87:: with SMTP id g7mr24813163wrh.250.1549847740611; Sun, 10 Feb 2019 17:15:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549847740; cv=none; d=google.com; s=arc-20160816; b=0cQvJaI6oc/4fbYs+VC6LRTSY6N1oSViaCcdsaBIzItK6n2YFhC0zQk30v0eD8gUbx LOHFK+vchsvovaSvRP37yOGicuN2gqHtEmy2ubwx9Bt/RJDVhaBBMq1VdnVDPUaW6XML w+biBYWO6lr1dD0PlTVbBGvHqvmx7N/pJdr4GSZ0xnbafkRj9LjpRz3JkYFxkl5XPrsF k73fSSuyywDO743/rmO/zK7ueSgsjOI67DMjyjDoEMEiLh2D0qlDg84QYPgyEzl1a3ym BsC3tDEgJp3EWQWxWDc3y8uVHwVA9nQ4Ar8krUsMFogoshF7dcKzCP5L2R/MpNjY8D30 2l8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UEnsVDtpBAmvsaSmrhCYvPqLmi/uP/YwCQYnlJNxoOc=; b=kVP5lcWxnZhqSI/p1UB0jmIQ0klc484B3t7qsoaUn59hTOLnHEjEB86rSC24kZI7mT hFeojXpoonqMrAz4XSntWmKN2JMuKby1kRL4kNEr4++puKZg1b73mM3z6t0BEo5Dqegf 9uQiag60Ly5OVBZIBWl9tk5w5ZRgv3bh7jEqSlQtK+ZMOIC9wSDz6E2Y1hYZSBBOOfnk ZZQSJJkX3/zMCGCJHjUSjONvKrGo35tsWnTItnYF+1RtBiLCsvAH0CmFedSKA98ymx2N YmKRUnECiUQJZOWycd4Bjylxxsdp4i+pKBuXeOCcXWoudU46ObtNni1+z+b+z1v2Ovrw 958A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bOaQpOpN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:29 -0800 Message-Id: <20190211010829.29869-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 26/26] tests/tcg/aarch64: Add mte smoke tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-1.c | 27 +++++++++++++++++++++ tests/tcg/aarch64/mte-2.c | 39 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 ++++ 3 files changed, 70 insertions(+) create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c -- 2.17.2 diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..740bf506f1 --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,27 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +int main(int ac, char **av) +{ + int *p0 = data; + int *p1, *p2; + long c; + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1)); + assert(p1 != p0); + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1)); + assert(c == 0); + + asm("stg [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0)); + assert(p1 == p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..4d2004ab41 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,39 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include +#include +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +void pass(int sig) +{ + exit(0); +} + +int main(int ac, char **av) +{ + int *p0 = data; + int *p1, *p2; + long excl = 1; + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg [%0]" : : "r"(p1)); + + *p1 = 0; + signal(SIGSEGV, pass); + *p2 = 0; + + assert(0); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 55420aeea6..614dfcd14d 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -22,4 +22,8 @@ AARCH64_TESTS += bti-1 bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib run-bti-1: QEMU += -cpu max,x-guarded-pages=on +AARCH64_TESTS += mte-1 mte-2 +mte-%: CFLAGS += -O -g +run-mte-%: QEMU += -cpu max,x-tagged-pages=on + TESTS:=$(AARCH64_TESTS)