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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:31 -0800 Message-Id: <20190211235258.542-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 01/28] target/arm: Split out arm_sctlr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Minimize the number of places that will need updating when the virtual host extensions are added. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 ++++++++++++++++---------- target/arm/helper.c | 8 ++------ 2 files changed, 18 insertions(+), 16 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 29663a264d..20be9fb53a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2987,11 +2987,20 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) != 0; } +static inline uint64_t arm_sctlr(CPUARMState *env, int el) +{ + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return env->cp15.sctlr_el[1]; + } else { + return env->cp15.sctlr_el[el]; + } +} + + /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - int cur_el; - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { return @@ -3010,15 +3019,12 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) arm_sctlr_b(env) || #endif ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + } else { + int cur_el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, cur_el); + + return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; } - - cur_el = arm_current_el(env); - - if (cur_el == 0) { - return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; - } - - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; } #include "exec/cpu-all.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 520ceea7a4..d4abbb5076 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13796,12 +13796,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } - if (current_el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[current_el]; - } + sctlr = arm_sctlr(env, current_el); + if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether From patchwork Mon Feb 11 23:52:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158034 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3198938jaa; Mon, 11 Feb 2019 15:53:45 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ5Hq/lt12J+vdDNvbGRBDBc5C7nPA9IBj594mE8PmGJXdARQUZRpyPgsmqeNkxPCxQD+xZ X-Received: by 2002:a0d:e6c8:: with SMTP id p191mr27886ywe.444.1549929225390; Mon, 11 Feb 2019 15:53:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929225; cv=none; d=google.com; s=arc-20160816; b=wQu2hW7+VFGKAvMHoBo6c+imhWJODgBb3ZZ8h6yyq19faMwUQ+aT35b77R84g6g11k QLho/EjOZze2qFwhGPgtSiLiMQ+NnHKAlaznbud+38vCAm/nTSAfrRLC/yPWffo6mpiR wW7rL/Hj87bZiaOUCJzgO456vsxCFq9FJbR5Hu8K44R0vgo3DPPqCOD0pGfJVQI6vlif EPV2IVA/lhiJGP3x0XG5RUf55qYZJN1bl/1Ze+tvIo//lJWlsuO8dW1W8uWEBh9MTHMM HLRCQFNAnf8KrtRv0z7wPMyyfCbzU0X0okR/cCHRaofR6c7/eG1Ybr6/q8d6JRKL77+C /7zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hbKS6AD3am/sY2oZ+gJOc5vr5/ws9wlGISFwMC+r3mY=; b=zxhPssVASB/rgPM7pkOT4A1YraCG0yD5VjUa0wp1fFjDPzpc0lbo85GEMB8BpTw+A4 pQUAzEUq9DZ1Iw/jPHuPOIER4zc3h9wzg5+iM8TfX2+J8k7WgRbQCBBz6HAiGFhfIiAf 9QeK2ttm8cRh7O31uwNB7zFifPlmwuzrRmlZzK/8WmLBTy61dZzxmcohpPmO1yBtuVdz gkemgMynogfPNFf+yT72XB6VfBM63RFqBHL2tkMBK5F93ZcToWhZiaNR2/7GF0dJ8e5d ZqAod+xe76ZWZGpbEDEO4NpwiJJuoodCY+CadVQMcABfafgFrgkzXvdbAW8kenk2i+zM sjHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rq2DDaSh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:32 -0800 Message-Id: <20190211235258.542-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 02/28] target/arm: Split helper_msr_i_pstate into 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The EL0+UMA check is unique to DAIF. While SPSel had avoided the check by nature of already checking EL >= 1, the other post v8.0 extensions to MSR (imm) allow EL0 and do not require UMA. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 3 +++ target/arm/helper.h | 1 - target/arm/internals.h | 15 ++++++++++++++ target/arm/helper-a64.c | 30 +++++++++++++++++++++++++++ target/arm/op_helper.c | 42 -------------------------------------- target/arm/translate-a64.c | 41 ++++++++++++++++++++++--------------- 6 files changed, 73 insertions(+), 59 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index aff8d6c9f3..a915c1247f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,9 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_2(msr_i_spsel, void, env, i32) +DEF_HELPER_2(msr_i_daifset, void, env, i32) +DEF_HELPER_2(msr_i_daifclear, void, env, i32) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..28b1dd6252 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,7 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) -DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) DEF_HELPER_2(get_r13_banked, i32, env, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..587a1ddf58 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); +static inline int exception_target_el(CPUARMState *env) +{ + int target_el = MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + #endif diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 101fa6d3ea..87b8f36122 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -61,6 +61,36 @@ uint64_t HELPER(rbit64)(uint64_t x) return revbit64(x); } +void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) +{ + update_spsel(env, imm); +} + +static void daif_check(CPUARMState *env, uint32_t op, + uint32_t imm, uintptr_t ra) +{ + /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ + if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { + raise_exception_ra(env, EXCP_UDEF, + syn_aa64_sysregtrap(0, extract32(op, 0, 3), + extract32(op, 3, 3), 4, + imm, 0x1f, 0), + exception_target_el(env), ra); + } +} + +void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1e, imm, GETPC()); + env->daif |= (imm << 6) & PSTATE_DAIF; +} + +void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1f, imm, GETPC()); + env->daif &= ~((imm << 6) & PSTATE_DAIF); +} + /* Convert a softfloat float_relation_ (as returned by * the float*_compare functions) to the correct ARM * NZCV flag state. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..c5721a866d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -68,20 +68,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, cpu_loop_exit_restore(cs, ra); } -static int exception_target_el(CPUARMState *env) -{ - int target_el = MAX(1, arm_current_el(env)); - - /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL - * to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { - target_el = 3; - } - - return target_el; -} - uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, uint32_t maxindex) { @@ -875,34 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) return res; } -void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) -{ - /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. - * Note that SPSel is never OK from EL0; we rely on handle_msr_i() - * to catch that case at translate time. - */ - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { - uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3), - extract32(op, 3, 3), 4, - imm, 0x1f, 0); - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)); - } - - switch (op) { - case 0x05: /* SPSel */ - update_spsel(env, imm); - break; - case 0x1e: /* DAIFSet */ - env->daif |= (imm << 6) & PSTATE_DAIF; - break; - case 0x1f: /* DAIFClear */ - env->daif &= ~((imm << 6) & PSTATE_DAIF); - break; - default: - g_assert_not_reached(); - } -} - void HELPER(clear_pstate_ss)(CPUARMState *env) { env->pstate &= ~PSTATE_SS; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 27b90d5778..13e010d27b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1647,29 +1647,38 @@ static void handle_sync(DisasContext *s, uint32_t insn, static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int crm) { + TCGv_i32 t1; int op = op1 << 3 | op2; + + /* End the TB by default, chaining is ok. */ + s->base.is_jmp = DISAS_TOO_MANY; + switch (op) { case 0x05: /* SPSel */ if (s->current_el == 0) { - unallocated_encoding(s); - return; + goto do_unallocated; } - /* fall through */ - case 0x1e: /* DAIFSet */ - case 0x1f: /* DAIFClear */ - { - TCGv_i32 tcg_imm = tcg_const_i32(crm); - TCGv_i32 tcg_op = tcg_const_i32(op); - gen_a64_set_pc_im(s->pc - 4); - gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); - tcg_temp_free_i32(tcg_imm); - tcg_temp_free_i32(tcg_op); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ - gen_a64_set_pc_im(s->pc); - s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); + t1 = tcg_const_i32(crm & PSTATE_SP); + gen_helper_msr_i_spsel(cpu_env, t1); + tcg_temp_free_i32(t1); break; - } + + case 0x1e: /* DAIFSet */ + t1 = tcg_const_i32(crm); + gen_helper_msr_i_daifset(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + + case 0x1f: /* DAIFClear */ + t1 = tcg_const_i32(crm); + gen_helper_msr_i_daifclear(cpu_env, t1); + tcg_temp_free_i32(t1); + /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ + s->base.is_jmp = DISAS_UPDATE; + break; + default: + do_unallocated: unallocated_encoding(s); return; } From patchwork Mon Feb 11 23:52:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158036 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3200446jaa; Mon, 11 Feb 2019 15:55:56 -0800 (PST) X-Google-Smtp-Source: AHgI3IZvJsY1Y/txkWdLxzdvSZQEiFiVDc49Y2kBPq0qn2SBrrTMSQ6QBlT0a9z0ASEqpeiAsdG5 X-Received: by 2002:a25:5a05:: with SMTP id o5mr655615ybb.510.1549929356028; Mon, 11 Feb 2019 15:55:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929356; cv=none; d=google.com; s=arc-20160816; b=SYTJtQErMDoeUBHeSGneySz3iP8X0kUsAXuy/wcLfHnifuN7zA5APhXVY2A294WXpF BpX4DIUmnb94ajlHCCgDREI7kH4yNvNmceacnGGPJG0T34MDebdGLT0KBc1y0aZHg0sS 3kxNMnOasGO1OqgY0jIurnXv10WxMwDZ9t3KkmLE++eS05yQcbcO4ux2fVbGRJ2s70OX CP6/zVFJ4Oek02q8ZP5id0hLyhrVKCwGl4qQd80IehaXoVOi8JwuKEELxtbwNngmylGq RMoWLiyrD5PMFwH7IPLik9oCYz6oz/k24D+hr0wfQaAEMTbRS3DHRKxa/1ry3iyK5PVN GwKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ItNJF+IPQ2RCWNqC/N6zjDNVc+cTfSXBzvGik2fXPgw=; b=V14VGvkgfevdWSnpEqSuX3ti21OfgkpHGb074/7oAn7s+1dqSFzphhT+yEW8uy8mq5 kQjUzu3OfWCBMCuYpGGUuyFZpHN1WrKoGMcoMpyVwAjLDaDNCvXmDhaPLk6iE1wNn5wH yiz/ggMuiJ6Rxm6nYzuJAxWLFtQjDW7PQl6wZ76THpx32hfN3A/U1U8wwz0zbhlwO7bv F1GQ6rgRitiZNzOJwKcfDr3znLPFfRgzHALjmOkECoJoCRhqEQ2oSCMaRm5QQ0hxHKjh YKSBDhaZaMS/0uulcMwZEdr96idRfs59d93CfVTPW+Z8CM2PajYCEPkbsiKc4DAtIF4L ZdRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z2y4ykkr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:33 -0800 Message-Id: <20190211235258.542-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v3 03/28] target/arm: Add clear_pstate_bits, share gen_ss_advance X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not need an out-of-line helper for clearing bits in pstate. While changing things, share the implementation of gen_ss_advance. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/translate.h | 19 +++++++++++++++++++ target/arm/op_helper.c | 5 ----- target/arm/translate-a64.c | 11 ----------- target/arm/translate.c | 11 ----------- 5 files changed, 19 insertions(+), 29 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.h b/target/arm/helper.h index 28b1dd6252..c21fa2edfe 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,8 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) -DEF_HELPER_1(clear_pstate_ss, void, env) - DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 17748ddfb9..33af50a13f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -202,6 +202,25 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } +/* Clear bits within PSTATE. */ +static inline void clear_pstate_bits(uint32_t bits) +{ + TCGv_i32 p = tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i32(p, p, ~bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + +/* If the singlestep state is Active-not-pending, advance to Active-pending. */ +static inline void gen_ss_advance(DisasContext *s) +{ + if (s->ss_active) { + s->pstate_ss = 0; + clear_pstate_bits(PSTATE_SS); + } +} /* Vector operations shared between ARM and AArch64. */ extern const GVecGen3 bsl_op; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c5721a866d..8698b4dc83 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -861,11 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) return res; } -void HELPER(clear_pstate_ss)(CPUARMState *env) -{ - env->pstate &= ~PSTATE_SS; -} - void HELPER(pre_hvc)(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 13e010d27b..ba139bba26 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -421,17 +421,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, s->base.is_jmp = DISAS_NORETURN; } -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss = 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..baf6068ec1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -298,17 +298,6 @@ static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) tcg_temp_free_i32(tcg_excp); } -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss = 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:34 -0800 Message-Id: <20190211235258.542-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v3 04/28] target/arm: Add MTE_ACTIVE to tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE, then arrange to perform the check while stripping the TBI. The check is not yet implemented, just the plumbing to that point. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Clean TBI bits exactly. Fix license to lgpl 2.1. v3: Remove stub helper_mte_check; moved to a later patch. --- target/arm/cpu.h | 12 +++++++++ target/arm/internals.h | 18 ++++++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 51 ++++++++++++++++++++++++++++++-------- target/arm/translate-a64.c | 1 + 5 files changed, 73 insertions(+), 11 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 20be9fb53a..2776df6981 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1215,6 +1215,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3071,6 +3072,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 14, 1) static inline bool bswap_code(bool sctlr_b) { @@ -3361,6 +3363,16 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; } +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..6c018e773c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -983,4 +983,22 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr != 0; +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index 33af50a13f..5a101e1c6d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -70,6 +70,8 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE tag checks affect the PE. */ + bool mte_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index d4abbb5076..e73bdbf041 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1862,6 +1862,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= SCR_ATA; + } /* Clear all-context RES0 bits. */ value &= valid_mask; @@ -4056,22 +4059,31 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = arm_env_get_cpu(env); - if (raw_read(env, ri) == value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { /* M bit is RAZ/WI for PMSA with no MPU implemented */ value &= ~SCTLR_M; } - raw_write(env, ri, value); + if (!cpu_isar_feature(aa64_mte, cpu)) { + if (ri->opc1 == 6) { /* SCTLR_EL3 */ + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); + + if (raw_read(env, ri) != value) { + /* + * This may enable/disable the MMU, so do a TLB flush. + * Skip the TLB flush if nothing actually changed; + * Linux likes to do a lot of pointless SCTLR writes. + */ + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4564,6 +4576,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= HCR_API | HCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= HCR_ATA; + } /* Clear RES0 bits. */ value &= valid_mask; @@ -13756,6 +13771,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); uint64_t sctlr; + int tbid; *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13764,7 +13780,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; + int tbii; /* FIXME: ARMv8.1-VHE S2 translation regime. */ if (regime_el(env, stage1) < 2) { @@ -13817,6 +13833,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + + /* + * If MTE is enabled, and tag checks affect the PE, + * then we check the tag as we strip the TBI field. + * Note that if TBI is disabled, all accesses are unchecked. + */ + if (tbid + && cpu_isar_feature(aa64_mte, cpu) + && allocation_tag_access_enabled(env, current_el, sctlr) + && !(env->pstate & PSTATE_TCO) + && (sctlr & (current_el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ba139bba26..3950067b79 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14041,6 +14041,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->mte_active = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Mon Feb 11 23:52:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158045 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3205832jaa; Mon, 11 Feb 2019 16:02:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IZggCCe3dCp3CSQ8IaC0BAmXBjLdySLSiVN/Qg0+MnQqb6jb9Q1st0her5162Zen0G/cwi+ X-Received: by 2002:a81:5d0b:: with SMTP id r11mr620648ywb.313.1549929760835; Mon, 11 Feb 2019 16:02:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929760; cv=none; d=google.com; s=arc-20160816; b=ETihR8eRA5TSN5k4YSmbNvDmNA+k1+y3I0aRFEPwmyhd4I0rRJHNzzkEueDnSJFZyN 2Be4z5ctEzwnAmib/xB9iUSaX2u/tuG+uU9hlyLcAuJb30MdLEq3V+0Qpm+nfh+LHJA2 5L1ox0e54oqdxRbZZSjes8SJbfnRw6zIAut2V8ArVkhvnB2KYZueIX9tyYzxd6zUrk9Z XbLhSesn+paOhzemTVPJ/6FzTAZmcNsenDw9QMMKJMpS9TwDnJ1GfSNWKazFFTkQo5IZ 9vFwBCPnEBckgFKuTyGM5TSFhUehVdNrXQbcS/TwUEQM/1tlqqkjO/tkkLEkypFvJDmK yTLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sSJPTVVkjcWARcwigg6wJDNen7ofl5R1qSbWzhReSSs=; b=jvSxDDNZW/BxjYybe1eiNeLRCyqa1wRW621tGWK7NRwcDJwxYTiZ2k8Zw+kE1UhNXi JVNNkxq5ma9hWCQyHpMXy/ScTiXROWig/6f2sQjxBM8eSFERzaOcc5Ugg2B0ToY3w9Du UREyBqB+mqib+8n5Xy0KNIZglwFSi/vzr2dGVi16YEnLzoMpPIRh8MxKnWqLfbYttTB1 KSqtY9lfLwPTTeOK91Ve9VIRQ92Bf2IlA93l9lAJH9D7lkOvNp8dgV8wNHGjts/S/5qZ VtfiWDl5W7BUxaKGGci7Oh1LMzWOEgCr4tFqApbIfvmsUWUJThLQOZQQwwIXIyd7F++u W9UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ou0+mTUM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 05/28] target/arm: Extract TCMA with ARMVAParameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c018e773c..2922324f63 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -959,6 +959,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; diff --git a/target/arm/helper.c b/target/arm/helper.c index e73bdbf041..cbe3500f78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10447,7 +10447,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; /* @@ -10462,11 +10462,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi = tbid = hpd = false; + tbi = tbid = hpd = tcma = false; } else { tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); tbid = extract32(tcr, 29, 1); + tcma = extract32(tcr, 30, 1); } epd = false; } else if (!select) { @@ -10477,6 +10478,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); tbid = extract64(tcr, 51, 1); + tcma = extract64(tcr, 57, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; @@ -10486,6 +10488,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); tbid = extract64(tcr, 52, 1); + tcma = extract64(tcr, 58, 1); } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -10497,6 +10500,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, .tbid = tbid, .epd = epd, .hpd = hpd, + .tcma = tcma, .using16k = using16k, .using64k = using64k, }; From patchwork Mon Feb 11 23:52:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158052 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3211833jaa; Mon, 11 Feb 2019 16:09:21 -0800 (PST) X-Google-Smtp-Source: AHgI3Ibtb//QGtpF1QTLzQGn9haSXwy66AYx8smk/oZTPlqJ+05oa6mzhf71pCEMRbDdO0+FmpB9 X-Received: by 2002:a25:830f:: with SMTP id s15mr659407ybk.135.1549930161615; Mon, 11 Feb 2019 16:09:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930161; cv=none; d=google.com; s=arc-20160816; b=u64Sc7lgbOHM5z8uPFUcfAQvmwqFqE0Mca/sOf/iHJXNCDquulRMuRMfu83Moa2Phk Ep1ZplPqc1ZLEeAExJpeK9gLXS9D2QWwFVXx4UrIjv7w+MdkC7GYJbZg0wHgQT270NFw DE0euObaFdWOyMwmGmst4ZD7iECxTjwo3lmL7xqVlRt9xyiwYnxd+bxQ4s8STRy2pCxq HCPa+MQUpfomYC1oezEELXjEZcEMcq38tMJtKzpWRwR5ptLyev/BQO/pkaq64HhfBwQd vgu2ah3hRzX4h6z9ErEhlzP7gLKBaPSLilQctD76GTnkdxe2Lhy91ynSL/rwOPfUAvCJ nG9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZiSulLpDJWuscSL8L2vnGag9UcUin0Tqpz1gsAL73nE=; b=Bar/UZM7r0LBGODEYeb3IZtFKJikIjhlmWAs1S4ULdlLXFrz+ABoWNot8yjzGmO+Oc TY1NmazyQDrZVizlzOw6DTZl3eJvLeu08y9qQdxqvaEQnmdtHYvxIXFWFII8oy8ngc9Z r2HHHJ0Kt8pQDyA6ZYWJ8+mRM1gdJRvIizIVaLKz0HB2yge60jrGtfHSLQUWP9mIyP7H uthtNmj6U9NAzMMJ8FnRisGSkrdVbZKv7vV1gxGYYyQWF1/30TQwjLfvZlJqHd7ICfOn ykCiYZprndcPafRdwAdC7uICGP+4drkp7yt+HUC4o731hxvC2Ahq0OL9b9HaBoDmNKOr P9wQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Nmx489sU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:36 -0800 Message-Id: <20190211235258.542-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 06/28] target/arm: Add MTE system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- v3: Add GMID; add access_mte. --- target/arm/cpu.h | 5 +++ target/arm/internals.h | 6 ++++ target/arm/translate.h | 11 +++++++ target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 +++++++ 5 files changed, 99 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2776df6981..74633a7a78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -495,6 +495,11 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ +#ifdef TARGET_AARCH64 + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; +#endif } cp15; struct { diff --git a/target/arm/internals.h b/target/arm/internals.h index 2922324f63..fbfa770c23 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,4 +1002,10 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, return sctlr != 0; } +/* + * The log2 of the words in the tag block, for GMID_EL1.BS. + * The is the maximum, 256 bytes, which manipulates 64-bits of tags. + */ +#define GMID_EL1_BS 6 + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index 5a101e1c6d..a24757d3d7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,17 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } +/* Set bits within PSTATE. */ +static inline void set_pstate_bits(uint32_t bits) +{ + TCGv_i32 p = tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i32(p, p, bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + /* Clear bits within PSTATE. */ static inline void clear_pstate_bits(uint32_t bits) { diff --git a/target/arm/helper.c b/target/arm/helper.c index cbe3500f78..f8e4e6f8ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5732,6 +5732,69 @@ static const ARMCPRegInfo pauth_reginfo[] = { .fieldoffset = offsetof(CPUARMState, apib_key.hi) }, REGINFO_SENTINEL }; + +static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ATA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) +{ + env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] = { + { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 6, .opc2 = 1, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL2_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 6, .opc2 = 0, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, + { .name = "TCO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, + .type = ARM_CP_NO_RAW, + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + REGINFO_SENTINEL +}; #endif void register_cp_regs_for_features(ARMCPU *cpu) @@ -6577,6 +6640,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3950067b79..f397603688 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1666,6 +1666,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_UPDATE; break; + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s); From patchwork Mon Feb 11 23:52:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158040 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3202906jaa; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:37 -0800 Message-Id: <20190211235258.542-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c Subject: [Qemu-devel] [PATCH v3 07/28] target/arm: Assert no manual change to CACHED_PSTATE_BITS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits are stored elsewhere; changing env->pstate has no effect. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.2 diff --git a/target/arm/translate.h b/target/arm/translate.h index a24757d3d7..296d1ac72c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -209,6 +209,8 @@ static inline void set_pstate_bits(uint32_t bits) { TCGv_i32 p = tcg_temp_new_i32(); + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ori_i32(p, p, bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); @@ -220,6 +222,8 @@ static inline void clear_pstate_bits(uint32_t bits) { TCGv_i32 p = tcg_temp_new_i32(); + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_andi_i32(p, p, ~bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); From patchwork Mon Feb 11 23:52:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158044 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3204570jaa; Mon, 11 Feb 2019 16:01:26 -0800 (PST) X-Google-Smtp-Source: AHgI3IbM7gxbWA2u+2JiCWJPwf4AhzXJwM1epKZfpSiodV459teud5ivWuTnxTTu1FXr+GqXbGP2 X-Received: by 2002:a81:9ac1:: with SMTP id r184mr631357ywg.365.1549929686008; Mon, 11 Feb 2019 16:01:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929686; cv=none; d=google.com; s=arc-20160816; b=qi4t+nfJInvBHfiV1PLY7t2oZ+Nu/wURVW8q79x2gOIVrgSCDKQkW6wxOKUHH23j29 trMbT7uS9uHa9IIZrcovwwF7jTvHb7M/PAmMdvUFWq4s+sEVdEyOxNtaFteVrcY4Oob7 sm6ApfFwvAsBnk2pFdMfkSNksH28anuRLFGWvZZchJBB/BKOv5nZDp1+OwOpmxrQaWPv FPSgS7xIS7os0fPRgIOYiL5Z95LokuFA8Y3tpTM7gSqIoYkwG83qb0PhXAXHDPMK0o44 Zn5L67MwCngeMRBuPnpC8BPlJ89SiIXXxASviJUPhXD+VaxrRlHtyARgxkmFvk3YgcTj oTXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2OQxyPmxfrr4UMT/ZUzdlEYMHFpvU0QnUKFRrfWrKM0=; b=azBxG1j5541gU17eSepx1HKoJQVAwrk2rHzIBcfVlPfMxRUj/GgsFBNM2Wxu1LlER1 XaDQWijzFNbhvShq5MFj9LOOUpK9NO6IazFTKdGFbwmvb+wqV5wi1ZMSB1ca8aKObT2v q6sLAv1sKKJwywHfwh66OK0b4nAkVrt9CGaEnJaNPkS/xV/NUK9KtTC6blXiXuLlgWlN QYRjW7J4xR9C4nTR/pyjgrbR+qwIQGiOvhDdKBcSg78ZV11wxGt/FCs+lvmQk12tnz2w zFlnvASKl+g2wZgnrQqEmSGoYe/FSJsHCg+Q+d7nQuGOZVbyHQoRXEFjzGWFtlOmhMT/ VjrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SllnUeWO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:38 -0800 Message-Id: <20190211235258.542-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [PATCH v3 08/28] target/arm: Add helper_mte_check{1, 2} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already implied by TB_FLAGS_MTE_ACTIVE. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- v2: Fix TFSR update. v3: Split helper_mte_check per {1,2} IAs; take tbi data from translate. --- target/arm/helper-a64.h | 3 + target/arm/mte_helper.c | 133 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 14 +++- target/arm/Makefile.objs | 2 +- 4 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 target/arm/mte_helper.c -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..c88797a922 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,6 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 0000000000..bcd82a9be0 --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,133 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ + return extract64(ptr, 56, 4); +} + +/* + * Perform a checked access for MTE. + * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. + */ +static uint64_t do_mte_check(CPUARMState *env, uint64_t dirty_ptr, + uint64_t clean_ptr, uint32_t select, + uintptr_t ra) +{ + int ptr_tag, mem_tag; + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules R0076 & R0077 are written with logical tags, + * and we need the physical tag below anyway. + */ + ptr_tag = allocation_tag_from_addr(dirty_ptr); + if (ptr_tag == 0) { + ARMMMUIdx stage1 = arm_stage1_mmu_idx(env); + ARMVAParameters p = aa64_va_parameters(env, dirty_ptr, stage1, true); + if (p.tcma) { + return clean_ptr; + } + } + + /* + * If an access is made to an address that does not provide tag storage, + * the result is implementation defined (R0006). We choose to treat the + * access as unchecked. + * This is similar to MemAttr != Tagged, which are also unchecked. + */ + mem_tag = get_allocation_tag(env, clean_ptr, ra); + if (mem_tag < 0) { + return clean_ptr; + } + + /* If the tags do not match, the tag check operation fails. */ + if (unlikely(ptr_tag != mem_tag)) { + int tcf, el = arm_current_el(env); + + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + tcf = extract64(env->cp15.sctlr_el[1], 38, 2); + } else { + tcf = extract64(env->cp15.sctlr_el[el], 40, 2); + } + if (tcf == 1) { + /* + * Tag check fail causes a synchronous exception. + * + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(ENV_GET_CPU(env), ra, true); + env->exception.vaddress = dirty_ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11), + exception_target_el(env)); + } else if (tcf == 2) { + /* Tag check fail causes asynchronous flag set. */ + env->cp15.tfsr_el[el] |= 1 << select; + } + } + + return clean_ptr; +} + +/* + * Perform check in translation regime w/single IA range. + * It is known that TBI is enabled on entry. + */ +uint64_t HELPER(mte_check1)(CPUARMState *env, uint64_t dirty_ptr) +{ + uint64_t clean_ptr = extract64(dirty_ptr, 0, 56); + return do_mte_check(env, dirty_ptr, clean_ptr, 0, GETPC()); +} + +/* + * Perform check in translation regime w/two IA ranges. + * The TBI argument is the concatenation of TBI1:TBI0. We have filtered + * TBI==0, but still need to check the IA range being referenced. + */ +uint64_t HELPER(mte_check2)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) +{ + uint32_t select = extract64(dirty_ptr, 55, 1); + + if ((tbi >> select) & 1) { + uint64_t clean_ptr = sextract64(dirty_ptr, 0, 56); + return do_mte_check(env, dirty_ptr, clean_ptr, select, GETPC()); + } else { + /* TBI is disabled; the access is unchecked. */ + return dirty_ptr; + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f397603688..1465c52a05 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -343,7 +343,19 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean = new_tmp_a64(s); - gen_top_byte_ignore(s, clean, addr, s->tbid); + + if (s->mte_active) { + if (s->current_el >= 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + gen_helper_mte_check1(clean, cpu_env, addr); + } else { + TCGv_i32 tbi = tcg_const_i32(s->tbid); + gen_helper_mte_check2(clean, cpu_env, addr, tbi); + tcg_temp_free_i32(tbi); + } + } else { + gen_top_byte_ignore(s, clean, addr, s->tbid); + } return clean; } diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1a4fc06448..c86cb1af5c 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,7 +8,7 @@ obj-y += translate.o op_helper.o helper.o cpu.o obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o obj-y += gdbstub.o obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-$(TARGET_AARCH64) += pauth_helper.o +obj-$(TARGET_AARCH64) += pauth_helper.o mte_helper.o obj-y += crypto_helper.o obj-$(CONFIG_SOFTMMU) += arm-powerctl.o From patchwork Mon Feb 11 23:52:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158042 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3203775jaa; Mon, 11 Feb 2019 16:00:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IYlKvFZiWyI5s+7jjc04B2FzRbHkKJ2LsEN4xvX/j9o5+1sXab7tGN9ok8KAqqhhW8M3HUt X-Received: by 2002:a25:20f:: with SMTP id 15mr624888ybc.453.1549929640267; Mon, 11 Feb 2019 16:00:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929640; cv=none; d=google.com; s=arc-20160816; b=mE9J+gO7WB7WKH44kepk6LNidAP7J7ljjar/wnk7GdyNTebBRdIFMtoikyfZ68bgRo naJA03TpLvPtckWGMBtwdVZwCIpDKBrhEF1OdBDS6IRfEwQ64+7+9kqxBY0V/ghytcfs bFG0tHMVdpOKrQ6Qhc9IcpyAkjd/9sSaMJHQqezNVziCl8Ils0vVZGU9L/Ww+h0ZtcEz q30HuGw/tCpII290BTqoaOZBmNhXvhGoFj23PJDtZSrsAX1y/avVr9L79CmjKso4dCDF aF8SczptdpFTdsTbXV03np7Tmmn4I3cxOP2vn9M+4GOcSFrNOEZ1x1wYG2CAoGkOOvKZ /7Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IyxP/jQzqtmvSIHHr3lmN5MXpU1gzFjdHYAoOgzE02E=; b=VIFxCGBQV12MKGNmd1vp1c9wPJ0s5thl+6ZyvSkUXEK51Go1Oz/+3QFNMsotprZMEv p59iWBylxqGeAxZxyvXQB/G6B+swUwQttxVyViv5tQHp0EkrCBWcULlhDNkmLxlGl+vc ysDIJqiFGXitGaSuD/NnJStOvWPBl0/OgN8z7pr9BvxUJVLaUXUbcS3tZDLWMwNTl4T4 4dQiigo6H4hTNGTvpL6jVXBgBNmOslgswaBWv9PjCpYSW1H06qy9/Q13CKdZI+d8u7+c JyM2El3GovzXJ+aPre9ohQMZ9SFyDqsFFYzyi1VerLfJa4W4y3IT6daxOBBfEjaAQY/a SaNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CZ1yIOy0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:39 -0800 Message-Id: <20190211235258.542-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PATCH v3 09/28] target/arm: Suppress tag check for sp+offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0078 specifies that base register, or base register plus immediate offset, is unchecked when the base register is SP. Signed-off-by: Richard Henderson --- v2: Include writeback addresses as checked. --- target/arm/translate-a64.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1465c52a05..27ceea66d1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -340,11 +340,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) * This is always a fresh temporary, as we need to be able to * increment this independently of a dirty write-back address. */ -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool check) { TCGv_i64 clean = new_tmp_a64(s); - if (s->mte_active) { + if (check && s->mte_active) { if (s->current_el >= 2) { /* FIXME: ARMv8.1-VHE S2 translation regime. */ gen_helper_mte_check1(clean, cpu_env, addr); @@ -2385,7 +2385,7 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2403,7 +2403,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); if (size == 2) { TCGv_i64 cmp = tcg_temp_new_i64(); @@ -2528,7 +2528,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; @@ -2537,7 +2537,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2557,7 +2557,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2573,7 +2573,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2587,7 +2587,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2605,7 +2605,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2795,7 +2795,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); if (is_vector) { if (is_load) { @@ -2933,7 +2933,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, writeback || rn != 31); if (is_vector) { if (is_store) { @@ -3040,7 +3040,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, true); if (is_vector) { if (is_store) { @@ -3125,7 +3125,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, dirty_addr = read_cpu_reg_sp(s, rn, 1); offset = imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn != 31); if (is_vector) { if (is_store) { @@ -3209,7 +3209,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_rs = read_cpu_reg(s, rs, true); if (o3_opc == 1) { /* LDCLR */ @@ -3271,7 +3271,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, is_wback || rn != 31); tcg_rt = cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, @@ -3431,7 +3431,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) elements = (is_q ? 16 : 8) / ebytes; tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (r = 0; r < rpt; r++) { @@ -3574,7 +3574,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (xs = 0; xs < selem; xs++) { From patchwork Mon Feb 11 23:52:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158056 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3215013jaa; Mon, 11 Feb 2019 16:13:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IY4CtOH7mPKB7wI3pEfkv2ytYgtUrakwoMB463TaSFwqe7RUVUby1rdB37CzLh0PGa1v1hm X-Received: by 2002:a0d:cc46:: with SMTP id o67mr701437ywd.123.1549930420021; Mon, 11 Feb 2019 16:13:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930420; cv=none; d=google.com; s=arc-20160816; b=cNUv+kltl7lUKjFwdpfsCBfKv4oFLGBeejHWcpvGX+VentANW23r4j8PGnJCYmj5lt db23LC8q2r7mulgzkk9r/dpw01LZzSu3tzpAyAnG1KleO4nvJYCYNTZ97/KmevIvff/I +6tpkFwoP5iffI/t7EU1lzUhDgEcG9xL5oOFYSnzUQOVvmOKaXVU3hcT4oreFQtzpmXm tCub6j562yKNM6wDLE7RtXAjEzRJ6o11WTqGE+p8UOUo4pJbWM9r5futViKDLl1FG/oG AJ0Zf6kFILXOIW6huROwITCABrYjlfCYgElyyj80ja9v0tG3pH37Y3v7gCav31AK40Rn 8IBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yBCUhDhUUX/BVeMsTLdHvYEBPRtZXUGYZEktbYJveAI=; b=wf0BM6EQO8+soZ/N127hzQy+c2QgZxAKR829AeR07aqcA2ftU9hAdgAOnYfuGEOxgn mHgCQe79imkoB+r2HqXYYPxYDyg/PIBcjPVkqgUbR4BBlvNHLIb426xTCfbqo+ccl62d Z67mn1LD54Tsbyhti3wYod6vwIvMCJ/YTuGQ6FFcApoQ38aafzGIH1vSTQn2AZxduOxo XaVULlj/b2owoqPQxnSvNzv/PVhLJt+F2/pFx4zfWo4jZhWKjhWJaczqI3bwwmMBQFKw VqAYm7MKdKKj2/pCvysViFZfuOCeGXNVU2wV7iXIKI1Pf71MpKPhKgdQFE1sRRnuqn3J 8kaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MIJ5oHxz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 10/28] target/arm: Implement the IRG instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Update to 00eac5. Merge choose_random_nonexcluded_tag into helper_irg since that pseudo function no longer exists separately. --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 +++++ 3 files changed, 65 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index c88797a922..0f6e78c77e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,4 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index bcd82a9be0..cd04e4954b 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -37,6 +37,31 @@ static int allocation_tag_from_addr(uint64_t ptr) return extract64(ptr, 56, 4); } +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude == 0xffff) { + return 0; + } + if (offset == 0) { + while (exclude & (1 << tag)) { + tag = (tag + 1) & 15; + } + } else { + do { + do { + tag = (tag + 1) & 15; + } while (exclude & (1 << tag)); + } while (--offset > 0); + } + return tag; +} + +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + rtag -= extract64(ptr, 55, 1); + return deposit64(ptr, 56, 4, rtag); +} + /* * Perform a checked access for MTE. * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. @@ -131,3 +156,35 @@ uint64_t HELPER(mte_check2)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) return dirty_ptr; } } + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + /* + * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if + * GCR_EL1.RRND==0, always producing deterministic results. + */ + uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); + int start = extract32(env->cp15.rgsr_el1, 0, 4); + int seed = extract32(env->cp15.rgsr_el1, 8, 16); + int offset, i; + + /* RandomTag */ + for (i = offset = 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed = (top << 15) | (seed >> 1); + offset |= top << i; + } + rtag = choose_nonexcluded_tag(start, offset, exclude); + + env->cp15.rgsr_el1 = rtag | (seed << 8); + } + + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 27ceea66d1..141a03a88f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5133,6 +5133,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Mon Feb 11 23:52:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158051 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3211411jaa; Mon, 11 Feb 2019 16:08:46 -0800 (PST) X-Google-Smtp-Source: AHgI3Ibgqt8A2W/JOuGvqUuhs409qdk/NVQtaKRq9LtrlSLzK9V6ymybUDFSvfiPZPOCpFaLB1QM X-Received: by 2002:a81:3944:: with SMTP id g65mr670015ywa.337.1549930126932; Mon, 11 Feb 2019 16:08:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930126; cv=none; d=google.com; s=arc-20160816; b=bpV36i4Y82ECviqBl32QN84TlQxUZf7dL6kfmevjBdtCB4LNL5Djq9zGFhjR0jjzjh lIrnsnH3K5Sl4S+cwmtEoPJM0U92xX+wAPhhyN0a5lMYZarxSsF3khQLggGwHjJHa6XH ci1N+5k6lv2IVpnE83aLrpdMXb2D75VKIZC7qoNwhRjkhqTSr9Uh2Yhlbh2pzJFrdY7B FreD1/1YG7O4rUWQn9wLENQC4KDDR4xObzS/zSHjtQCIkuggO+HC4ANtFLPZrfJNFT2d qeuRG3XgzHKLUwi4KUpLLDgRTwtWeXt4z7Z5cqcP03Mm5vYp98uRDCluBs0OAOx7KEHg 85Sw== ARC-Message-Signature: i=1; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:41 -0800 Message-Id: <20190211235258.542-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 11/28] target/arm: Implement ADDG, SUBG instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Shift offset in translate; use extract32. --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 4 +++ target/arm/mte_helper.c | 32 +++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 86 insertions(+), 23 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 0f6e78c77e..6ad23bf9ee 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -106,3 +106,5 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index fbfa770c23..8d1a81df8c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1008,4 +1008,8 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, */ #define GMID_EL1_BS 6 +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 +#define TAG_GRANULE (1 << LOG2_TAG_GRANULE) + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index cd04e4954b..7aca5b074f 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -188,3 +188,35 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 141a03a88f..8e322bd6a0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3679,7 +3679,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3690,10 +3692,10 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) bool setflags = extract32(insn, 29, 1); bool sub_op = extract32(insn, 30, 1); bool is_64bit = extract32(insn, 31, 1); + bool is_tag = false; TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; switch (shift) { case 0x0: @@ -3701,35 +3703,58 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) case 0x1: imm <<= 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag = true; + break; default: + do_unallocated: unallocated_encoding(s); return; } - tcg_result = tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm = tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset = tcg_const_i32(imm & 15); + TCGv_i32 offset = tcg_const_i32((imm >> 6) << LOG2_TAG_GRANULE); - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result = tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm = tcg_const_i64(imm); + tcg_result = new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } /* The input should be a value in the bottom e bits (with higher From patchwork Mon Feb 11 23:52:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158041 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3203616jaa; Mon, 11 Feb 2019 16:00:31 -0800 (PST) X-Google-Smtp-Source: AHgI3IZmGNoAWg4WeYOZ0Shf0bHIzFxI9+ub8UYsxEEz1XUHrArAIHWFskbrAn6cvZ6nYfuQMSsx X-Received: by 2002:a25:6754:: with SMTP id b81mr620213ybc.425.1549929631183; Mon, 11 Feb 2019 16:00:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929631; cv=none; d=google.com; s=arc-20160816; b=zoSrcBsBrsnsMhacllY+8d/lNCnimpwaZACBjejKnvEmXEUh6B8SbB1pJqMDzvYZef V6UyKGjh18UQz1LtxtztANNxDkg3tftPBNHvuFhYeDf634gSCJ9onWGlWogUqLs1hJqa xmnEhHRCiLRAZlgR7813BoK0ks2SAnbhEcpmmhk2pf/SIbKMtxly/7xzhENAUtkvVH1E BdfrLl+bTKCZ6OMf/n+qZsnncwo62MbSp55d5OCeW7O02pYfDYdCK3DbXj4vci9e0CBz VMrkpmP3xPvMRQoKroCFOEhrSx1cIjbXlSw9HYcsX5Qff5xs7KSFEUVTsIExI25DTNpp vXTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Kmm2As5QErToKnAZtTaLla6p1MaYpNIuxtZbUjkLWnk=; b=Ch/L9CLMY/GGydRiqz+mYK9c+v+E35i77g+y9IblRtwXscLEDhpnV/iXhOZfe+1x2X Qbijo/spq+rq7Qar0GwgnWk3ayWoMGPT+GWx5FcNDGBatHxpQPfCdZpUxpG08KWvgnKj 8CR5B1gjPXMa+11L+RXMkpt42UeQZRiQzvPCZiHfxX6YEkGqfilgDC7cyGC01Hmz28yi N4dx1t1NWIJd5obFKQtLYkJenXScYXtrp//aBIx79VFsTTujwf/caZXRPIz/q6ytA5MD iGLh/B2eIesVfUXuzhKVa/HBjdqGJis2IQfte1qwnjSXeqk5ChJKCJx4XHdUlKnHlmik IwsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZidENpA9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:42 -0800 Message-Id: <20190211235258.542-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 12/28] target/arm: Implement the GMI instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6ad23bf9ee..3b78e19279 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -108,3 +108,4 @@ DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 7aca5b074f..e60c6f48eb 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -220,3 +220,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag = allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8e322bd6a0..791bcc3b66 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5165,6 +5165,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Mon Feb 11 23:52:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158047 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3207572jaa; Mon, 11 Feb 2019 16:04:31 -0800 (PST) X-Google-Smtp-Source: AHgI3IbUEYb/31o6YvqjMK3r5kVra0OLMIWcckmOgxAYsW1K6gfgXWNZ5KF98kql+zl/NB0CbLA4 X-Received: by 2002:a81:4c54:: with SMTP id z81mr655955ywa.219.1549929871416; Mon, 11 Feb 2019 16:04:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929871; cv=none; d=google.com; s=arc-20160816; b=nB/WSy8esv3I12Zu3fk3JHtg5c0J1TjbiHYnRl5AhWEms91TuwYKHO6xTPSikJQMz5 zHwjt8C8aiW/DEsatX4h+N6qPVOCLeiLapmlbFl9nM8z7Xj8TLnRCVaSQrm67/N6O8iF fHXu/20dWR3xOoa7SO2nfwVJXsTWVo18k6RB0wVa96xxfGO93iUZzshcD01f64qP+I3C kLggre4p9QR/3tOJfGoa/Y+jbTv3Bm4XMzso/jKLTzdOUjv7oU6w5KF2tHuZphZBX1l6 HJV+7Ijcr81ZvTUuJL7DF1JRm8uDV3QgrC3tIoaIw1HePOOqFac6mpKU+5PhbuLCGYEI pNmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=DNVFOwsoNzgnKbR7Mnu9AKsd+9PuR6uwgzj4ngGGq+U=; b=MYaK3xtFtJzZKw+lenZ3s/O/KPEXvv9eQ0GZ9ysFXWYimt3DvYlYcARZM4U+LwwDtw nF5uzTvXDJ68ZRi+/X6BTy2gUKQrnlI3vQmjDgR5fcyzcceUhISlWxPl/6dU9YHLfBYZ wHDAYcpXBQETAwKnnqLMLkdIzrpqaPUt+m+EqdzJ55QO298HZ4CsZguLFaAYNzAn/E+L hVt3bplotfvyeFIACokJDgyhljHOrklY1Bv8mnX3ublbVH9gTMyPVN41UCnPqhfVmbTz Opd5R5kigExWAw6GTrTx5qgsM+ZdxwAIdl5+9w33rao33YrShn0gvHTA0CaWKjPG8Bkx Pw7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NJr08u+t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:43 -0800 Message-Id: <20190211235258.542-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PATCH v3 13/28] target/arm: Implement the SUBP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Fix extraction length. --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 791bcc3b66..2339556320 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5139,19 +5139,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf = extract32(insn, 31, 1); + setflag = extract32(insn, 29, 1); rm = extract32(insn, 16, 5); opcode = extract32(insn, 10, 6); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - if (extract32(insn, 29, 1)) { + if (setflag && opcode != 0) { unallocated_encoding(s); return; } switch (opcode) { + case 0: /* SUBP(S) */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n = read_cpu_reg_sp(s, rn, true); + tcg_m = read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); + tcg_d = cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; From patchwork Mon Feb 11 23:52:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158054 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3214228jaa; Mon, 11 Feb 2019 16:12:36 -0800 (PST) X-Google-Smtp-Source: AHgI3Ibu32JV3l0dxmiuahSJWfgDvCq/nb3vfpZpUnrLyVQxS79Sj4vsvSj+Fcqd0lFfMKsmssOg X-Received: by 2002:a25:2102:: with SMTP id h2mr688408ybh.363.1549930356515; Mon, 11 Feb 2019 16:12:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930356; cv=none; d=google.com; s=arc-20160816; b=y9AvX1468GEDu9WybmDw3CDRD4JOoVuUmU8Mb8rXtPRMmwJWanlgINWahGhQutEsm6 Cx78kP0t1uDg3OdpkkRegkSpQ2/gofjvT2dRXeDXsCKDHwqjuSafjPP7Pz6hkjnrHTty 92QMW/4p5vemalADPcPZcbzukFEhtdRXEnOe+tNey/u3Cb2Am3gjTEVQCUe03j9GqNXF WDkS47fB7LfiuWKeoiqPeVUZox5RR745f+alhGRNuxqnongAvUpJcqmMOQFOLjCROkDk EOG0iqS20oXyfdj5tiYSgaJQVmgp4a3BeEtvAUA2MUC9svjiMRghzCyMSLe7XSNogRws rYiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AmqIDdbNf59JA1t3/NmXQ2mwEInbv+gIdpyKJXCMyoQ=; b=CGVIxmZXQFpPugIUwBozHSN+bCLxOyxdJW3GCmCGikg1rWnimdTXuzn7ZRF+8GPoNy TojLMNL2Ktk5jeyZ+h0I3p5TIXChNj2zX8zv/eD9SthSC6nFVAFN4gKYspHW3ioYRDxT nF2ChW472EDPzfxLRuNwIwEjrAW+9Q3FpJ8oRUMkkL/W2ba6E2rDaOnDTAlZ071rqbpD 8PWyJt/k8N2U/lTJSERyOKSg32zkz/sfS9u3ASBrh8xOILHSGy+94lg/BHlVF2X1AU3d PPutYSTzipEEi+A4UCRDps/6bQSijI0rVshVc4EvjBdBarTHHSw4+OXsHjWt4BOeE3FK C4JQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kpTRBcPR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:44 -0800 Message-Id: <20190211235258.542-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 14/28] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will need this to raise unaligned exceptions from user mode. Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) -- 2.17.2 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..d3cf362e4b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -87,8 +87,6 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, return val; } -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -179,6 +177,22 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, raise_exception(env, exc, syn, target_el); } +/* Raise a data fault alignment exception for the specified virtual address */ +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + ARMMMUFaultInfo fi = {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.type = ARMFault_Alignment; + deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); +} + +#ifndef CONFIG_USER_ONLY /* try to fill the TLB and return an exception if error. If retaddr is * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) @@ -200,21 +214,6 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, } } -/* Raise a data fault alignment exception for the specified virtual address */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - ARMCPU *cpu = ARM_CPU(cs); - ARMMMUFaultInfo fi = {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.type = ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); -} - /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort * exception From patchwork Mon Feb 11 23:52:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158043 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3203788jaa; Mon, 11 Feb 2019 16:00:41 -0800 (PST) X-Google-Smtp-Source: AHgI3Ibi0/DJ34zv9ayENCBfz0s81VGpDDyj8hMLhiWqd2DhjIObQQapkjYmQnyRgrQLUnJTVbUf X-Received: by 2002:a0d:efc2:: with SMTP id y185mr684078ywe.252.1549929641089; Mon, 11 Feb 2019 16:00:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929641; cv=none; d=google.com; s=arc-20160816; b=gEdMUQ4cSjPvw8SlbgNOMVLksxj0vs4O99Il6ufa4sZ1jvuPKtrBAf6wX//XASJ5cs oaFYpCMUurte1ZnUGMEgLsOSHoGg4PEvI9oCpXFxTq+2tJ0ROQEwZxvWaxQAlfdU+qzd eSzM0wOtdHSK2bCXoOT2RpGeAupdIwxmrOOMer9CZS++jkSpQyVg8bn8Ijs4r03g2Zl1 EgMowgwF97lwBDJ6ubzEEtVJ9K5OJ0aL/tS2Ozrv9e/I3/syKQZVd2YdhYu0tXeN1UFg Xx85rcEzM8nksJgsKH230uRR/EAmEbrPnQDwbofs9bSCESfda2CIh3/iRsPN74yG6jyR r6Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=fXIMbZNutQ7uXFr8eeZrKD7Mbf0VwPe0oJf0QZj17Fg=; b=CxTnl/ijEyTRPmlwvfUtSplWUgCGQymySnreo7v1mZZHdMFX4nuMKcA1YYa6/11Sb7 ZgZH1p78hCr/W1sFhhqzhK0VVUthLML7HBLfELPXddxhMEDTVNIxNWPMetr47aabGiGv OSSgfjQ27giRnQb9mHQXFIvueNUZTWHlSXF+IUMbUY8eOK9KbVDh0y6P/y6qjMtyLnTI iyGguxY2WKuvbT5EgWnBBgd2DhxEoY26JH/dK+AymrKNWR+mfxLYTCrnP9fM5yHYEEKO FhSkAoE0sh6tQrtJsnsHqP8Sc54bWZbbHZvfsOGOXTzgCikF3GBmPa68w7+Ss6epRqik xfPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jFCDe0as; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:45 -0800 Message-Id: <20190211235258.542-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 15/28] target/arm: Implement LDG, STG, ST2G instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Split out allocation_tag_mem. Handle atomicity of stores. v3: Add X[t] input to these insns; require pre-cleaned addresses. --- target/arm/helper-a64.h | 5 ++ target/arm/mte_helper.c | 151 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 115 ++++++++++++++++++++++++++++ 3 files changed, 271 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 3b78e19279..91e6a6ea94 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -109,3 +109,8 @@ DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e60c6f48eb..e8873f1e75 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,8 +25,21 @@ #include "exec/helper-proto.h" +static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, + bool write, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return NULL; +} + static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) { + uint8_t *mem = allocation_tag_mem(env, ptr, false, ra); + + if (mem) { + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + return extract32(atomic_read(mem), ofs, 4); + } /* Tag storage not implemented. */ return -1; } @@ -226,3 +239,141 @@ uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) int tag = allocation_tag_from_addr(ptr); return mask | (1ULL << tag); } + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + int el; + uint64_t sctlr; + int rtag; + + /* Trap if accessing an invalid page. */ + rtag = get_allocation_tag(env, ptr, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (rtag < 0 || !allocation_tag_access_enabled(env, el, sctlr)) { + rtag = 0; + } + + return address_with_allocation_tag(xt, rtag); +} + +static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { + arm_cpu_do_unaligned_access(ENV_GET_CPU(env), ptr, MMU_DATA_STORE, + cpu_mmu_index(env, false), ra); + g_assert_not_reached(); + } +} + +/* For use in a non-parallel context, store to the given nibble. */ +static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + uint8_t new = deposit32(old, ofs, 4, tag); + + atomic_set(mem, new); +} + +/* For use in a parallel context, atomically store to the given nibble. */ +static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + + while (1) { + uint8_t new = deposit32(old, ofs, 4, tag); + uint8_t cmp = atomic_cmpxchg(mem, old, new); + if (likely(cmp == old)) { + return; + } + old = cmp; + } +} + +typedef void stg_store1(uint64_t, uint8_t *, int); + +static void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int el; + uint64_t sctlr; + uint8_t *mem; + + check_tag_aligned(env, ptr, ra); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* Store if page supports tags and access is enabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (mem && allocation_tag_access_enabled(env, el, sctlr)) { + store1(ptr, mem, allocation_tag_from_addr(xt)); + } +} + +void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1_parallel); +} + +static void do_st2g(CPUARMState *env, uint64_t ptr1, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int el; + uint64_t ptr2, sctlr; + uint8_t *mem1, *mem2; + + check_tag_aligned(env, ptr1, ra); + ptr2 = ptr1 + TAG_GRANULE; + + /* Trap if accessing an invalid page(s). */ + mem1 = mem2 = allocation_tag_mem(env, ptr1, true, ra); + if (unlikely((ptr1 ^ ptr2) & TARGET_PAGE_MASK)) { + /* The two stores are across two pages. */ + mem2 = allocation_tag_mem(env, ptr2, true, ra); + } + + /* Store if page supports tags and access is enabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if ((mem1 || mem2) && allocation_tag_access_enabled(env, el, sctlr)) { + int tag = allocation_tag_from_addr(xt); + + if (likely(mem1 == mem2)) { + /* The two stores are aligned 32, and modify one byte. */ + tag |= tag << 4; + atomic_set(mem1, tag); + } else { + /* The two stores are unaligned and modify two bytes. */ + if (mem1) { + store1(ptr1, mem1, tag); + } + if (mem2) { + store1(ptr2, mem2, tag); + } + } + } +} + +void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2339556320..feed325083 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3610,6 +3610,118 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } } +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 = extract32(insn, 10, 3); + int op1 = extract32(insn, 22, 2); + bool is_load = false, is_pair = false, is_zero = false; + int index = 0; + TCGv_i64 dirty_addr, clean_addr, tcg_rt; + + if ((insn & 0xff200000) != 0xd9200000 + || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + switch (op1) { + case 0: /* STG */ + if (op2 != 0) { + /* STG */ + index = op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 != 0) { + /* STZG */ + is_zero = true; + index = op2 - 2; + } else { + /* LDG */ + is_load = true; + } + break; + case 2: + if (op2 != 0) { + /* ST2G */ + is_pair = true; + index = op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 != 0) { + /* STZ2G */ + is_pair = is_zero = true; + index = op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + dirty_addr = read_cpu_reg_sp(s, rn, true); + if (index <= 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + + clean_addr = clean_data_tbi(s, dirty_addr, false); + tcg_rt = cpu_reg(s, rt); + + if (is_load) { + gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rt); + } + } else { + if (is_pair) { + gen_helper_st2g(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stg(cpu_env, clean_addr, tcg_rt); + } + } + + if (is_zero) { + TCGv_i64 tcg_zero = tcg_const_i64(0); + int mem_index = get_mem_index(s); + int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; + + for (i = 0; i < n; i += 8) { + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + tcg_temp_free_i64(tcg_zero); + } + + if (index != 0) { + /* pre-index or post-index */ + if (index > 0) { + /* post-index */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3634,6 +3746,9 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* Load/store tag */ + disas_ldst_tag(s, insn); + break; default: unallocated_encoding(s); break; From patchwork Mon Feb 11 23:52:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158037 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3201563jaa; Mon, 11 Feb 2019 15:57:43 -0800 (PST) X-Google-Smtp-Source: AHgI3IYGXFaHmfHQC7qPnmCRSKQmX8evsJX3/d4up8IpMiO8X8kvUhwPHZZgKBh2vkQIbhTAzRAr X-Received: by 2002:a81:7102:: with SMTP id m2mr626002ywc.235.1549929463148; Mon, 11 Feb 2019 15:57:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929463; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:46 -0800 Message-Id: <20190211235258.542-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 16/28] target/arm: Implement the STGP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v3: Handle atomicity, require pre-cleaned address. --- target/arm/translate-a64.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index feed325083..ef3fc3a397 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2708,7 +2708,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2733,6 +2733,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) bool is_signed = false; bool postindex = false; bool wback = false; + bool set_tag = false; TCGv_i64 clean_addr, dirty_addr; @@ -2745,6 +2746,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (is_vector) { size = 2 + opc; + } else if (opc == 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { + unallocated_encoding(s); + return; + } + size = 3; + set_tag = true; } else { size = 2 + extract32(opc, 1, 1); is_signed = extract32(opc, 0, 1); @@ -2797,6 +2806,15 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) } clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); + if (set_tag) { + TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); + if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rn); + } else { + gen_helper_stg(cpu_env, clean_addr, tcg_rn); + } + } + if (is_vector) { if (is_load) { do_fp_ld(s, rt, clean_addr, size); From patchwork Mon Feb 11 23:52:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158049 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3209356jaa; Mon, 11 Feb 2019 16:06:28 -0800 (PST) X-Google-Smtp-Source: AHgI3IYkQI9fp4h2tJezeiXAIQqVbU2dzzeXs741dntXxapmu5qJn1TYPQBisWyL2TOMgdsrjJPP X-Received: by 2002:a81:ae61:: with SMTP id g33mr715826ywk.220.1549929988129; Mon, 11 Feb 2019 16:06:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929988; cv=none; d=google.com; s=arc-20160816; b=wIZ/9H+nGdRVQFoCD541DsTqwqqgwFp+im0rRDjgYZt0nXE+e4lxR/KtrnxuuxecDa aEPDog4iDN0tcfi7hWqg7BroxGU210K5zgbV/AcfMnkK4Q7/EbENgUcRsL40pfGsadOd 4ROhBJxgWSY04k9rmwPQvV7lSor9PfKH/X8rI05X/sUxcmvTYJKlHJCZFNUMJumkY665 t0rYhp+NrUP3Otj+aq69XvntKK8xf2dTnmEWZo5rcTNKND6++AvbZD175XfRicrqW9DS aeQ5VGxUta+8YNAX4oKYLGBn2rqac/ZOF4KkJMo9Ynw/TlzgfYC9oUY3ABVVjKvGJJqn cSeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=uWHLuK9tuxKWuI11A7yFd0AHF+W16hGm0E91RHeIwSc=; b=ek/9ZBNEiXn8wbBSxT7WD9VUTpY0pKDqBfhOmkWJyizPtdNU53AbC5UtoxZf2f9iJ/ uClNt9QZ5d87te2RaIUlAwGP3udV142ATI1zxVxjaJFnupH29vNTMbcrvg+mvq9TZHFp TgpFt+J9jfPEXFL2ELPms4o2W6Mpofx2m0s9mvKKlbq60jUMBH7SnJEl2AIzhaFqSIaW et8yVc/umKFdzsYKNclQbM1C0g7UI5UM+/BB7ebuhc6tfb33AxgBD/G6Sn3ea4C9vUQC 8zSrasdWAPeGJUR3YL2jTsUUgfhTXaCo1RFOoCOYhrBWh0fOR8nDr6eNB3cUcP/shv5G +bVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TeDWiBmg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:47 -0800 Message-Id: <20190211235258.542-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 17/28] target/arm: Implement the LDGM and STGM instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v3: Require pre-cleaned addresses. --- target/arm/helper-a64.h | 3 ++ target/arm/mte_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 42 +++++++++++++---- 3 files changed, 132 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 91e6a6ea94..5bcdfcf81b 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -114,3 +114,6 @@ DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e8873f1e75..afa4c26535 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -377,3 +377,99 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) { do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); } + +uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, false, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return 0; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are loading 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + return ldq_le_p(mem); +} + +static uint64_t do_stgm(CPUARMState *env, uint64_t ptr, + uint64_t val, uintptr_t ra) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* + * No action if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return ptr; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are storing 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + stq_le_p(mem, val); + + return ptr; +} + +void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + do_stgm(env, ptr, val, GETPC()); +} + +void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + int i, mmu_idx, size = 4 << GMID_EL1_BS; + uintptr_t ra = GETPC(); + void *mem; + + ptr = do_stgm(env, ptr, val, ra); + + /* + * We will have just probed this virtual address in do_stgm. + * If the tlb_vaddr_to_host fails, then the memory is not ram, + * or is monitored in some other way. Fall back to stores. + */ + mmu_idx = cpu_mmu_index(env, false); + mem = tlb_vaddr_to_host(env, ptr, MMU_DATA_STORE, mmu_idx); + if (mem) { + memset(mem, 0, size); + } else { + for (i = 0; i < size; i += 8) { + cpu_stq_data_ra(env, ptr + i, 0, ra); + } + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ef3fc3a397..b97af372f0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3643,7 +3643,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; int op2 = extract32(insn, 10, 3); int op1 = extract32(insn, 22, 2); - bool is_load = false, is_pair = false, is_zero = false; + bool is_load = false, is_pair = false, is_zero = false, is_mult = false; int index = 0; TCGv_i64 dirty_addr, clean_addr, tcg_rt; @@ -3653,13 +3653,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) } switch (op1) { - case 0: /* STG */ + case 0: if (op2 != 0) { /* STG */ index = op2 - 2; - break; + } else { + /* STZGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_zero = true; } - goto do_unallocated; + break; case 1: if (op2 != 0) { /* STZG */ @@ -3675,17 +3680,27 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) /* ST2G */ is_pair = true; index = op2 - 2; - break; + } else { + /* STGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = true; } - goto do_unallocated; + break; case 3: if (op2 != 0) { /* STZ2G */ is_pair = is_zero = true; index = op2 - 2; - break; + } else { + /* LDGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_load = true; } - goto do_unallocated; + break; default: do_unallocated: @@ -3702,7 +3717,16 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) clean_addr = clean_data_tbi(s, dirty_addr, false); tcg_rt = cpu_reg(s, rt); - if (is_load) { + if (is_mult) { + if (is_load) { + gen_helper_ldgm(tcg_rt, cpu_env, clean_addr); + } else if (is_zero) { + gen_helper_stzgm(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stgm(cpu_env, clean_addr, tcg_rt); + } + return; + } else if (is_load) { gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (is_pair) { From patchwork Mon Feb 11 23:52:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158048 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3209163jaa; Mon, 11 Feb 2019 16:06:14 -0800 (PST) X-Google-Smtp-Source: AHgI3IaFOlUhnoOK+TtyTptd/dExykn8whiTpanNwkvvgwL2R8dIouiCzl1ur6mWx0Fhe6cjMHpB X-Received: by 2002:a25:48a:: with SMTP id 132mr664705ybe.305.1549929974877; Mon, 11 Feb 2019 16:06:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929974; cv=none; d=google.com; s=arc-20160816; b=DzN/eSnmys4ctbrFLdcS021gjPK6ugEGnuIPkFbBsTq0QyAHHtwlou9lpkJVZ4bmOr OmpgJbZLkG3bmpVCVXgAvPtFL6kktrZTJHBf9kcWKqw5quEgy3qxfK2mU5kMgsT75jWD Ofnm3DCiAvJj2fGmNvH4XoeunkXpKN88imdsC4kHtiakcASNxOV/DzonJuHh478dngKj IH88SvSwDTDr3HBfAPUuiDKUt1yoidgJ9nA10RbG90Ystbh7cHFz6iI1Ak7O/QoXvwxe g5OLdZJh4ChWIJz7Fqg0iLc8Bt84X/X3Cv9OOrSr5CGkpIz1tubz2o+WVO99e46y/RqU KMmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U/D4l6oEbeVfp8+t8gRAbmKwAQMWeg+He9HLmsCdEd8=; b=JfOuKbWRfzpgqsZHWeNWPB0DPYVWx1tXwgeV1xI4yzvApw8hfAcowpWGbPWPMiXIx2 iP8fe+5VT2iRo2DRulisx+katuZhcGP2wn6icQixLAHbdafUrfq2GMnlcfJ4s3Mp3/zF CuXSvloN0iLc/uCy+kxOscfMJ6apArA1hTKQCWm2UGaPrBrozQPKicYJ9q1VnZWTnnUj 2Opjg6eBOZ77Rarnh3PnF1GJn4omrvt+0ljWpMqD5GhJnBq7vjD8+T+i8CmsGiRYf+k0 M1TAKG0V5IYz6IF8Qkq0L9eG0BOFJMFAEst5UOG4wTulWCLzoK0POFUpkcxMyR0iIU5R ybJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yXtHJj9A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:48 -0800 Message-Id: <20190211235258.542-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Like the regular data cache flushes, these are nops within qemu. Signed-off-by: Richard Henderson --- target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index f8e4e6f8ae..ed1b258497 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5793,6 +5793,54 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + { .name = "IGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, REGINFO_SENTINEL }; #endif From patchwork Mon Feb 11 23:52:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158035 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3199517jaa; Mon, 11 Feb 2019 15:54:35 -0800 (PST) X-Google-Smtp-Source: AHgI3IZoqNqgQZJDxZvxn6F+jxfZ1mubvZKorMdebnN/JD8gMd08l9Umk0IBfBiny3XJbeIaIgnC X-Received: by 2002:a25:3457:: with SMTP id b84mr657047yba.154.1549929275637; Mon, 11 Feb 2019 15:54:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929275; cv=none; d=google.com; s=arc-20160816; b=IfH98K7Nx5f72Ef8O7f+WDZpahGm+M5xEBdau2HdOx3HVq9Qfo2jU+Z/CuuaQDxo5D LaInffUb/anQ4Q/YKeY/qAdZkB+BDugqs3WmCvQ8slDdjaeim3byli39kWP84eay8p4T N2PfUMcv6t7Zk8Ox607/DniR/05Xd36XHJZGnruO56PAT+9otR1KcFlMq9xf0OwIY9CZ oCaksEku0fnfRPNheLm39tXvjBe/8t/oUuUzou4DakhLCI7eaGpEqYZmotd2y2wJtM8l DOKBF1MF67Xw9ibkGI0OvpCdi3rlq4/7nNWWanTnk9Csva0yAaBRAJnkywaGKtIj22Kc nLhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CY+4xvY3XNlng3h4IyHhGPUmeyAfX1LC7tzqEoCASgM=; b=ghPSPHRDL8eWy1MJXE/SInJT8OBt63+OHDW+DBjI8uaYrXyHxMximCMuiAQ7zDIzs+ bZ8Gj6PRvT+tB9F7COrgjoSaEPgEAd/doFgf+QA5Qs6YMaJ/xny63em4w++lr5RbkX3x /JhpE8yMROhXCoMUcU46qlkKi+3WVrG0Sry0Rty6ONCUG/u032qFRgKOGxAO4h6bK2DW iZ504/+kV/LRO4nLfvASo2s4fc4EY87Wm8zc6dcLV9aZTcZgbPY6JWmHj8kuCvqJ3GEm f49WeXHtMGaMwArpT6dGwd8hz2IkG4R8W2PNYtXmODJgEtYJ96ynNqXqV/5kOcdSGGAA 3n8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RwX2IXIE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:49 -0800 Message-Id: <20190211235258.542-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v3 19/28] target/arm: Clean address for DC ZVA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data access was forgotten in the previous patch. Fixes: 3a471103ac1823ba Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b97af372f0..9e7afa571d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1815,7 +1815,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ - tcg_rt = cpu_reg(s, rt); + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); gen_helper_dc_zva(cpu_env, tcg_rt); return; default: From patchwork Mon Feb 11 23:52:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158053 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3212336jaa; Mon, 11 Feb 2019 16:10:00 -0800 (PST) X-Google-Smtp-Source: AHgI3IbgWY+i/0/bt4SRX4REUfEE0wZrHolJ40swP2IuWBs6a0t2p/wSvSInR/sZHHDl3fdJrMEi X-Received: by 2002:a25:258f:: with SMTP id l137mr694324ybl.416.1549930200559; Mon, 11 Feb 2019 16:10:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930200; cv=none; d=google.com; s=arc-20160816; b=He/iF6Mfiu0LIJQcmz7ZTlZExfoFKHL0DPBJI2tpHaB13tPs7cSrbyVxFGhvkNeXWP LYRBhTPUSSwJuaRbf25WqHUIEq8Mg08+A+aHC0YkRBF4udSvdxNqZiCVowVqEACrdI5I cDzARkeesefuFqwunrXsmZ2BXMuDzpcBON39Jy/gRvCMN7pA2G2gyjLopzHTFoZuEefc zETwfnhcZU57P89WvubkXSSwU/CLfOK1qdZva7WyTIaSkmvPQpDJ3hYqSep9/z28rmGY zasU1PgaJ2C9eFpyCnc3NZrNeKNpVL3ghHfLmcgeBlXUB3hl+O7mDq8Em9B1wn7vh+H0 X2mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=u1cP8m0OoSVsqCjKblIhCfU4wnhzJWGLVFK+17Qjpco=; b=dQP5g2k7biQHXniadH3NgNUfwxj8uLaQiuEZOR+YTIG9WCBBtSVqb/atYpWxnhZSsB f5EK1uDaKGOJYF1IZ0/DniZPNshCkudJ+VCY9o2fQU5aXAU+2xnD5kzDE79PfxZTlkDH 1h9HUk6xk3ed8EwfN5vYfckOTGLkk04tt433KgCcMZo8kL8EESqGm9q+4Yrk8gqQ5Wwo y6eIvk0zAtzG62xQIdg+ZL8c0sA2i1sIlPDVSPHxIdmxxXPdtRNIWhXA2gCXdu+r6z8t h4GnjoZQUT8h1kKCRXiXTwHPa2zbw99GwpSwJ4Z+2+CKoy89XdNBGKqnPnFhyKM8FA3Z Fgaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ljZlRPnZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:50 -0800 Message-Id: <20190211235258.542-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 20/28] target/arm: Implement data cache set allocation tags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is DC GVA and DC GZVA. Signed-off-by: Richard Henderson --- v2: Use allocation_tag_mem + memset. v3: Require pre-cleaned addresses. --- target/arm/cpu.h | 4 +++- target/arm/helper-a64.h | 1 + target/arm/helper.c | 16 ++++++++++++++++ target/arm/mte_helper.c | 28 ++++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++++ 5 files changed, 57 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 74633a7a78..ca32939483 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2160,7 +2160,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 5bcdfcf81b..ec4e7f7cf5 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -117,3 +117,4 @@ DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(dc_gva, TCG_CALL_NO_RWG, void, env, i64) diff --git a/target/arm/helper.c b/target/arm/helper.c index ed1b258497..f17e045706 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5841,6 +5841,22 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "GVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, + .access = PL0_W, .type = ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, + { .name = "GZVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, + .access = PL0_W, .type = ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index afa4c26535..6d0f82eb99 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -473,3 +473,31 @@ void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) } } } + +void HELPER(dc_gva)(CPUARMState *env, uint64_t ptr) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + size_t blocklen = 4 << cpu->dcz_blocksize; + int el; + uint64_t sctlr; + uint8_t *mem; + int rtag; + + ptr = QEMU_ALIGN_DOWN(ptr, blocklen); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, GETPC()); + + /* No action if page does not support tags, or if access is disabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag = allocation_tag_from_addr(ptr); + rtag |= rtag << 4; + + assert(QEMU_IS_ALIGNED(blocklen, 2 * TAG_GRANULE)); + memset(mem, rtag, blocklen / (2 * TAG_GRANULE)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9e7afa571d..1bab7ea211 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1818,6 +1818,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; + case ARM_CP_DC_GZVA: + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); + gen_helper_dc_zva(cpu_env, tcg_rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; default: break; } From patchwork Mon Feb 11 23:52:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158050 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3209993jaa; Mon, 11 Feb 2019 16:07:08 -0800 (PST) X-Google-Smtp-Source: AHgI3IbWbUAegHO+zAQcTBKMAEQqrADLNI7mNnDTxWRTfoOvsjNjtT4k5NcPKdVxnRW2UdoJmpLW X-Received: by 2002:a81:b189:: with SMTP id p131mr674152ywh.92.1549930028604; Mon, 11 Feb 2019 16:07:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930028; cv=none; d=google.com; s=arc-20160816; b=uRgfgHraKLgjI2xwUkBP7muEkxECE+Ana+VfSwPazeKRKCwMgnDS7VDhQGnsxqSWBL tMbJ532BMn/d9QP9XBV3y3sRYc4J0A7rc2ywVmwZqDSK1uPo6Yw8L98lBr0WW7nh998/ oi8ryd/tZMatYmI1R5Mq7AvIlXBdz6GTjV2Dy53G0lf9szfGIe7YKkVbFstpbaCqAPOf QPBGdfC6oK/qyKW66tU1bllXakHrvZ//M84rLaYjqGe7V/A15/wsfmlx9U9Ecy2rzK/t pDX1DPdJW+o4KMdBBkMrFFdyG0sprQExRJ2cBS6muAoczbgacWc9CrZg+NdnMKNT0ggg Ri/g== ARC-Message-Signature: i=1; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:51 -0800 Message-Id: <20190211235258.542-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH v3 21/28] target/arm: Set PSTATE.TCO on exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0085 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Only set if MTE feature present. --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index f17e045706..b979ca0255 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9476,6 +9476,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int cur_el = arm_current_el(env); + unsigned int new_pstate; /* * Note that new_el can never be 0. If cur_el is 0, then @@ -9569,7 +9570,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); - pstate_write(env, PSTATE_DAIF | new_mode); + new_pstate = new_mode | PSTATE_DAIF; + if (cpu_isar_feature(aa64_mte, cpu)) { + new_pstate |= PSTATE_TCO; + } + pstate_write(env, new_pstate); env->aarch64 = 1; aarch64_restore_sp(env, new_el); From patchwork Mon Feb 11 23:52:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158058 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3216277jaa; Mon, 11 Feb 2019 16:15:17 -0800 (PST) X-Google-Smtp-Source: AHgI3IYgkatSTYPdaP+R5AKIGNrho0maXeJBAR4vt29DGDMv7WGYjvRYn2GSGe86f3Iph0v3zs1n X-Received: by 2002:a81:20c6:: with SMTP id g189mr707179ywg.284.1549930517810; Mon, 11 Feb 2019 16:15:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930517; cv=none; d=google.com; s=arc-20160816; b=KphjmFiUolft+hTZHahc/a5HvoSZ/LRbFrKnuybAJheHtxzxKX6XL3LDgEbolUjlyH 26deEkA73RjnGgGBuTprctHOPDoD7DAOfwkqDg6uV+LdtUYMuXFcAqjVtr1IVzU4vwQh cJtqGqv9CoUVxwZWkWJpUtbKEG4mEvKlCGBy2EvOlh165N8RmQ3f9X0AlLxT8SGM41d/ WHtUboSMLdznGpGVl75TGr6XePpeQ5g7q96mZjkXSPeaDp/susnWq54z02m/FC6EJiga 9YuKkvMFtPufCdN3cZ1fjJGgBCIuHmW9cSl7JsAfQup+NsNmWRT7mMfmBHuIKawJF/i3 uZiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IYfDmawl379GZgWCUsgON1GHK8BY9wa/LpINsjn/HBc=; b=PctymgRvD9grgFujZvAH3XSRkYSkUlfHs7DwGdhdxML+KvjWaKJLRbpITuNBBJG1n4 QiJkU23WxR0L73/mQp7PjUjdiLNP54ipjcISKIORzqlDaqu7Md+H5FDLvoC0VKkPP3C7 lFxefLHQ9/5pY9uq9/VKmVnTmiI9X2ZzA0yITjHgyPvU4gldZa/7uazdjdezfV6H7r7+ +uIbTQ5G738WGnInl11VZAiCuaRB6/lPPZN5MxEny3t2JV+pwRFRRrfBVoZiKAJhIW9g C6YjFK9rdWYBNGNO5FuJ92OWNEdauZPM9Smh5kFHcQWc15ESEOQ/46U3o0bMS9WiGdVB eUDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jiVgBVN1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:52 -0800 Message-Id: <20190211235258.542-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 22/28] tcg: Introduce target-specific page data for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, remember MAP_SHARED as PAGE_SHARED. When mapping new pages, make sure that old target-specific page data is removed. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 10 ++++++++-- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++++ linux-user/mmap.c | 10 ++++++++-- linux-user/syscall.c | 4 ++-- 4 files changed, 46 insertions(+), 6 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b16c9ec513..e88ecad0b3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -244,10 +244,14 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_ORG 0x0010 /* Invalidate the TLB entry immediately, helpful for s390x * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ -#define PAGE_WRITE_INV 0x0040 +#define PAGE_WRITE_INV 0x0020 +/* Page is mapped shared. */ +#define PAGE_SHARED 0x0040 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif #if defined(CONFIG_USER_ONLY) @@ -260,6 +264,8 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); +void *page_get_target_data(target_ulong address); +void *page_alloc_target_data(target_ulong address, size_t size); #endif CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8f593b926f..6cc266428d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -107,6 +107,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2476,6 +2477,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2492,6 +2494,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) if (flags & PAGE_WRITE) { flags |= PAGE_WRITE_ORG; } + reset_target_data = !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &= ~PAGE_RESET; for (addr = start, len = end - start; len != 0; @@ -2505,10 +2509,34 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data = NULL; + } p->flags = flags; } } +void *page_get_target_data(target_ulong address) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + void *ret = NULL; + + if (p) { + ret = p->target_data; + if (!ret && (p->flags & PAGE_VALID)) { + p->target_data = ret = g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index e0249efe4f..0b786b87a2 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -562,7 +562,11 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, } } the_end1: - page_set_flags(start, start + len, prot | PAGE_VALID); + if ((flags & MAP_TYPE) == MAP_SHARED) { + prot |= PAGE_SHARED; + } + prot |= PAGE_RESET | PAGE_VALID; + page_set_flags(start, start + len, prot); the_end: #ifdef DEBUG_MMAP printf("ret=0x" TARGET_ABI_FMT_lx "\n", start); @@ -754,9 +758,11 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = -1; } else { new_addr = h2g(host_addr); + /* FIXME: Move page flags (and target_data?) for each page. */ prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5bbb72f3d5..9d89b40321 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3884,8 +3884,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_env, raddr=h2g((unsigned long)host_raddr); page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_SHARED | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); for (i = 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { From patchwork Mon Feb 11 23:52:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158046 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3206933jaa; Mon, 11 Feb 2019 16:03:51 -0800 (PST) X-Google-Smtp-Source: AHgI3IauFeWso8DIecaFcegbNC5w5FOAnTMLKe79F+CfDk5VtcLNc6PJU00ZNugtwpKjyT4NnZhv X-Received: by 2002:a25:7056:: with SMTP id l83mr638994ybc.189.1549929831445; Mon, 11 Feb 2019 16:03:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549929831; cv=none; d=google.com; s=arc-20160816; b=gfcbDxcCFGMGehWkFN6ttg85hbXwmow17UmPEmto1ISo/SqR14NtXkQzXtnzqHs13K j/w5I/tyO5Dk+bjCfkuDA1+YkwQlEi7oITdo0gN7YxxDr5iEiDqAlI+N00x+dn2ko192 5ywOjRu/g3+FJVeppIFn20z3qd+dyM/X6WNHfexv5+0zRYYmnigebYVLt5W/hkFLx0nA 2LJczNz/TT1ooeo1CVk/tx0A9ABWYWrL7vNcThohj0p+jFfTuNWThoI6e+npPrqV9pM4 m3+UZUb/hb97LGNXRPmijkG5Ao1VOGxut4LrmSFipUMME+fkgUnz4xidIsbsLUO8Xfm2 WuHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=+Gn6j+ksJBWpAxFZK52yAjwPBXTbbLVYAigRV7FM7Ok=; b=c3pzmSr7/3rtMo2HbjWDji/AFYGHCbduV/rznwhBrW6MZm/ruBgfGVzW1E4I0AuOSR l9apIAEl2CGSs0qMPIoGTaevpoiugw3lsAoAPbLhETnRNAjZRcEr9HByFg0uOutt8x4z QMbPvhujpXMLHxQEikyds5nk0IT/KZ3ZRtEJPgHOe+MU3/XHVYF7+Sk6JDxpykCjKtzg ib+YwdqMNwqVdwB4EuRc2dJoDO227qgu9WW25o7OnFXoChNFiua0ubI8F1UV6Ki/2s/C HGGoFLkwYOLPpTisEkFJcxZk+ZJC2dkHx0PylhkY0NVLx8W4MY0XsSBu0PGdD1CMrCTB pseg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ac8DMoMC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:53 -0800 Message-Id: <20190211235258.542-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index b979ca0255..e312d62140 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10740,6 +10740,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; + uint8_t memattr; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10970,17 +10971,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, txattrs->target_tlb_bit0 = true; } + if (mmu_idx == ARMMMUIdx_S2NS) { + memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint64_t mair = env->cp15.mair_el[el]; + memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8); + } + + /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */ + if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) { + txattrs->target_tlb_bit1 = true; + } + if (cacheattrs != NULL) { - if (mmu_idx == ARMMMUIdx_S2NS) { - cacheattrs->attrs = convert_stage2_attrs(env, - extract32(attrs, 0, 4)); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 0, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); - } + cacheattrs->attrs = memattr; cacheattrs->shareability = extract32(attrs, 6, 2); } From patchwork Mon Feb 11 23:52:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158060 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3218389jaa; Mon, 11 Feb 2019 16:18:11 -0800 (PST) X-Google-Smtp-Source: AHgI3IZKFl+TFug6sQjZgyueCU5HLd5q/zSljPjhow7l0LeSafy4nsqpYp+fOApR4e5dJV5Yme8U X-Received: by 2002:a0d:c5c2:: with SMTP id h185mr733128ywd.26.1549930691379; Mon, 11 Feb 2019 16:18:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930691; cv=none; d=google.com; s=arc-20160816; b=DtZtjUqeBYoOD7w0Tv8j4anhvGcNoY3Q6Skhz7PykU2YPIyGZKbB4KFgw416S2MO2Q TsBfch8i7e/0ycFWdc2MBpnIXjNMAUhPu4IM+1lnDl19DkCdWz0yLgkCK+0mNUfOWc4z oJMYCJFBB6Q4vbfZe4S4Fr6l9/f/JBPspQy0DJm7LYtzDsX9gi9JF39mTS8QGhbPS33R WKRe8GYlNfrSOAxLwFQnkCeW21BVolvGD1GrstO4HYT2WQIR54TCXlgNTSSbQfcbNQM2 NuehjCnEo4aLgJZfO8cPfXeC9++bu2VHf2m3QrydXxMxd6KKqxZCJXeJL2TQW3IAqgle hSuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=A8TAMIXN+69/Jk9cvH3CNk1W0843jdUBpea8zUdjfM0=; b=oya2fvQV/PkwtVEh8sm9tV9Cup3Wvf581ufNWxqk72QSh9Z/YSYYQP+bd40ZHBIAMb 88okskhVu1DM5hQSTX9hAzcw83UA2bmJINV6W4kRM+oNyFr+7ajXbnfHwEpG7zcgban2 ljRZRoBua4GanGXG2NoxJjve9ueLxlNQHWKLInU/4ybh+1U6dL2hwfKOs7DLYgf/POQh poz57gHL6eGUDAhruTG1Ay2tO+VK+RxAef6/aYyIIVoqditgnOm/LJCQdxgVen0y/l4s wuDnN+c/AKWCDZJCayDpisQHbE98K2ucGADkKnsM/ghw4qk9D81lr1KNrL0dEaoWxIgh G+hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tA0F2DP7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:54 -0800 Message-Id: <20190211235258.542-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 24/28] target/arm: Create tagged ram when MTE is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ target/arm/cpu.c | 21 ++++++++++++++++++--- 3 files changed, 55 insertions(+), 3 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca32939483..2626af4a9c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -768,6 +768,9 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; @@ -2850,6 +2853,7 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch); typedef enum ARMASIdx { ARMASIdx_NS = 0, ARMASIdx_S = 1, + ARMASIdx_TAG = 2, } ARMASIdx; /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d..dccd1345a1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1260,6 +1260,21 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } +static void create_tag_ram(VirtMachineState *vms, MachineState *machine, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *tagram = g_new(MemoryRegion, 1); + hwaddr base = vms->memmap[VIRT_MEM].base / 32; + hwaddr size = machine->ram_size / 32; + + memory_region_init_ram(tagram, NULL, "mach-virt.tag", size, &error_fatal); + memory_region_add_subregion(tag_sysmem, base, tagram); + + /* ??? Do we really need an fdt entry, or is MemTag enabled sufficient. */ + /* ??? We appear to need secure tag mem to go with secure mem. */ + /* ??? Does that imply we need a fourth address space? */ +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board = container_of(binfo, VirtMachineState, @@ -1362,6 +1377,7 @@ static void machvirt_init(MachineState *machine) qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *secure_sysmem = NULL; + MemoryRegion *tag_sysmem = NULL; int n, virt_max_cpus; MemoryRegion *ram = g_new(MemoryRegion, 1); bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); @@ -1518,6 +1534,20 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } + /* + * The cpu adds the property iff MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem = g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + } + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + } + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } @@ -1540,6 +1570,9 @@ static void machvirt_init(MachineState *machine) create_secure_ram(vms, secure_sysmem); create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } + if (tag_sysmem) { + create_tag_ram(vms, machine, tag_sysmem); + } vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..decf95de3e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -851,6 +851,18 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); + } +#endif } static void arm_cpu_finalizefn(Object *obj) @@ -1164,16 +1176,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) init_cpreg_list(cpu); #ifndef CONFIG_USER_ONLY + cs->num_ases = 1; if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { cs->num_ases = 2; - if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases = 1; + } + if (cpu->tag_memory != NULL) { + cs->num_ases = 3; + cpu_address_space_init(cs, ARMASIdx_TAG, "cpu-tag-memory", + cpu->tag_memory); } cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); From patchwork Mon Feb 11 23:52:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158057 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3215414jaa; Mon, 11 Feb 2019 16:14:18 -0800 (PST) X-Google-Smtp-Source: AHgI3IaQezS+ln6NIlqj9dyFdKGAIq8wg2oKe3bqXJLRlxcyosID2Y1j/YtDj71F0/TTmFHAfBO8 X-Received: by 2002:a81:99c7:: with SMTP id q190mr695817ywg.398.1549930458515; Mon, 11 Feb 2019 16:14:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930458; cv=none; d=google.com; s=arc-20160816; b=uzAgCTi4nxyLxqBHOuyqrheZLmGXHGw1M3Jzs4TLi9rM5u0ZIQeJTkaO3+4EsbD3xg kf0Q6gL9UEssdgAV2VW9Sg4XSvMchvQSUz+8yL6bTzmPecCuLAiUPJQIndL6FraLcVZk KCQGkrZODOBNbbk2EhFbAgrD3A9VOBZO6ApsuNGxlvIdZfSOMdKxF+v8yxLjOxygghom Xu8daf/PiTzbFoO/4UoerXJoqmooMUdNcgTlnB0ngtOl0+aqYQpv3DFl0A/eBAg3xYfq tk9Xzo7LKwrPPbsC9Dru0eZafE0WcfIIC6Lq7BEZw1c6zWGr2OylEePhBsEp+AOjy7Tv Sfnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ah6gpD+An0QDDQ04ODgwPJ8bm3GJsZDkKDcKBtcRmis=; b=FI7tWL+hD8C+mcODKwbt95BuaYOsyxUUxBniI+fdmiZ8hrlS6OmlK4PHLHdhPQkbn6 8v6pp4tysM+oOWTx9jcsDRbb1ym8QNheZHUxBrH/PCkQR0dwQnA1mu0ve/7ZZCMiZDm7 Z/NuD6iCPLWUAnFAnCJpbF7KxvdT0N0ss0qG9NmEls6Di6XUvb2H25SNZLmVS7/5JYB0 4Sd3VGlzrOYaQBg/WKF0I3Nj0Loe5o58APqwJW2diDgRstodANEC8bYeYLIcHsViHchj OnhihSbKYM8UnGpLxzwLjIL52FK0CmpFUZMr9Gjs6y6EQrUk7OjFKWp+sl3jJn39tec7 g+9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ixi4F8QJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:55 -0800 Message-Id: <20190211235258.542-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 25/28] target/arm: Add allocation tag storage for user mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Control this with x-tagged-pages, which is off by default. The limitation to non-shared pages is not part of a future kernel API, but a limitation of linux-user not being able to map virtual pages back to physical pages. Signed-off-by: Richard Henderson --- v2: Add the x-tagged-pages cpu property --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 18 ++++++++++++++++++ target/arm/mte_helper.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2626af4a9c..ec5ddfbacc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -910,6 +910,7 @@ struct ARMCPU { #ifdef CONFIG_USER_ONLY bool guarded_pages; + bool tagged_pages; #endif QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c5675fe7d1..53a7d92c95 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -293,6 +293,18 @@ static void aarch64_cpu_set_guarded_pages(Object *obj, bool val, Error **errp) ARMCPU *cpu = ARM_CPU(obj); cpu->guarded_pages = val; } + +static bool aarch64_cpu_get_tagged_pages(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu->tagged_pages; +} + +static void aarch64_cpu_set_tagged_pages(Object *obj, bool val, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + cpu->tagged_pages = val; +} #endif /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); @@ -380,6 +392,12 @@ static void aarch64_max_initfn(Object *obj) aarch64_cpu_set_guarded_pages, NULL); object_property_set_description(obj, "x-guarded-pages", "Set on/off GuardPage bit for all pages", NULL); + + object_property_add_bool(obj, "x-tagged-pages", + aarch64_cpu_get_tagged_pages, + aarch64_cpu_set_tagged_pages, NULL); + object_property_set_description(obj, "x-tagged-pages", + "Set on/off MemAttr Tagged for all pages", NULL); #endif cpu->sve_max_vq = ARM_MAX_VQ; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 6d0f82eb99..09c387e2c7 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -28,8 +28,44 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + ARMCPU *cpu = arm_env_get_cpu(env); + uint8_t *tags; + uintptr_t index; + int flags; + + flags = page_get_flags(ptr); + + if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ))) { + /* SIGSEGV */ + env->exception.vaddress = ptr; + cpu_restore_state(CPU(cpu), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + + if (!cpu->tagged_pages) { + /* Tag storage is disabled. */ + return NULL; + } + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return NULL; + } + + tags = page_get_target_data(ptr); + if (tags == NULL) { + size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(ptr, alloc_size); + assert(tags != NULL); + } + + index = extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; +#else /* Tag storage not implemented. */ return NULL; +#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) From patchwork Mon Feb 11 23:52:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158061 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3220268jaa; Mon, 11 Feb 2019 16:19:47 -0800 (PST) X-Google-Smtp-Source: AHgI3IbRC+NmBD7f9VwR8rF0j7Y+Kfpmc1NUClURbsEdK9xtOzA/6ntrAoB/VLnd3IhuMbqxOhZl X-Received: by 2002:a0d:ff85:: with SMTP id p127mr689586ywf.371.1549930787922; Mon, 11 Feb 2019 16:19:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930787; cv=none; d=google.com; s=arc-20160816; b=ppAUDgpA/uQxJQY+dTaXxf1UnJ2nldLgNo7qnQ/WzAnqdOLUmzn5tnSzQgCt9EQugU lYPAlAHIYYWhXDjih074VvXtKvDBZ1XqZ4BXj4S3Ttkvyb3NuMh7o/zTEBW6D9cnjzPQ Y/72CLkcdr/9hdkobxPPKo+BKF4a5AX0LO8iGoqcNeCP5KxQC9WuhdGYXoD75thEYlYl DqfWENm3z68K1UGQKpc+y+WyFPKcTrEPQN6KKkpjYAAcHasAF6lwrPCCQNXxvydF16Zt DjeI74qkffWM8gY5CaRXH2TzPBZNLxaR4MbZ9HroXz9lioG/K1XMFxYD4WrglBwIzw0J bVPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ju0kTjI209UCLXJK9JoNZjkA22NnBtRT7DAuiRVZe0I=; b=B/INGqTdqTrI7X7D8kh92/vTP1LfIsGrr3lySxEhHCSyQKI0qz2+80uv+NjM+pYKbl y4aDG6PuPhbXdZihb4qVwZC8or6bbKa7KjrLUey/8g52ip+xq+9/KeN3px2bZ11U9M/w 3/DDgccpkcJ/WuvrbPoklljUXccG3zbzxOjPkRXRFQo49A8/tM9qn5xcHIIeKE4ukPy0 RYB7WNJnYNwHiw1GLEUIZ9DzJvGSI7cYbf6UiljWcZXtUoVnru2ZqzW5LdH/3lxqPwcn KlPQPlvMJCUL3JFRRmpcM8FJ34zXAEagcSgU8//uC6yB8plMxwX4Pj3n9reap2G3c65J +dPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eM3Ut9Q8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:56 -0800 Message-Id: <20190211235258.542-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 26/28] target/arm: Add allocation tag storage for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 96 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 87 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 09c387e2c7..53c3ed862e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -28,18 +28,18 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { -#ifdef CONFIG_USER_ONLY ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); uint8_t *tags; uintptr_t index; - int flags; - flags = page_get_flags(ptr); +#ifdef CONFIG_USER_ONLY + int flags = page_get_flags(ptr); if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ))) { /* SIGSEGV */ env->exception.vaddress = ptr; - cpu_restore_state(CPU(cpu), ra, true); + cpu_restore_state(cs, ra, true); raise_exception(env, EXCP_DATA_ABORT, 0, 1); } @@ -56,16 +56,94 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, if (tags == NULL) { size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); tags = page_alloc_target_data(ptr, alloc_size); - assert(tags != NULL); + } +#else + int mmu_idx; + AddressSpace *as; + CPUTLBEntry *te; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + MemoryRegion *mr; + FlatView *fv; + hwaddr physaddr, tag_physaddr, tag_len, xlat; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + */ + mmu_idx = cpu_mmu_index(env, false); + index = tlb_index(env, mmu_idx, ptr); + te = tlb_entry(env, mmu_idx, ptr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, ptr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, ptr, 16, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + index = tlb_index(env, mmu_idx, ptr); + te = tlb_entry(env, mmu_idx, ptr); } + /* If the virtual page MemAttr != Tagged, nothing to do. */ + iotlbentry = &env->iotlb[mmu_idx][index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* If the board did not allocate tag memory, nothing to do. */ + as = cpu_get_address_space(cs, ARMASIdx_TAG); + if (!as) { + return NULL; + } + + /* Find the physical address for the virtual access. */ + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr + + section->offset_within_address_space + - section->offset_within_region); + + /* Convert to the physical address in tag space. */ + tag_physaddr = physaddr >> (LOG2_TAG_GRANULE + 1); + tag_len = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + + /* + * Find the tag physical address within the tag address space. + * + * ??? Create a new mmu_idx to cache the rest of this. + * + * ??? If we were assured of exactly one block of normal ram, + * and thus exactly one block of tag ram, then we could validate + * section->mr as ram, use the section offset vs cpu->tag_memory, + * and finish with memory_region_get_ram_ptr. + */ + rcu_read_lock(); + fv = address_space_to_flatview(as); + mr = flatview_translate(fv, tag_physaddr, &xlat, &tag_len, + write, MEMTXATTRS_UNSPECIFIED); + if (!memory_access_is_direct(mr, write)) { + /* + * This would seem to imply that the guest has marked a + * virtual page as Tagged when the physical page is not RAM. + * Should this raise some sort of bus error? + */ + rcu_read_unlock(); + qemu_log_mask(LOG_GUEST_ERROR, "Tagged virtual page 0x%" PRIx64 + " maps to physical page 0x%" PRIx64 " without RAM\n", + ptr, physaddr); + return NULL; + } + rcu_read_unlock(); + + /* The board should have created tag ram sized correctly. */ + assert(tag_len == TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)); + + /* FIXME: Mark the tag page dirty for migration. */ + + tags = qemu_map_ram_ptr(mr->ram_block, xlat); +#endif + + assert(tags != NULL); index = extract32(ptr, LOG2_TAG_GRANULE + 1, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); return tags + index; -#else - /* Tag storage not implemented. */ - return NULL; -#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) From patchwork Mon Feb 11 23:52:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158059 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3217629jaa; Mon, 11 Feb 2019 16:17:03 -0800 (PST) X-Google-Smtp-Source: AHgI3IZi6focVIGm1nHQ3Rn4evI8RaTQS9ALDsPTsoP2cp6eJDwyclGIgYK9BcC0tEJysR7ulXOR X-Received: by 2002:a81:2982:: with SMTP id p124mr704161ywp.273.1549930623488; Mon, 11 Feb 2019 16:17:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930623; cv=none; d=google.com; s=arc-20160816; b=Mpu/MiFpOIBeZ2Z8l5q8QSIgdAaa7tbSAxrhoZDAk3jbQ3AyhjYlP48HD+D+G+z55I /QVsOlZj15w95PQODpOajva0/fFZuh5iuHEk/rSjaRJMg7s+/EHGH2tWFqu7O7wOeMMs iGCjF4nTj3Pb5Uz0+/RyMoFvkOVODUWxpcZE+yf60nd2DKuSgeOEltx9bQjc2IJArg+N V19jTzuGCKMVNXwKfLLkfBBRmXQwiqSY4geub0ZCwEAcFOOA4REdmQFM9pZsbm74Oyll wLm1chSLvwPvTIR8Lb1s4H36cZKQr9RjCWXn+Rk5A0Qnk4labdZHZUnsztKalQHCgq+O PDng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=g7oNh1d8VWGEQw+YCuZLsLZ9OlLSdLVyb8nPu7OZ0AM=; b=ik3JB7RA5NIVV7D5UF/8+92PBT4IiLnVPzlAlV0/mtgn9391f0vW2jHhN3RevWjkf/ eSqOVBM+7V8vW/nHB9hooRG3zFgwy04DYNDQr+f8i0K9HCl5ZRcEHfRdKUSAAcyb2FaA +F1szZOx1APSHa38RZdLuZ2X+ZXTilk7JQdRzg8vsRK5ReSk+LZ1+zYwk3BsMWqvyCCt 5opkYXKpf4Lomgb9YtdvW5VfAXvFB8EQCbCWWpi6rBSuMISy+8gd1TnZx4yTBSSgzjE3 0p9fgCO1HHdFb+3OZsaOoQhCYSzpqEPe3QEPSkA04ieBDtjt6wK7a1RXaIH866NzpzpX kK/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="W1/tgCF5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:57 -0800 Message-Id: <20190211235258.542-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v3 27/28] target/arm: Enable MTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 10 ++++++++++ target/arm/cpu64.c | 1 + 2 files changed, 11 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index decf95de3e..a5599ae19f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -206,6 +206,16 @@ static void arm_cpu_reset(CPUState *s) * make no difference to the user-level emulation. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); + /* Enable MTE allocation tags. */ + env->cp15.hcr_el2 |= HCR_ATA; + env->cp15.scr_el3 |= SCR_ATA; + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* Enable synchronous tag check failures. */ + env->cp15.sctlr_el[1] |= 1ull << 38; +#ifdef TARGET_AARCH64 + /* Set MTE seed to non-zero value, otherwise RandomTag fails. */ + env->cp15.rgsr_el1 = 0x123400; +#endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 53a7d92c95..7bd761b8f5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -352,6 +352,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr1; From patchwork Mon Feb 11 23:52:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158055 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3214859jaa; Mon, 11 Feb 2019 16:13:25 -0800 (PST) X-Google-Smtp-Source: AHgI3Iax0QToK/YHkS6n9DEYxpyu+fKUuV8Xw0UDYvnyGb8MLDt4691FKfk6Q5k6BhTC+ar77th+ X-Received: by 2002:a81:a355:: with SMTP id a82mr647313ywh.445.1549930405316; Mon, 11 Feb 2019 16:13:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549930405; cv=none; d=google.com; s=arc-20160816; b=KhkZdvLWMV5SZLuPCEpUGeWHfAsrh4jkubqLgByzGILVvJH4PVr1FRqITPIe7iAUB2 qCF3exCtt1gTchXuXlDu3EyaOJJdUx0AxJdV1V0UWSHTnDjmPvery074JEDU4AzY4Sgp MOvjpPtKOuMo2hcy54z8NNyWa4ZchVoJdqjUpGIaguckI3XOjx0TpWpGipdHK8OqiFIc mdzSgGmAahQ2StupkIawFYW8F7Tg0PaKZZUN5/yT313/lqvJuJljjoq4F0NQ9rGKKZVh KX9qxuRzHnWkkAONCuqI2vAQfZyckWaXGZ3/AKvK44UgS3flG8+z/QWbeXk1v1IE5Dgc uQ4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=D7zmCCEx4gtvzG1BwOiqP1rjcgbsuS/cyN2XMLs4c+Y=; b=wPFl+l1nSdfPeCWs16zn6+AgJH0Rc11Dxr38ZaIei8Fdt7s3Vy2yR3iwJQfj3oTEby iHY57mAihKvHUXNLzUbFbofiaTEGjgXbkwDioIHOBV61yqI2WkN2fumrt0y5x4j9eEQt RM3bBabD3sC4hXSSurydm4T25fdYUpKiQAGSJgJgVrWrfQHsrU03qXlKD/kin52qlTBg RxjUlWqw8gcXme0Vx4U/Glv3wfeXCdJr0zfDdOrJciOvny0pcLbpagQbCrfACurvAgzj TcdqQPv48r24nJF25k0dqqXuDvgsBdBFH08zepuuXFestSii0RUHZ3jOzheJFUb3s/S2 f/Sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pgI8ttDa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:58 -0800 Message-Id: <20190211235258.542-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 28/28] tests/tcg/aarch64: Add mte smoke tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-1.c | 27 +++++++++++++++++++++ tests/tcg/aarch64/mte-2.c | 39 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 ++++ 3 files changed, 70 insertions(+) create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c -- 2.17.2 diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..18bfb1120f --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,27 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +int main(int ac, char **av) +{ + int *p0 = data; + int *p1, *p2; + long c; + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1)); + assert(p1 != p0); + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1)); + assert(c == 0); + + asm("stg %0, [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0)); + assert(p1 == p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..2991b7df69 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,39 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include +#include +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +void pass(int sig) +{ + exit(0); +} + +int main(int ac, char **av) +{ + int *p0 = data; + int *p1, *p2; + long excl = 1; + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + *p1 = 0; + signal(SIGSEGV, pass); + *p2 = 0; + + assert(0); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 55420aeea6..614dfcd14d 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -22,4 +22,8 @@ AARCH64_TESTS += bti-1 bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib run-bti-1: QEMU += -cpu max,x-guarded-pages=on +AARCH64_TESTS += mte-1 mte-2 +mte-%: CFLAGS += -O -g +run-mte-%: QEMU += -cpu max,x-tagged-pages=on + TESTS:=$(AARCH64_TESTS)