From patchwork Sat Sep 3 17:41:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6859BC6FA86 for ; Sat, 3 Sep 2022 17:42:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231864AbiICRmY (ORCPT ); Sat, 3 Sep 2022 13:42:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230507AbiICRmX (ORCPT ); Sat, 3 Sep 2022 13:42:23 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 826043E744; Sat, 3 Sep 2022 10:42:22 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id se27so9496683ejb.8; Sat, 03 Sep 2022 10:42:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=D2qyNP74bkeHUfQDADt03rKY4mapPBk8YQvQpuKozmc=; b=p1HseITbCo5DzJgZHHSZBat4C+PhV9H+NyKhorNitRbgYDe+twK6hAnq+BHZGVfpkK BLCFj+n2kVp0wBh3kDnEaLkUU5a4IpMLn7gaXAjf7Tn+BX9CRa10rIDs4zHQXKgyrCAO 9jwlFRCzu+FSqdIVZRQZQU/ffg/QX0eCKn6NSHFzl3TCXRIoy5x7Wuqq8UWcYmLiHB43 NGIVhMFL4r/GdXDKO9nfOM/yPxSkIYuq/RfZLX1uic0iCx6ZABV+hX6//TcQXLAm/VoD 7OSAO1xbhkhdwK6rKV4Yfbh6ykPpQ0c/7A/v4262LJH+KKxiE/U6GA7V6Uvzr1ylMwaX bFnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=D2qyNP74bkeHUfQDADt03rKY4mapPBk8YQvQpuKozmc=; b=Kc9qdTeOZB0Bz74efJmQ+fiZo496r9zYRPFOjtuUf3G8SI2KlYEOElVBHxpu/3mW8t jL95ag+WBLEYUw0uEP9N4Zsr0qvWPJbTWDD6qKb8UQmIQDeH8kf03mQXyh1eedOhQjSj neCYSW52OZZzgjP8+UeGWYIWENjqwUuUqWN/Nci2QwJO119u4irL+/LIeqVwV3uZMrO9 Le/0KyWTZTqGnbPoK4OLqEEsTNaGlMyY+3bIXkR/KOi+QBP8r7NM6t0YHX3Ypxc2+Yfl K+0JzRuU/Tofv/Q/82pTX7brV5ZcRYe4CC0flXvVAKJD7qrsNDpYjSqbiZ5/9/JbNivd ZhKw== X-Gm-Message-State: ACgBeo0FHmkFrxsZOKn8Y43g1/HHdXQmEGvDXkyYmcvtBBsvIl2H70sg P/Eea6BMXxB7ogImpbYUVGA= X-Google-Smtp-Source: AA6agR7H+AF+kBGgB2nDfQn3ShDwIAdxH/R5napeahxVwQNIz/Oo4Psea/trzOr3PBGD3w9Xorltrg== X-Received: by 2002:a17:906:4d9a:b0:73d:b425:d6b8 with SMTP id s26-20020a1709064d9a00b0073db425d6b8mr30454921eju.120.1662226941067; Sat, 03 Sep 2022 10:42:21 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id 9-20020a170906210900b0073d61238ae1sm2696220ejt.83.2022.09.03.10.42.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:20 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Alim Akhtar , Avri Altman , Bart Van Assche , Krzysztof Kozlowski , linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/9] dt-bindings: ufs: qcom: Add sm6115 binding Date: Sat, 3 Sep 2022 20:41:42 +0300 Message-Id: <20220903174150.3566935-2-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SM6115 UFS to DT schema. Signed-off-by: Iskren Chernev --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index f2d6298d926c..be55a5dfc68f 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -28,6 +28,7 @@ properties: - qcom,msm8998-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc + - qcom,sm6115-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - qcom,sm8250-ufshc @@ -178,6 +179,31 @@ allOf: minItems: 1 maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-ufshc + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: core_clk_ice + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + reg: + minItems: 2 + maxItems: 2 + # TODO: define clock bindings for qcom,msm8994-ufshc unevaluatedProperties: false From patchwork Sat Sep 3 17:41:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21A0BC54EE9 for ; Sat, 3 Sep 2022 17:42:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232252AbiICRm3 (ORCPT ); Sat, 3 Sep 2022 13:42:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232088AbiICRm0 (ORCPT ); Sat, 3 Sep 2022 13:42:26 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C987451A1D; Sat, 3 Sep 2022 10:42:24 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id 29so1452537edv.2; Sat, 03 Sep 2022 10:42:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=LiCUxZdYLa2Of1DNqQYrl2eGe/pmnbwIvotetEM5Z2E=; b=RriP5YsUUr8sTJic9u0ObZgjVl9Ko9DW/aBbZ8c5oGaZq3/XUk4CiulZFulnyZhF/G CVupWTuzwW6sv+s6qWt9VCrXKUo395LUPTupmVzaaGkoxbWOVjJKpA0TZdKyJN54uD4x M6j3rUUvuCGmuRXT7OtnDmAbTJhl4ZmrI7QiiYR+AZMRSutFkMDw+Cow9LFlIQcRvgBQ B9VkPGODe5bwfOumHKOkDFehJnncxSJJmwZKKB1Zp2cK+/c+xGdW2eH+6Z4HQ3nzgbbH kjDoOxeVxdvgVAvOsVwhvHsNSRcIpuGHOUezvASPQ1/fkG4Nznwsu2bMgN75nHjhqSbc P0Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=LiCUxZdYLa2Of1DNqQYrl2eGe/pmnbwIvotetEM5Z2E=; b=03DY6hBvaHIB6EoQKXkUTdeHe1ieZ/uipOsn1BIRVRv6sN3fcMIg00iqOoG744Wmk9 G/9J8K+8Aks+JV9QxmHAnwEsp9E6sX/LmVriIl6n4yL2C0LklW1c1pkIfzOfm3AmHbgn gXhqs+6B1+aLCIYYwWSDjdv5N51bHc6yk0te32vH1vjRJdF/Vy0GtvBd8dZq3GWZ4vJn P8KrTUyAI0hkkThAbh08gg3ziE+qBLHoVVRjx3DBcpdXpLNeJCXucC0R36C4+uXNyRbN M32OmfQn+UAvjNIoKWzTNbIsSXZZzagP1UuA3/VLtuEKdQPtju7cJMZTMk9mUHV6zezs FfDg== X-Gm-Message-State: ACgBeo134UFyiOYWL18yINXdUk53PvyRMWMRRXthshMgZFde3dyTq1D+ E8tzfh/It5EBSc6w28ofEz4= X-Google-Smtp-Source: AA6agR4nnz4enbxMuJD36RW+xEJMyZPRe/w5XSKaS+tFONKi0VzodqTT0gjITpf+ZoeKJM6NW3vI6w== X-Received: by 2002:a05:6402:14c6:b0:448:e27:5974 with SMTP id f6-20020a05640214c600b004480e275974mr31127791edx.53.1662226943292; Sat, 03 Sep 2022 10:42:23 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id az24-20020a170907905800b007385e929344sm2714168ejc.55.2022.09.03.10.42.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:22 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Robert Marko , Das Srinagesh , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/9] dt-bindings: firmware: document Qualcomm SM6115 SCM Date: Sat, 3 Sep 2022 20:41:43 +0300 Message-Id: <20220903174150.3566935-3-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the compatible for Qualcomm SM6115 SCM. Signed-off-by: Iskren Chernev Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 9fdeee07702f..c5b76c9f7ad0 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -44,6 +44,7 @@ properties: - qcom,scm-sdm845 - qcom,scm-sdx55 - qcom,scm-sdx65 + - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 - qcom,scm-sm8150 From patchwork Sat Sep 3 17:41:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E12C9C54EE9 for ; Sat, 3 Sep 2022 17:42:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232594AbiICRmd (ORCPT ); Sat, 3 Sep 2022 13:42:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230507AbiICRm2 (ORCPT ); Sat, 3 Sep 2022 13:42:28 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EB855141D; Sat, 3 Sep 2022 10:42:27 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id u6so6475223eda.12; Sat, 03 Sep 2022 10:42:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=0WRb2V91EcpbVW8u0Sp6LXTsiRGhW6DTkPaNDUU1Ni4=; b=mH5r4nxkfCoO9Jc9cNOO//o7p3t3pMbkvQxbHkkMeH3VNnl6jaxSVReyAml88/UZbZ 2x9KQQQtTu1sBSgMFXVFjjikMIEov34tLdj++jlVNXIK3M4cYjh9GH37XJ5oUUCD2lHj q/NUt6oL3EPBCeZVrOxnToqz8D2BWFH6WQeb0ubpY7y6q85Y88fB6rftDYD7fOVqsQU1 wR9QFnBszBQpddm2MfMNzycZjC4jJDCyWFWxLE9uo3z/dHrCy5CZ/qfqzIERNy4fpPpH kAQu81znHT5MWM7C5DPcrmopAeVnJw3m1/eOg96AHyR9/FnLKoOdZO61biYfNjzn0OBf DTVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=0WRb2V91EcpbVW8u0Sp6LXTsiRGhW6DTkPaNDUU1Ni4=; b=ct+KRzZ4qHb3uKj02x12AbuSSarJuMAgV8vzrP9+1Mwn0BmiRgrufkmewqGEkQ2Lgy f7u40Tpd766x1A4yijB512PXGYNJ0/bVLACTihRUn97bNBIPMOAmfSDnJ8bZQNR1MSeC 6w4pAoqsJWB7kWC3arib/2Ot+Tkz4zGVGWCOKE1DNiNBCEWDC7dMHp6nhMcveXFx3E0A oiKe0XW27RMvrcP3cjnASiccKtgZ79zUT+WJ1XSoawaRSTqEx5VQERnDEqz7aZwZwVhp 73JY8tatYrDU1CYiNXjut9Es/gw/Ea8kXN0GpmVvUUQskgnv199Zb3BZLgQuGP6RGT45 6fig== X-Gm-Message-State: ACgBeo1cWNkxEWe8wfjx1r45pO8tLtGVZ2r/sBto8hRyywe9NYnsv3mq SEzivx/Qq4K8BcgmCzEdNH4= X-Google-Smtp-Source: AA6agR4R9FsaOO172LC1Qlkygor8ueNi2Y4WqVoIHCT3jFpBFsSp1gBXWsspQ8Zz5Hc1+a25qrHMMQ== X-Received: by 2002:a05:6402:5008:b0:440:941a:93c3 with SMTP id p8-20020a056402500800b00440941a93c3mr37639760eda.47.1662226945606; Sat, 03 Sep 2022 10:42:25 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id 7-20020a170906328700b00734bfab4d59sm2754221ejw.170.2022.09.03.10.42.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:25 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Srinivas Kandagatla , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v2 3/9] dt-bindings: nvmem: Add SoC compatible for sm6115 Date: Sat, 3 Sep 2022 20:41:44 +0300 Message-Id: <20220903174150.3566935-4-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document SoC compatible for sm6115. Signed-off-by: Iskren Chernev Reviewed-by: Caleb Connolly Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index dede8892ee01..54053e16b8fd 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -26,6 +26,7 @@ properties: - qcom,sc7180-qfprom - qcom,sc7280-qfprom - qcom,sdm845-qfprom + - qcom,sm6115-qfprom - const: qcom,qfprom reg: From patchwork Sat Sep 3 17:41:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17EDFC38145 for ; Sat, 3 Sep 2022 17:42:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232790AbiICRmh (ORCPT ); Sat, 3 Sep 2022 13:42:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbiICRmd (ORCPT ); Sat, 3 Sep 2022 13:42:33 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B3C257893; Sat, 3 Sep 2022 10:42:29 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id fc24so517778ejc.3; Sat, 03 Sep 2022 10:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=P73eOPxMdP7ah0azvc46uUcxJLF7hXluonfSDW4iPlU=; b=FYOYYO7nA9ih7qSra3mlwk6cojp6M3gau8L+lT1NiJEBEDzwc2bRy8XaTLRtlfODRr QtBLcFU4zoeXc497oR4/gjCSmBsK8iHSng2AkmYTe2VBit0wS9d2QtHkXgac+yqTpQ6Q PWshtu4YhbKLHDVbyCi4iyZu6umUqKu6iazVT+PI1AwQlObMBrB4q2vAmOTt/X8apFVm S3wkuKLdMEp09hkDog5j1l6otrarLNqiGTyTNtXyxTa5S9ZIMEG+sce/KM14a1/MiAWW +kVcVUC/Bt25Gg9v68V+UtCY5tmqd/43flHA9EHX3A6Pe/U97YLBouDCnIJPqtXtlx9j KRyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=P73eOPxMdP7ah0azvc46uUcxJLF7hXluonfSDW4iPlU=; b=nadoRIdifWdj52kfvdIu+KJ2QfLoFbxf2CBrdE6abKjJH0kXfWToyP2FVGGwHuU1jD hy1gDPxoVVfTR/VoqFxc/qjgg7H28o0QQwW9Orc2nnPjP3yMxf2OIOC1xIhoRhDxtYFv 9W968luaLkodAvi/ncVKv+nfG5COKLUKZedq3OcWoRAyJrHLvJz5XZDjmiEbsepqSG95 qBaMpJ7aN2UcnzcrPuLeokL1ylbIMZtNPNReRhg5u24T6qdH3cEPk5awBlDE1AZDrAqn xSe3g3qssZ82BLHuhS6InsYLQUbV8p7XCf8ute6TdhB16HsrggZKFsyyM8zwoEAiYG3E 7LXg== X-Gm-Message-State: ACgBeo0i2306S/ttWEddQV1WWtUNzENzMxT/zUd4bxxP6CvgTtp75rOM Cup0dh9XePRgYr6+dJb48uY= X-Google-Smtp-Source: AA6agR693gMoJ12Yqon2WkSOZAzj4/Z+NxE82MtUpcccaXpmS5XBS56s6uLjexZ6F/Bhee5HkNkQ6Q== X-Received: by 2002:a17:906:8a5c:b0:73d:7f4a:b951 with SMTP id gx28-20020a1709068a5c00b0073d7f4ab951mr30384322ejc.481.1662226947822; Sat, 03 Sep 2022 10:42:27 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id u9-20020a1709061da900b0073d83f80b05sm2745035ejh.94.2022.09.03.10.42.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:27 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Linus Walleij , Krzysztof Kozlowski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/9] dt-bindings: pinctrl: qcom: sm6115: Add reserved ranges Date: Sat, 3 Sep 2022 20:41:45 +0300 Message-Id: <20220903174150.3566935-5-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ideally this and similar common properties will be inherited so you won't need to paste them in every pinctrl binding. Signed-off-by: Iskren Chernev Reviewed-by: Caleb Connolly --- .../devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml index a7a2bb8bff46..d8443811767d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml @@ -49,6 +49,8 @@ properties: gpio-ranges: maxItems: 1 + gpio-reserved-ranges: true + wakeup-parent: true #PIN CONFIGURATION NODES From patchwork Sat Sep 3 17:41:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA8E2ECAAD4 for ; Sat, 3 Sep 2022 17:42:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233125AbiICRm4 (ORCPT ); Sat, 3 Sep 2022 13:42:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232985AbiICRmt (ORCPT ); Sat, 3 Sep 2022 13:42:49 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 801CD5852A; Sat, 3 Sep 2022 10:42:35 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id fc24so518195ejc.3; Sat, 03 Sep 2022 10:42:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=d90cBTaHglfa/L3UmwiIFS49uaF4cnaVMbMrPZWt4mU=; b=US5Ymhd9bM+pHZEy+RWB9EG+qVJy8Ozaj7Xadj5wyPsMwt6AM7ChtfgFmbb4BWASG/ TMgJtFSGdEZaSG0aJh55FagneR0uvkXpw8hL/+upfXpxYXMsIpDMbAnZvdSalUy1SE9Y 2B8LTt+sjNcGVTrHWWt94ks8xoqOOD7DX2o+Q3K69pGI3kkvTMVG6GPCXHqQhkX4iAvT qs1zo00tBZAsccRQ3RnZte0tUpHNLEAX3M5Clm4zJxadfJ5/g2fbv0d+OCP6BWPBQYro qU7nD9TMW4xB3gkBAJF7St5jGhdVdaCMhpoDaCegwEvqlPYZm5A76fZkl4s4NN0M6riJ QULA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=d90cBTaHglfa/L3UmwiIFS49uaF4cnaVMbMrPZWt4mU=; b=F08ghTxFH6TZycJTnFfH0ldTq9PI5WAO88LNC2lOc1/MlFjtYDFApljVODiTXOF0CR 1MPLNBnV7FKq5b3e0zfbQGlVdq5eWBOmsa/X8c2vFk8MP8CNigBN7n7jMlrzv8yTEONh j4669SB57CF8zbluRYyH7wng0ZkMV7lBJr98RWYp5mZys0S5RigF3gL4cftAXfMOrpV5 gh+OyIth3YQRHb/9fqYRK2lm/gstIsM6ip/6YBR7e7RCZ/i8/6BpnvdiSah5zIcJt6Cb aAN4gDUQHVkuAo9HwoNraCOkE/uCOXtkKYjAQJoQdtAQdnRsAJbo/rMQJm8rD9nWm4P3 Pw8A== X-Gm-Message-State: ACgBeo3MXwLQOaErI/Ju96HLoZUazsFu31cd7KDNhupT77g4UiPEYGIy oB+Q+RYJUe6BJQN4sPRtAoQj9qTSgklTow== X-Google-Smtp-Source: AA6agR67nlD/IWBkek7VE3gtKSTY7s+2KevCI5sqqIokH7Q2aDWKF9uhimnyr4Hl8CUxPYnRpFfn8g== X-Received: by 2002:a17:906:9b8b:b0:741:56d3:b8fc with SMTP id dd11-20020a1709069b8b00b0074156d3b8fcmr23859088ejc.337.1662226955358; Sat, 03 Sep 2022 10:42:35 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id r13-20020a056402034d00b00447c89a63f4sm3526853edw.35.2022.09.03.10.42.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:34 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Vinod Koul , Krzysztof Kozlowski , Stephan Gerhold , Luca Weiss , Bartosz Dudziak , Maxime Ripard , Robin Murphy , Lorenzo Pieralisi , linux-kernel@vger.kernel.org Subject: [PATCH v2 5/9] dt-bindings: arm: cpus: Add kryo240 compatible Date: Sat, 3 Sep 2022 20:41:46 +0300 Message-Id: <20220903174150.3566935-6-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Kryo240 is found in SM4250, the slower sibling of the SM6115. Signed-off-by: Iskren Chernev Reviewed-by: Vinod Koul Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index a07c5bac7c46..5c13b73e4d57 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -174,6 +174,7 @@ properties: - nvidia,tegra194-carmel - qcom,krait - qcom,kryo + - qcom,kryo240 - qcom,kryo250 - qcom,kryo260 - qcom,kryo280 From patchwork Sat Sep 3 17:41:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C54DAC54EE9 for ; Sat, 3 Sep 2022 17:43:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233317AbiICRnG (ORCPT ); Sat, 3 Sep 2022 13:43:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233036AbiICRmv (ORCPT ); Sat, 3 Sep 2022 13:42:51 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD07C58DD9; Sat, 3 Sep 2022 10:42:39 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id qh18so9505308ejb.7; Sat, 03 Sep 2022 10:42:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=6uq5cQ9KVfg3HDUbnIhY2Bo8RTmJZ/5rDl5ZHG3HNZs=; b=Bs8aQTbFEJWFO3jn2TIdWHELQWYmLaFsndh/f1y3iMxdRbAf1lbXyzFVaHdK7fA3Ea gg6XxRaw9NTVSFBNkBzAuqkfVCBKJjPjLpjMgCjSK6mLTdSHJ5KZ+h25+bJdb9Z/PXNl 1LNki6l9lvJ26EuisTgvq41IZEQN7YG+j71Z9ie6W0VA/kX5M+xzOqQlaLC9rl1UnY99 u0wu4qVumq0Hr6ae6Z0UgOXFKHP0nKLr7sL5Al29V3t71EXPx/Scmi8x9U0KVdmO6m1Q W7fOTQ8K5fAe0wlBMnvstWpdgjK/hdgBuc51WbytaE16nykQ0O7oIc7mDvw/JP9Z7GYw zBNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=6uq5cQ9KVfg3HDUbnIhY2Bo8RTmJZ/5rDl5ZHG3HNZs=; b=ophtpAyEMJtrR624HBW3k1zxAN+/vnjS8geFUVHkC/8HZOZ3Sssb8T6CYQPYrIWpq4 2SGJ7URpghnhrm+w0W4ejVhkMICF7jSeC4XJtcq6WKTtIL/DjXYTS2kIZfesFZPDgCr+ 8sACoLXLq7+Np0htC0nEzFc4Le3pxnHO5uOj8SrQqNI3GgW7mKBgPAEICTY8fIXH1pnR PLWOv1+3TxQUO+CQnx3f8G5ynjgRFEoieOHZcupUbcz++BUAM6R6hJM9Bb8L/cOqYhlR 7uFcmkQDhBynWYQSHqiDs5eNknReb5CrSAn4e+Pok04BmhKCpgSoVBrA2rhAKgCT+zTv BokA== X-Gm-Message-State: ACgBeo0VHKSgFVcYt8g6TMYVnjPMW5wjRLoZu2v8faEqWinj/8jSAc+s nnQJ/LZG/D+ynUZ0nye8sxs= X-Google-Smtp-Source: AA6agR6SDJy0EOBbhTRUl47m86R28C2FgIqrmKWXSYZd7akQwenjoWfY+8xZ37pS7lDtAdkCe6Ff6Q== X-Received: by 2002:a17:906:9b89:b0:73d:6a55:c489 with SMTP id dd9-20020a1709069b8900b0073d6a55c489mr31335827ejc.406.1662226957543; Sat, 03 Sep 2022 10:42:37 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id c4-20020aa7c744000000b0044df7fd6250sm540402eds.3.2022.09.03.10.42.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:37 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v2 6/9] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Date: Sat, 3 Sep 2022 20:41:47 +0300 Message-Id: <20220903174150.3566935-7-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org oneplus,billie2 (OnePlus Nord N100) is based on QualComm Snapdragon SM4250 SoC. Add support for the same in dt-bindings. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 19c2f4314741..63cc41cd0119 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -54,6 +54,8 @@ description: | sdm845 sdx55 sdx65 + sm4250 + sm6115 sm6125 sm6350 sm7225 @@ -670,6 +672,11 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - oneplus,billie2 + - const: qcom,sm4250 + - items: - enum: - sony,pdx201 From patchwork Sat Sep 3 17:41:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CFE4C38145 for ; Sat, 3 Sep 2022 17:43:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233249AbiICRnS (ORCPT ); Sat, 3 Sep 2022 13:43:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233236AbiICRnB (ORCPT ); Sat, 3 Sep 2022 13:43:01 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AB925927F; Sat, 3 Sep 2022 10:42:43 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id gb36so9488157ejc.10; Sat, 03 Sep 2022 10:42:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=k5q1Z+5iM8r0Dfbb5h7AQPC3JDa/s1rXVrKO3l7mjC8=; b=G+To4AhtVBVsX14J2k/0rsjkGQsvLGHyrwwVziNXsYpoKz4oMCiGujiG7icdx67Gq6 Os0AdCyGr+/DCkJW72i/xYE+B4FHCoDdU3BP1Nso8v3ygfUBK/uaCGoFpvd7Lu84olz0 7ZFm3mU0CHfJpVS0I45HMcZ627HsYzZPqP95hW91M2xotpzpkh4uPux8Xp6oN1X/m2Tm Ts/CI1U1h+6PbwUmvxp1NOx/8sva3xHoXW3HC64oPf+B0KdQ/gsEue2de1zLX/kTUkFO DArEi+TRwicdk8tbzlm/a1SJZFPW02zYb4hUJxhWv62PYofyhsiCXXgLTX9C49GBVaMv kHDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=k5q1Z+5iM8r0Dfbb5h7AQPC3JDa/s1rXVrKO3l7mjC8=; b=0oxMl0EFIji2grawRHkX6g5kThtplijYQ7abf/fySNpXvkAZ8cKdnHFbVEodXQahmc EAWGzUMNTzcdyg8ZbtcOeiK/8JyTnAOLKDWOA5TJwbaFNPY/tX0PrJsogQnn5nxNmilg eSvlVJiobRPAbdadKKGlmjtIJmeJj9ocfcw/8IVfdABVvOTEvnOntNvTIwbeYVOPWbGA g0Ge1TFGPiGQ3H8E8y+IRvnWnQg3j6+ZEsArRWr35LqaTEU67viNgPpzHrpcCkWYtc1f NhWi0kGLzgcsb3FOaAXlq7aIe7FGz1mc8VVv3yS1/cf3t89y+XJFmHtVKTLElGh3LpFN wpLg== X-Gm-Message-State: ACgBeo1bZwma5AjndttZafOFIWp2G5lLFtj0IVwi4tHrnUGThgxjSAyY zNU7/cwA/Tw5/sNAoQtJLfY= X-Google-Smtp-Source: AA6agR4VItXUUjNEc6Lg5ayzdZkrImGVoW9E9B+eBDFpRCiyGZueiqsBrRVu/89zeUrhtKiSI2WuMg== X-Received: by 2002:a17:907:94c4:b0:741:9910:9dd with SMTP id dn4-20020a17090794c400b00741991009ddmr19713042ejc.568.1662226961639; Sat, 03 Sep 2022 10:42:41 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id 24-20020a170906301800b007386a8b90c9sm2810081ejz.13.2022.09.03.10.42.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:41 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v2 7/9] arm64: dts: qcom: sm6115: Add basic soc dtsi Date: Sat, 3 Sep 2022 20:41:48 +0300 Message-Id: <20220903174150.3566935-8-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Qualcomm SM6115 SoC. This includes: - GCC - Pinctrl - RPM (CC+PD) - USB - MMC - UFS Signed-off-by: Iskren Chernev --- Remaining issues from make dtbs_check: - qcom,glink-rpm -- this is still in a txt file - rpm-requests: qcom,glink-channels -- according to txt file, it is allowed property - pinctrl -- the existing bindings should support both simple (single pin) and multi-block pinctr blocks (this commit contains multi-block only). However it doesn't work. This block needs to be revisited: #PIN CONFIGURATION NODES patternProperties: '-state$': oneOf: - $ref: "#/$defs/qcom-sm6115-tlmm-state" - patternProperties: ".*": $ref: "#/$defs/qcom-sm6115-tlmm-state" - ufs phy: binding complains about missing #clock and #phy -cells. The outer binding is never used as a clock or a phy (via reference), and I don't think it will be. Also none of the other ufs phy dts files has those props - usb: according to schema, there should be 4 interrupts, but some have 2 (like sm6115), and some have none. I see no such interrupts on DS. Are they defined elsewhere? arch/arm64/boot/dts/qcom/sm6115.dtsi | 904 +++++++++++++++++++++++++++ 1 file changed, 904 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi new file mode 100644 index 000000000000..a1a5dc24e4db --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -0,0 +1,904 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: memory@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@46000000 { + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + }; + + cdsp_sec_mem: memory@46200000 { + reg = <0x0 0x46200000 0x0 0x1e00000>; + no-map; + }; + + pil_modem_mem: memory@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: memory@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: memory@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_cdsp_mem: memory@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_mem: memory@53800000 { + reg = <0x0 0x53800000 0x0 0x2800000>; + no-map; + }; + + pil_ipa_fw_mem: memory@56100000 { + reg = <0x0 0x56100000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@56110000 { + reg = <0x0 0x56110000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: memory@56115000 { + reg = <0x0 0x56115000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: memory@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: memory@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: memory@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + + secure_display_memory: memory@f3c00000 { + reg = <0x0 0xf3c00000 0x0 0x5c00000>; + no-map; + }; + + dump_mem: memory@f9800000 { + reg = <0x0 0xf9800000 0x0 0x800000>; + no-map; + }; + + adsp_mem: memory@fa000000 { + reg = <0x0 0xfa000000 0x0 0x800000>; + no-map; + }; + + qseecom_mem: memory@fa800000 { + reg = <0x0 0xfa800000 0x0 0x1400000>; + no-map; + }; + + user_contig_mem: memory@fbc00000 { + reg = <0x0 0xfbc00000 0x0 0x1000000>; + no-map; + }; + + qseecom_ta_mem: memory@fcc00000 { + reg = <0x0 0xfcc00000 0x0 0x1000000>; + no-map; + }; + + linux_cma_mem: memory@fdc00000 { + reg = <0x0 0xfdc00000 0x0 0x2000000>; + no-map; + }; + + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x500000 0x400000>, + <0x900000 0x400000>, + <0xd00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 121>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc1_state_on: sdc1-on-state { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio88"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x1400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + hsusb_phy: phy@1613000 { + compatible = "qcom,sm6115-qusb2-phy"; + reg = <0x1613000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + + status = "disabled"; + }; + + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x340000 0x20000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x4744000 0x1000>, <0x4745000 0x1000>, <0x4748000 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + + pinctrl-0 = <&sdc1_state_on>, <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_state_on>, <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6115-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x4804000 0x3000>, <0x4810000 0x8000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x100 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6115-qmp-ufs-phy"; + reg = <0x4807000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@4807400 { + reg = <0x4807400 0x098>, + <0x4807600 0x130>, + <0x4807c00 0x16c>; + #phy-cells = <0>; + }; + }; + + usb3: usb@4ef8800 { + compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; + reg = <0x04ef8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb3_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x04e00000 0xcd00>; + interrupts = ; + phys = <&hsusb_phy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; + reg = <0xc600000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,sm6115-apcs-hmss-global"; + reg = <0xf111000 0x1000>; + + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = ; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = ; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = ; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = ; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = ; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = ; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, + <0xf300000 0x100000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; From patchwork Sat Sep 3 17:41:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BF53ECAAD4 for ; Sat, 3 Sep 2022 17:43:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233375AbiICRnb (ORCPT ); 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Sat, 03 Sep 2022 10:42:44 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v2 8/9] arm64: dts: qcom: sm4250: Add soc dtsi Date: Sat, 3 Sep 2022 20:41:49 +0300 Message-Id: <20220903174150.3566935-9-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SM4250 is a downclocked version of the SM6115. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi new file mode 100644 index 000000000000..8cadf813e55b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include "sm6115.dtsi" + +&CPU0 { + compatible = "qcom,kryo240"; +}; + +&CPU1 { + compatible = "qcom,kryo240"; +}; + +&CPU2 { + compatible = "qcom,kryo240"; +}; + +&CPU3 { + compatible = "qcom,kryo240"; +}; + +&CPU4 { + compatible = "qcom,kryo240"; +}; + +&CPU5 { + compatible = "qcom,kryo240"; +}; + +&CPU6 { + compatible = "qcom,kryo240"; +}; + +&CPU7 { + compatible = "qcom,kryo240"; +}; From patchwork Sat Sep 3 17:41:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 602416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DBA6ECAAD4 for ; Sat, 3 Sep 2022 17:44:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231247AbiICRoG (ORCPT ); Sat, 3 Sep 2022 13:44:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233495AbiICRnK (ORCPT ); Sat, 3 Sep 2022 13:43:10 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A9325853C; Sat, 3 Sep 2022 10:42:51 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id a36so6518102edf.5; Sat, 03 Sep 2022 10:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=iH08URkzH4PtN0w43A4FqUIwqdPE7r8cstz4jRBcSF4=; b=CGZ4Kkycta6UgmTIkPkwdhqi4+T8LPWomiIYGeinaXG1B7ToAuSZdQ+dEk9JV29Laj Pc4E9mhKuZynp+PQRcU1kQJ6sUTM+rFMfh49WXMZNYQ5zCvbvbhEKwVBvwfgnDjtps4R cb1VZd5S1BXtdct+AO3R93u6hKu6Bj+v9CI6Y3lzxEKA8w4xeIKtnvI1t9hYJHvVK/iB POzGgE9vnPnvNmtrZVwKr2VU2XaXi7RHqHZhXTvyDDfivy4oVsIvWumfYRHYV13t7O8c cCd5cHXEpUAr/dOSVKL+N2SX3a3VvthBvMMbsrW7clYGCwlZT926jriw81Gt18O9plTj 5MQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=iH08URkzH4PtN0w43A4FqUIwqdPE7r8cstz4jRBcSF4=; b=6pA1+WyX2KbhEozng//9qwK833Z1JPeGPF81CeZKfScDqQWoJ4NhkOnhtrjY35vwIy uJg+JU68XClqFtN8ixtpNhAws+O2XotCbixUZCmBXNEpAZInk8bZX/ftOWzXQ+JxsxOw +K+vST1Zla2IqcAEv2gF0t6v19J02JJguDGhK4YXRTV2OAqG2a9vF+OMz8bVe9zprRI8 xAMgsQ5a13ooCBVDmTU9fKpXeAGpsKGsE3H8TD/3O3IGRe4kozCtWkJeK+/uzMplagio FIopwsgNXQxpw7vQmayTNdOf3fQ6vq6A3xJ+XySi+w6A3pPmUkUnMubLm+I0PJFXaT2w xkmQ== X-Gm-Message-State: ACgBeo3ra4VnROHMZSF6z2BVFezEJy2fMcr9VXDKPDiQVHu7ukk8eNI3 lBzb6csoGs4vT11CtunMUyE= X-Google-Smtp-Source: AA6agR4w9F1P+PSx9hSsZ7PRT7u1y6nV6ps0sq/JULWDegbUAMDq407bTbnPekP06P9DO191AK75Qw== X-Received: by 2002:a50:baa1:0:b0:43e:5e95:3eda with SMTP id x30-20020a50baa1000000b0043e5e953edamr38020237ede.340.1662226969180; Sat, 03 Sep 2022 10:42:49 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id z11-20020aa7d40b000000b00445b5874249sm3493955edq.62.2022.09.03.10.42.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Sep 2022 10:42:48 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-kernel@vger.kernel.org Subject: [PATCH v2 9/9] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Date: Sat, 3 Sep 2022 20:41:50 +0300 Message-Id: <20220903174150.3566935-10-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220903174150.3566935-1-iskren.chernev@gmail.com> References: <20220903174150.3566935-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add initial support for OnePlus Nord N100, based on SM4250. Currently working: - boots - usb - buildin flash storage (UFS) - SD card reader Signed-off-by: Iskren Chernev --- Remaining issues from make dtbs_check: - rpm-requests: it doesn't like the pm6125-regulators subnode. Every other DTS I checked is written in this way. arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 243 ++++++++++++++++++ 2 files changed, 244 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1d86a33de528..b8c2de2932a6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts new file mode 100644 index 000000000000..ea5f626a6749 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Iskren Chernev + */ + +/dts-v1/; + +#include "sm4250.dtsi" + +/ { + model = "OnePlus Nord N100"; + compatible = "oneplus,billie2", "qcom,sm4250"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; + qcom,board-id = <0x1000b 0x00>; + + aliases { + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (1600 * 720 * 4)>; + width = <720>; + height = <1600>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; + + clocks { + xo-board { + clock-frequency = <19200000>; + }; + + sleep-clk { + clock-frequency = <32764>; + }; + }; + + reserved-memory { + mtp_mem: memory@cc300000 { + reg = <0x00 0xcc300000 0x00 0xb00000>; + no-map; + }; + + param_mem: memory@cc200000 { + reg = <0x00 0xcc200000 0x00 0x100000>; + no-map; + }; + + bootloader_log_mem: memory@5fff7000 { + reg = <0x00 0x5fff7000 0x00 0x8000>; + no-map; + }; + + ramoops@cbe00000 { + compatible = "ramoops"; + reg = <0x0 0xcbe00000 0x0 0x400000>; + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + }; + }; +}; + +&usb3 { + status = "okay"; +}; + +&hsusb_phy { + vdd-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vddp-ref-clk-supply = <&vreg_l18a>; + status = "okay"; +}; + +&rpm_requests { + pm6125-regulators { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1456000>; + }; + + vreg_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; +};