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[209.132.180.67]) by mx.google.com with ESMTP id s13si9827354pgp.347.2019.02.18.04.30.24; Mon, 18 Feb 2019 04:30:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rZ+ikkj+; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730876AbfBRMaY (ORCPT + 15 others); Mon, 18 Feb 2019 07:30:24 -0500 Received: from mail-yw1-f68.google.com ([209.85.161.68]:43794 "EHLO mail-yw1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729690AbfBRMaY (ORCPT ); Mon, 18 Feb 2019 07:30:24 -0500 Received: by mail-yw1-f68.google.com with SMTP id u200so6350611ywu.10 for ; Mon, 18 Feb 2019 04:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LcPMcbMM+gl1ODsCm4mK776/DDedJToAB/PDkquqhxA=; b=rZ+ikkj+7sSAGH2HzRt8Sf2fk/tk/wl3mx4XSBsaOUE1wfIX85D3Y+VK1vL14NAyJC aPq4GCqK5dtw5usUA6Ai5BoXeRgl77eXnFHnbaznZn2zWuRizv6fQyNhmcaloRKIJyF3 sFbEvs/2UL99WHyzQk2tUEdtT9jvgi3vOofsLxF0DNUev03Kvj5YYPAUHvdU48ot0zrG U6moBbCjzTa5BxSoXBbGstUekEnUC8rrhsMGUa3+N0SMrBMcWuWij9Dpdy/3QAf3RAmj K4C6RHicRMQiU8wMEfL0zFGxBLo0vBYV/RMJF2OLtlTlIznIH/4G8rIwTLtHEF6zrybN zxKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LcPMcbMM+gl1ODsCm4mK776/DDedJToAB/PDkquqhxA=; b=JdMigPSXNljps3ePNbKXaajDX/2OsGLn+puACrCZLGeetQge87uAf2IpXUZzRcEze8 98H1GmPVGJeXft/VE1MwOt0z6ApU0PC6eeu8nly30V7XaSOki0UpgLv8ci7rT49f9HLa Ku7pF9kheg2XCXvd2bhxvgn0hoe3UbXzl0I/e136gMJu8sqAG1Ww1fT1MeBAD7TgkpTz wUAyWulSWEM7h84dzLfOrPGmaUJoh7MifFXmHd+7qHmrZ2k6OdfjsyuYK9jCB0I8nIPS uigGRXexZ4/CQ9kMx2qO1rOskojFzfjMZ/8uisFIOxiwJ3TMmQhHuZKCa0Xq2N0wAwGz 5KDA== X-Gm-Message-State: AHQUAuYTj4orLeUyESoSa2ILaTtIy4lgw6KWHA1FfvTqgvvzQVvhyH/K Hbo9JZrBfof2YVFKJyP1QItNFg== X-Received: by 2002:a81:3d45:: with SMTP id k66mr18257671ywa.279.1550493022684; Mon, 18 Feb 2019 04:30:22 -0800 (PST) Received: from localhost.localdomain ([106.51.22.126]) by smtp.gmail.com with ESMTPSA id z77sm1663695ywz.91.2019.02.18.04.30.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Feb 2019 04:30:21 -0800 (PST) From: Amit Pundir To: Greg KH Cc: Stable , Linus Walleij , Christian Lamparter Subject: [PATCH for-3.18.y+] pinctrl: msm: fix gpio-hog related boot issues Date: Mon, 18 Feb 2019 18:00:11 +0530 Message-Id: <1550493012-5959-2-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550493012-5959-1-git-send-email-amit.pundir@linaro.org> References: <1550493012-5959-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Christian Lamparter commit a86caa9ba5d70696ceb35d1d39caa20d8b641387 upstream. Sven Eckelmann reported an issue with the current IPQ4019 pinctrl. Setting up any gpio-hog in the device-tree for his device would "kill the bootup completely": | [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe | [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517 | [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register | [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip | [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri This was also verified on a RT-AC58U (IPQ4018) which would no longer boot, if a gpio-hog was specified. (Tried forcing the USB LED PIN (GPIO0) to high.). The problem is that Pinctrl+GPIO registration is currently peformed in the following order in pinctrl-msm.c: 1. pinctrl_register() 2. gpiochip_add() 3. gpiochip_add_pin_range() The actual error code -517 == -EPROBE_DEFER is coming from pinctrl_get_device_gpio_range(), which is called through: gpiochip_add of_gpiochip_add of_gpiochip_scan_gpios gpiod_hog gpiochip_request_own_desc __gpiod_request chip->request gpiochip_generic_request pinctrl_gpio_request pinctrl_get_device_gpio_range pinctrl_get_device_gpio_range() is unable to find any valid pin ranges, since nothing has been added to the pinctrldev_list yet. so the range can't be found, and the operation fails with -EPROBE_DEFER. This patch fixes the issue by adding the "gpio-ranges" property to the pinctrl device node of all upstream Qcom SoC. The pin ranges are then added by the gpio core. In order to remain compatible with older, existing DTs (and ACPI) a check for the "gpio-ranges" property has been added to msm_gpio_init(). This prevents the driver of adding the same entry to the pinctrldev_list twice. Reported-by: Sven Eckelmann Tested-by: Sven Eckelmann [ipq4019] Reviewed-by: Bjorn Andersson Signed-off-by: Christian Lamparter Signed-off-by: Linus Walleij [AmitP: Minor rebasing for Stable] Signed-off-by: Amit Pundir --- Cherry-picked from lede tree https://git.lede-project.org/?p=source.git and build tested for LTS trees up to v4.14.y for ARCH=arm/arm64 defconfig. drivers/pinctrl/qcom/pinctrl-msm.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 31632c087504..8f0368330a04 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -839,11 +839,24 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return ret; } - ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); - if (ret) { - dev_err(pctrl->dev, "Failed to add pin range\n"); - gpiochip_remove(&pctrl->chip); - return ret; + /* + * For DeviceTree-supported systems, the gpio core checks the + * pinctrl's device node for the "gpio-ranges" property. + * If it is present, it takes care of adding the pin ranges + * for the driver. In this case the driver can skip ahead. + * + * In order to remain compatible with older, existing DeviceTree + * files which don't set the "gpio-ranges" property or systems that + * utilize ACPI the driver has to call gpiochip_add_pin_range(). + */ + if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { + ret = gpiochip_add_pin_range(&pctrl->chip, + dev_name(pctrl->dev), 0, 0, chip->ngpio); + if (ret) { + dev_err(pctrl->dev, "Failed to add pin range\n"); + gpiochip_remove(&pctrl->chip); + return ret; + } } ret = gpiochip_irqchip_add(chip,