From patchwork Thu Feb 21 15:44:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 158913 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp634977jaa; Thu, 21 Feb 2019 07:45:35 -0800 (PST) X-Google-Smtp-Source: AHgI3IbExuz5ZSrS/1IIGsjKie035tmdp3OUwNwhx84a3hHpCiweUHNHaNNRG2bKURrIB8m79UMy X-Received: by 2002:a63:f753:: with SMTP id f19mr33880906pgk.437.1550763935074; Thu, 21 Feb 2019 07:45:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550763935; cv=none; d=google.com; s=arc-20160816; b=qjIfIlF9d40DOB35hj4Qu1R6FmxnBt1Z0AZaeIXupBCp8HV9pBsEas6Nb8xAQ+OFxy dFoneZXOxeWPMdoyIGjRAb2px200lDa/UtpC5a1mexhvX7lcTN01n+1Sk8vKfjpjYAeV jwueLlhj3lktDnBHXVvnEQv6qIODqm/c/LfYo5LeurVyW3iImvzJrRGn3P55Xn6wGDeS +pptIoglVVvzUc22MpubUQIp1PibggELi5vg6XhiW78iMg2lrHHvmT6y29YnzgY3XYja L36XOKqkbg2kPHfaf7Lf8CbF6hSrwljbcUlgfoXdQMLji7+GGpbiOhT0IV7oUg06OmNY KpBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/KRBvvDb8vJ/IUxT9QJ5LwxvIcDsKjNvBeUVd1RADoU=; b=VGwZVcnXVGUGxtb6GuqwSDsYM9BDEqZ2GWIFnjuuCOeeX/Igg74/Jqs6OoFIi9qZMo XE2lqM+pTlrq+BuFq5HAVg6AVoOtU6VQJRuz/aLwsLcqzECa3AtvsWjAtOm02Sik3Y5X XXm01QmKsWem89K9B/wsVhYO8P1aql9mbKuXzu42auXeTLu+osDN7z/vPGoXZfKwnE+a 8iSkf97wjjzpjUfuRSDYoR1cBOFteoVR0tKmU6ZS1Ngchrk702CYloBI3mq4bhYGSskO cHT8nvM7e6CZrZVSJTHYGQeo7FK7fNxFwYeWr4pFzFAhlJSHmCZSHPQl4o9ntHD1cDTH bA6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k6IOv8NP; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id m73sm1316965lfa.65.2019.02.21.07.45.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 07:45:31 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , Marc Zyngier , Jason Cooper , Thomas Gleixner , devicetree@vger.kernel.org Subject: [PATCH 09/30 v2] irqchip: ixp4xx: Add DT bindings Date: Thu, 21 Feb 2019 16:44:37 +0100 Message-Id: <20190221154458.23763-10-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221154458.23763-1-linus.walleij@linaro.org> References: <20190221154458.23763-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the IXP4xx interrupt controller. It's a standard 2-cell controller. Cc: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Converted to use JSON yaml schema, why not. - Not keeping Rob's ACK because I think he wants to take a second look. --- .../intel,ixp4xx-interrupt.yaml | 57 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml new file mode 100644 index 000000000000..f32c08f270d6 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx XScale Networking Processors Interrupt Controller + +maintainers: + - Linus Walleij + +description: | + This interrupt controller is found in the Intel IXP4xx processors. + Some processors have 32 interrupts, some have up to 64 interrupts. + The exact number of interrupts is determined from the compatible + string. + + The distinct IXP4xx families with different interrupt controller + variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four + families were the only ones to reach the developer and consumer + market. + +properties: + compatible: + oneOf: + - items: + - enum: + - intel,ixp42x-interrupt + - intel,ixp43x-interrupt + - intel,ixp45x-interrupt + - intel,ixp46x-interrupt + + reg: + description: The register bank for the interrupt controller. + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: The number of cells to define the interrupts. + with two cells specified in interrupt-controller/interrupts.txt + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + intcon: interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + reg = <0xc8003000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a2fb67b75026..79f01af59a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Thu Feb 21 15:44:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 158914 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp635084jaa; Thu, 21 Feb 2019 07:45:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IbfuvitixVwGs7WKbBodbk7bmvLwblAAhYih2qfcI3dMdYyAojM33o8pw0XvJzwdCT7UO4G X-Received: by 2002:a63:4a11:: with SMTP id x17mr19843056pga.376.1550763940276; Thu, 21 Feb 2019 07:45:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550763940; cv=none; d=google.com; s=arc-20160816; b=cld3zaAReNyKJtXYgC1leKiKdDZ/2iPT6MOYDLMmvZfDbWhKFu9b/4OZp+ewWfR3OX F1d03VYdE70M4B1hH3rAoQjwNSDvZ4gEmHRC99+uWMhILPSBFrE3zWtVYKzm2HIex48l HratCZzHjBet8aggE9Mdwc3SdEb3h5ikVjdpndowk6mXthnxw/UjxYKkf3dIxkTdS06H 5wTTmiGrZxVhNHxTm8PuiVii+K/0zxvoKUKdYHL530K1bv9Ou30By7iZ1oceaUN92WQ1 1AD5mHdqrKFSy1nvxa8PIAr/bHVSlpn1Lux/8X19f1L9c90iey0BwIsA48l7/dUgjV2Z hU8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=M/pLMnhSvVZVSoeIbvbkl48PXY+MXU30hXCPMAGgHSA=; b=xfpKtCIukplf81/xjxySUyEK39j8YDF1BcAnVkFk70cpLFBdr2u4qD+0Efy/MjP8w5 Ijuvvr/SHwFdmYmeTmU8UIPSCOam1ZCMFrIBoIyp/01hWppmiwT70C7n8kmEFEFnRHNX t7O0wbKn4mLJNls/h0m4zTzYwHjZ/RLsKNuzamV3CoEoPfZmhIIAPrKinij/pKSuPt9L DnAI+lJf2SFV383iJYplTF7aeQdmoYXjb1VHq0EkMXUNOuqIn6tR/MehKYc46ixLTJvI Ap2m3FGKgalGwWZfC3WSiQ0T6d02pGxTQy1uxcPAZw+8Q1LkaPtvjwyFDRUy3a5v69zY ddtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SdzM9T+2; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id m73sm1316965lfa.65.2019.02.21.07.45.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 07:45:36 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , Daniel Lezcano , Thomas Gleixner , devicetree@vger.kernel.org Subject: [PATCH 11/30 v2] clocksource/drivers/ixp4xx: Add DT bindings Date: Thu, 21 Feb 2019 16:44:39 +0100 Message-Id: <20190221154458.23763-12-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221154458.23763-1-linus.walleij@linaro.org> References: <20190221154458.23763-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx timers. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Switch to JSON YAML schema, why not. - Not collecting any review tags as this changed a bit. --- .../bindings/timer/intel,ixp4xx-timer.yaml | 42 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml new file mode 100644 index 000000000000..a36a0746c056 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/timer/intel-ixp4xx-timer.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx XScale Networking Processors Timers + +maintainers: + - Linus Walleij + +description: This timer is found in the Intel IXP4xx processors. + +properties: + compatible: + items: + - const: intel,ixp4xx-timer + + reg: + description: Should contain registers location and length + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: Timer 1 interrupt + - description: Timer 2 interrupt + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + timer@c8005000 { + compatible = "intel,ixp4xx-timer"; + reg = <0xc8005000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 79f01af59a63..bd04142b1026 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1651,6 +1651,7 @@ M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml +F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Thu Feb 21 15:44:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 158915 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp635156jaa; Thu, 21 Feb 2019 07:45:44 -0800 (PST) X-Google-Smtp-Source: AHgI3IbtCQFcmI2EgSQCamQ/HCi4cqf9lWK+5B/7HZ6oNyRVrhEVFXWTCp76Z+LnP9TwppZ/teat X-Received: by 2002:aa7:8d53:: with SMTP id s19mr21600361pfe.16.1550763944884; Thu, 21 Feb 2019 07:45:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550763944; cv=none; d=google.com; s=arc-20160816; b=yBJHkUxko47jZz2tmxa0TCZfKNUtid/RcTgZsQxzy4p5imxJnWwLe+WpnTY8eL6IPh ezmGPA3LEF/3+1yR9b26WSiY1lrog3k81l4Che4qcgP0LmLnNoi2l6aTwmZgKwFjhJQk 6e8MvhdoKrOHzpGsRuBWEz2a/4XM/wNA/ksdELGVRAmCUH0MVu5vyMTLiVbEfQKlle0a E8EvLp5oNgRjFCf01eZcGF7ZTlRFmOh7HLBhb7Ms3DbousZyBhb2xxcnz2lzcGY1lQzK A0Hv5Y0Y0BRJCUn337E5uCrEdfiOQ2FLbm4fc4jN/GtbdpN4K2WIf7Vy+k4dlwj66cis fE7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aeX9DWMdIFwcCgwi5VRHCh7QUyGrTDz0LIVexfDO4ns=; b=RwDynOaSlwlaLUbHWMSPrqjyMAhG7pbMWJyGLSllFuY2/UceEGplcjOgmu2pqDe7dt pCquce8/pivdJsG0VxdSbwOJbYm6awAmFlbp+2+LjLaTKKdcMu9glcj7A6ZDn7VayKsN Oc0+mdRVks9xO0wc4Q7wgqQICSX05aEe3IVd5behPzdN4I9chw5Xo663y/u5TwKACOpt RLyFNut+BGhAQhLntKUqxxy58G0v6GDHn0eSMj1245TOWQsskaubQd4Ztkxb8D9Gm4hq 0O3Q/mUtR+iHtrehoVkDQegP5My0ZoYdtOFYH/YDCLSpVWqxtv+1WfAgccpAAqiTpdlL HuWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XYnabqTj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id m73sm1316965lfa.65.2019.02.21.07.45.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 07:45:41 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org, Bartosz Golaszewski , Rob Herring Subject: [PATCH 13/30 v2] gpio: ixp4xx: Add DT bindings Date: Thu, 21 Feb 2019 16:44:41 +0100 Message-Id: <20190221154458.23763-14-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221154458.23763-1-linus.walleij@linaro.org> References: <20190221154458.23763-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds DT bindings for the IXP4xx GPIO controller. Cc: devicetree@vger.kernel.org Reviewed-by: Bartosz Golaszewski Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Collect Bartosz and Rob's review tags. --- .../bindings/gpio/intel,ixp4xx-gpio.txt | 38 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt new file mode 100644 index 000000000000..8dc41ed99685 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt @@ -0,0 +1,38 @@ +Intel IXP4xx XScale Networking Processors GPIO + +This GPIO controller is found in the Intel IXP4xx processors. +It supports 16 GPIO lines. + +The interrupt portions of the GPIO controller is hierarchical: +the synchronous edge detector is part of the GPIO block, but the +actual enabling/disabling of the interrupt line is done in the +main IXP4xx interrupt controller which has a 1:1 mapping for +the first 12 GPIO lines to 12 system interrupts. + +The remaining 4 GPIO lines can not be used for receiving +interrupts. + +The interrupt parent of this GPIO controller must be the +IXP4xx interrupt controller. + +Required properties: + +- compatible : Should be + "intel,ixp4xx-gpio" +- reg : Should contain registers location and length +- gpio-controller : marks this as a GPIO controller +- #gpio-cells : Should be 2, see gpio/gpio.txt +- interrupt-controller : marks this as an interrupt controller +- #interrupt-cells : a standard two-cell interrupt, see + interrupt-controller/interrupts.txt + +Example: + +gpio0: gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index bd04142b1026..b44ee076d57c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml F: arch/arm/mach-ixp4xx/ From patchwork Thu Feb 21 15:44:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 158916 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp635253jaa; Thu, 21 Feb 2019 07:45:50 -0800 (PST) X-Google-Smtp-Source: AHgI3IYO8AovfN/iCwbGnKhMgNaTyIE9m/QPbcJbYjRnSEwNYkOeSnUNL8ByGFU0Bjva1Ci3v5Fb X-Received: by 2002:a17:902:1486:: with SMTP id k6mr44455446pla.49.1550763950185; Thu, 21 Feb 2019 07:45:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550763950; cv=none; d=google.com; s=arc-20160816; b=a2FvnrGtc4LgtysHtJSYLFrFmCs2/TNDsRV2BN1xY17h9AOXZwbHE84JNNMiha1bkQ X82YOtoMudzjuBBsuEj5uywK73BdnAxjjdEBoo8c9QhjugGFMSLRAQ0EbjZbKqAY9y5P gBkBzJQL0QF494ryMJTsSzm+0XhC5xRJisk2OarQYPzdl5dQ5FoKqN2AuCAta59YO7nk ytCtn5P/zf1StWSoCGIg/hIHcoeDAHj9RTxNakF0C6vYrkOZeTWNmLTvt5BtWzq+xxEZ zA+RNVp+0ZIcZNNHla2D7Y3282Nsg25LhShs5FOhJRxtXBUtkx++zZq6/63SFtqfpY0z IpbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GnaI9YHPXZ63mtHWRidjn+9xBecr9vZlVNuaRUYughg=; b=wVr1kwOf6k5RWLznRY3N4e8xlaZwKAv6T4R5bwAp18CRkJxNdkeF15mtvoAT7MomF0 PQagNvWxplC/rCXENKIN4QfsRx5tlsFL61uvI4GFWoI3WDwMOW1iK5Wlh5kqv7q2af6W yP53exD43WA/UmXRzGR+6xiaNWj64BwLKYVU6WnIqehPlJLJhjiyB5kmqDG2nLMKL8Gb +njvuV+/zDzlSHAm36Q5kn6elUQdU+szRxVfrj3Ip02+xIdYBCpw9+k+OIdnkTcVq0wU KQ6n715uJQdENRztKxp/tz9U3ipFSNLmCHJMvK/hK8fOVeratHK16PdtJrJmJ56iL7EA LBfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TdGQDh7C; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id m73sm1316965lfa.65.2019.02.21.07.45.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 07:45:46 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org, Rob Herring Subject: [PATCH 15/30 v2] ARM: ixp4xx: Add DT bindings Date: Thu, 21 Feb 2019 16:44:43 +0100 Message-Id: <20190221154458.23763-16-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221154458.23763-1-linus.walleij@linaro.org> References: <20190221154458.23763-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds initial device tree bindings for the IXP4xx machines. This time I tried something wild and crazy and try to make proper JSON-style YAML bindings for the top level. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Fix up the GW2358 compatible string. --- .../devicetree/bindings/arm/intel-ixp4xx.yaml | 22 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml new file mode 100644 index 000000000000..f4f7451e5e8a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx Device Tree Bindings + +maintainers: + - Linus Walleij + +properties: + compatible: + oneOf: + - items: + - enum: + - linksys,nslu2 + - const: intel,ixp42x + - items: + - enum: + - gateworks,gw2358 + - const: intel,ixp43x diff --git a/MAINTAINERS b/MAINTAINERS index b44ee076d57c..20d02e1e60a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml From patchwork Thu Feb 21 15:44:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 158917 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp635725jaa; Thu, 21 Feb 2019 07:46:16 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia6TF98+LgjDZSwF+dwFDOYrDIel+0M3a/qjjCbCRy3SR0I2ArtTOBmuFxNtMQAyExYYjLN X-Received: by 2002:a63:89c7:: with SMTP id v190mr33191858pgd.370.1550763976476; Thu, 21 Feb 2019 07:46:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550763976; cv=none; d=google.com; s=arc-20160816; b=GkTsaxV+acUuWSaW9lAogNwbKO1GfhpoYNMi0wbc2jx5X/0w7qiZgsmE9EpdmaxrRl 5DRd5M1D2cfrIuqaj+Ddq4bQCovSGyMVpd9/RFkyoW3zDv4jTCdG5vl5Td8Ji1ixD73i +uTwqt89mf/KcSPPleVBYRm93Kb2P4Q8yzErpPfO2URRliTnlMub/hVf5NIoDNExFwNb UXyOThFtlZCFiukPJR9BSCP/vJoaR6UeWCcXbMHCgppdPOKuI4w+B7So1MVI4ade0rbY Ori3YwzZydlCFV/FNIDe0eIOi96WFTe2naW+nXfOLb0eFVWS4c6/kioBh29xDPo4UG8r PgBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9AKPZy57Xp9MQSyeUW4oZ24ugkhPxGm7E69P5yoWAno=; b=vwQ2UhrJ/0ZCr1O8jGEfZMQZ/dNOrs0oS3GeyzibbtCvBCMJSyxVKHpQT8SdPtkSYZ 7mqWY556ogyVic06yXv6M1Zm4UuxYfU2ckQsfZMAN8RAfKQsE/di3BpNM3wlXRx+lKZC l646bE9qP6gHu6UJUE8+3TGOP24Tv3E4wQPy5bf4aWqVQNh3PUQi8xqYu95OWGclT/RG L7UqVJZQQhtzHn5/UIrE3foTp31oL/pw869PYbKro+elPzQZ8/rRkv7zLCLRimPumFPf bCzUjNNUyBFw3q65driQ3vXVOumjYlQ6lKSGPyydL4QiOTVkoyUsf0T2Xk+MjZPQ5Dnf jKJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VgT5Q5gZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id m73sm1316965lfa.65.2019.02.21.07.46.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 07:46:12 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 26/30 v2] soc: ixp4xx: Add DT bindings for IXP4xx NPE Date: Thu, 21 Feb 2019 16:44:54 +0100 Message-Id: <20190221154458.23763-27-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221154458.23763-1-linus.walleij@linaro.org> References: <20190221154458.23763-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds DT bindings for the Intel IXP4xx Network Processing Engine (NPE). These are three firmware-executing units found in the IXP4xx SoC. These bindings use YAML. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ...ntel,ixp4xx-network-processing-engine.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml new file mode 100644 index 000000000000..8cb136c376fb --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx Network Processing Engine + +maintainers: + - Linus Walleij + +description: | + On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small + processor that can load a firmware to perform offloading of networking + and crypto tasks. It also manages the MDIO bus to the ethernet PHYs + on the IXP4xx platform. All IXP4xx platforms have three NPEs at + consecutive memory locations. They are all included in the same + device node since they are not independent of each other. + +properties: + compatible: + oneOf: + - items: + - const: intel,ixp4xx-network-processing-engine + + reg: + minItems: 3 + maxItems: 3 + items: + - description: NPE0 register range + - description: NPE1 register range + - description: NPE2 register range + +required: + - compatible + - reg + +examples: + - | + npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + }; From patchwork Thu Feb 21 15:44:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 158918 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp635836jaa; Thu, 21 Feb 2019 07:46:22 -0800 (PST) X-Google-Smtp-Source: AHgI3IYMPQLGvzyA21pDyM8uidfq2v7otO8ejaSxE8QrcPOJmBWH7+IHumRT1C7AS0NexTUiFVfh X-Received: by 2002:a17:902:6b08:: with SMTP id o8mr9876876plk.105.1550763982368; Thu, 21 Feb 2019 07:46:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550763982; cv=none; d=google.com; s=arc-20160816; b=bXqEH14s/BSEnkaafbh85X7D1yAnT0AuGIsjqvgCUMa+px7iV+CazE5rhMX6agyzdC ydMj3S0Ri7mCTwj0fQiMeTk0kf1qTTd6iJkp54SD/LIMziH/HgVz2X+rU+QgsJbdrZ2l wknaR3VEH832KpXLNY/j7KJBvu/au9AlRWGWyXezPmeG5KmLLa7EEoU/vA9K6Y6WjLgO 4ZD+V5zUXn0XqrZ2lIoXJHMWZycLHHnD3CrE6puHMAy0HvuoESbxIoHZvxzhNHocxLB8 tdBY4f5BFOQDHyVAGPaZRLUPIGll9/Rfvh+nEss/Uzm5Mo0S4y9mz2TGw8aJmJsG09ie /EOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Lg7YL4rHndwDCrRxPsXDrWFsjfxlwxbyihlkIAGrRzI=; b=ndJOuqc9ZT5j0BkuUUOuUeZbMkXKjA/UWN6dZhoEn0PJ/3FvOhT2qEm2Rlb/5IwdbO jp0RejJBRAlSSg98mHKxpeE/f3UHBbnnxTrwpqiU905RHmPHRA0/IQW2KVSz1vrfhI4r 8h8ES+I2nJ5xYkgvuP/T4g2gy0ozBbWWmMlh0oumilu19A7DWqXSTJU9+DBNWYOPnB6H J3U7OWrxYsqOouuurD+MkrPIwHpToJKGQlDE/wC/rNPiThV2U//ym8nazgpjeSMC+KZ7 o+s13UXEVsGXRUZ1kNOV3kLyhUNPbkPwZ4WJ9lB3rcxx20v+eBZC1oGw7aeBBs/unIcj UfCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sNakXodk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id m73sm1316965lfa.65.2019.02.21.07.46.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 07:46:18 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 28/30 v2] soc: ixp4xx: qmgr: Add DT bindings for IXP4xx qmgr Date: Thu, 21 Feb 2019 16:44:56 +0100 Message-Id: <20190221154458.23763-29-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221154458.23763-1-linus.walleij@linaro.org> References: <20190221154458.23763-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx AHB Queue Manager. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- .../misc/intel,ixp4xx-queue-manager.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml b/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml new file mode 100644 index 000000000000..c324860bede5 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx AHB Queue Manager + +maintainers: + - Linus Walleij + +description: | + The IXP4xx AHB Queue Manager maintains queues as circular buffers in + an 8KB embedded SRAM along with hardware pointers. It is used by both + the XScale processor and the NPEs (Network Processing Units) in the + IXP4xx for accelerating queues, especially for networking. Clients pick + queues from the queue manager with foo-queue = <&qmgr N> where the + &qmgr is a phandle to the queue manager and N is the queue resource + number. The queue resources available and their specific purpose + on a certain IXP4xx system will vary. + +properties: + compatible: + oneOf: + - items: + - const: intel,ixp4xx-ahb-queue-manager + + reg: + items: + - description: Queue Manager MMIO range + + interrupts: + minItems: 2 + maxItems: 2 + items: + - description: Interrupt for queues 0-31 + - description: Interrupt for queues 32-63 + + '#queue-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + + qmgr: queue-manager@60000000 { + compatible = "intel,ixp4xx-ahb-queue-manager"; + reg = <0x60000000 0x4000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; + #queue-cells = <1>; + };