From patchwork Wed Sep 28 17:52:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 610299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58EDDC6FA90 for ; Wed, 28 Sep 2022 17:52:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234369AbiI1Rwz (ORCPT ); Wed, 28 Sep 2022 13:52:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234093AbiI1Rww (ORCPT ); Wed, 28 Sep 2022 13:52:52 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBAACF85AC; Wed, 28 Sep 2022 10:52:49 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqSeE068355; Wed, 28 Sep 2022 12:52:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664387548; bh=U/A5bFOTrvS5PJd2SiMxUroXJjiGvivMeuXikcg9+n0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pU2/IBjr9EfNnKFxbu8dFyG85vxYJnTgj3RPtkXruA2Pt54RkT9N5m1isHXmCLFuX ZT5DgB+/uqJbzOm8U0t6BjmoYTAtfO1jTYqWJniLgbqi0mXgcPmpu/cx/v1neg8TNn Xwlb1wsPMnXm53YSmfm4ae2zVP6mDCoyjWPU41uU= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28SHqSfL115162 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Sep 2022 12:52:28 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 28 Sep 2022 12:52:27 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 28 Sep 2022 12:52:27 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqQ3W001066; Wed, 28 Sep 2022 12:52:27 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 2/6] dt-bindings: display: ti: am65x-dss: Add new port for am625-dss Date: Wed, 28 Sep 2022 23:22:19 +0530 Message-ID: <20220928175223.15225-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add 3rd "port" property for am625-dss. This port represents the output from the 2nd OLDI TX (OLDI TX 1) latched onto the first video port (VP0) from the DSS controller on AM625 SOC. Signed-off-by: Aradhya Bhatia --- .../bindings/display/ti/ti,am65x-dss.yaml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 6bbce921479d..99576c6ec108 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -82,13 +82,18 @@ properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: - The DSS OLDI output port node form video port 1 + The DSS OLDI output port node form video port 1 (OLDI TX 0). port@1: $ref: /schemas/graph.yaml#/properties/port description: The DSS DPI output port node from video port 2 + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + The DSS OLDI output port node form video port 1 (OLDI TX 1). + ti,am65x-oldi-io-ctrl: $ref: "/schemas/types.yaml#/definitions/phandle" description: @@ -104,6 +109,17 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second +if: + properties: + compatible: + contains: + const: ti,am65x-dss +then: + properties: + ports: + properties: + port@2: false + required: - compatible - reg From patchwork Wed Sep 28 17:52:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 610297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B13CC04A95 for ; Wed, 28 Sep 2022 17:53:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234225AbiI1RxR (ORCPT ); Wed, 28 Sep 2022 13:53:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234723AbiI1RxJ (ORCPT ); Wed, 28 Sep 2022 13:53:09 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51184F8594; Wed, 28 Sep 2022 10:52:59 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqTdm077451; Wed, 28 Sep 2022 12:52:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664387549; bh=wOdTIH04zCG32VSdCu2/2EFESBmHau0thJrO8QBimxo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DOqQmbbrFAeZ+KlatytGC9cE8NIhKbyZycV+/I0RfI7I6ztP0cjOyDwZU0M5+AVbc wVMAzMR/kayQv2u5ThbE/MVMo08v27W/tV/bMrZYJIQLN4XD/Z0p54mglC4ey0oTdo lUBYa07VkSFTgsOlO9wdQmSBBcJtQQa/AzeGokm4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28SHqT7S029184 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Sep 2022 12:52:29 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 28 Sep 2022 12:52:29 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 28 Sep 2022 12:52:29 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqS19001228; Wed, 28 Sep 2022 12:52:28 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 3/6] drm/tidss: Add support for AM625 DSS Date: Wed, 28 Sep 2022 23:22:20 +0530 Message-ID: <20220928175223.15225-4-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the DSS controller on TI's new AM625 SoC in the tidss driver. The first video port (VP0) in am625-dss can output OLDI signals through 2 OLDI TXes. A 3rd port has been added with "DISPC_VP_OLDI" bus type. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 61 ++++++++++++++++++++++++++++- drivers/gpu/drm/tidss/tidss_dispc.h | 3 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index dd3c6a606ae2..34f0da4bb3e3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -93,6 +93,7 @@ const struct dispc_features dispc_k2g_feats = { .common_regs = tidss_k2g_common_regs, .num_vps = 1, + .num_max_ports = 1, .vp_name = { "vp1" }, .ovr_name = { "ovr1" }, .vpclk_name = { "vp1" }, @@ -168,6 +169,7 @@ const struct dispc_features dispc_am65x_feats = { .common_regs = tidss_am65x_common_regs, .num_vps = 2, + .num_max_ports = 2, .vp_name = { "vp1", "vp2" }, .ovr_name = { "ovr1", "ovr2" }, .vpclk_name = { "vp1", "vp2" }, @@ -257,6 +259,7 @@ const struct dispc_features dispc_j721e_feats = { .common_regs = tidss_j721e_common_regs, .num_vps = 4, + .num_max_ports = 4, .vp_name = { "vp1", "vp2", "vp3", "vp4" }, .ovr_name = { "ovr1", "ovr2", "ovr3", "ovr4" }, .vpclk_name = { "vp1", "vp2", "vp3", "vp4" }, @@ -275,6 +278,57 @@ const struct dispc_features dispc_j721e_feats = { .vid_order = { 1, 3, 0, 2 }, }; +const struct dispc_features dispc_am625_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI] = 165000, + [DISPC_VP_OLDI] = 165000, + }, + + .scaling = { + .in_width_max_5tap_rgb = 1280, + .in_width_max_3tap_rgb = 2560, + .in_width_max_5tap_yuv = 2560, + .in_width_max_3tap_yuv = 4096, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .subrev = DISPC_AM625, + + .common = "common", + .common_regs = tidss_am65x_common_regs, + + .num_vps = 2, + /* note: the 3rd port is not representative of a 3rd pipeline */ + .num_max_ports = 3, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + .vp_bus_type = { DISPC_VP_OLDI, DISPC_VP_DPI, DISPC_VP_OLDI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vid", "vidl1" }, + .vid_lite = { false, true, }, + .vid_order = { 1, 0 }, +}; + static const u16 *dispc_common_regmap; struct dss_vp_data { @@ -778,6 +832,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) return dispc_k2g_read_and_clear_irqstatus(dispc); case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: return dispc_k3_read_and_clear_irqstatus(dispc); default: WARN_ON(1); @@ -793,6 +848,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) break; case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: dispc_k3_set_irqenable(dispc, mask); break; default: @@ -1282,6 +1338,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, x, y, layer); break; case DISPC_AM65X: + case DISPC_AM625: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); break; @@ -2205,6 +2262,7 @@ static void dispc_plane_init(struct dispc_device *dispc) break; case DISPC_AM65X: case DISPC_J721E: + case DISPC_AM625: dispc_k3_plane_init(dispc); break; default: @@ -2310,6 +2368,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc, dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); break; case DISPC_AM65X: + case DISPC_AM625: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; case DISPC_J721E: @@ -2583,7 +2642,7 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, 2, 2), REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); - if (dispc->feat->subrev == DISPC_AM65X) + if (dispc->feat->subrev == DISPC_AM65X || dispc->feat->subrev == DISPC_AM625) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", REG_GET(dispc, DSS_SYSSTATUS, 5, 5), REG_GET(dispc, DSS_SYSSTATUS, 6, 6), diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index e49432f0abf5..b66418e583ee 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -61,6 +61,7 @@ enum dispc_dss_subrevision { DISPC_K2G, DISPC_AM65X, DISPC_J721E, + DISPC_AM625, }; struct dispc_features { @@ -74,6 +75,7 @@ struct dispc_features { const char *common; const u16 *common_regs; u32 num_vps; + u32 num_max_ports; const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ @@ -88,6 +90,7 @@ struct dispc_features { extern const struct dispc_features dispc_k2g_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; +extern const struct dispc_features dispc_am625_feats; void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c index 04cfff89ee51..326059e99696 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -235,6 +235,7 @@ static const struct of_device_id tidss_of_table[] = { { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, + { .compatible = "ti,am625-dss", .data = &dispc_am625_feats, }, { } }; From patchwork Wed Sep 28 17:52:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 610298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28F2FC32771 for ; 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Wed, 28 Sep 2022 12:52:33 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 28 Sep 2022 12:52:33 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 28 Sep 2022 12:52:33 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28SHqWQA001317; Wed, 28 Sep 2022 12:52:33 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski CC: Nishanth Menon , Vignesh Raghavendra , Rahul T R , DRI Development List , Devicetree List , Linux Kernel List Subject: [RFC PATCH v5 6/6] drm/tidss: Enable Dual and Duplicate Modes for OLDI Date: Wed, 28 Sep 2022 23:22:23 +0530 Message-ID: <20220928175223.15225-7-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220928175223.15225-1-a-bhatia1@ti.com> References: <20220928175223.15225-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AM625 DSS IP contains 2 OLDI TXes which can work to enable 2 duplicated displays of smaller resolutions or enable a single Dual Link display with a higher resolution (1920x1200). Configure the necessary register to enable and disable the OLDI TXes with necessary modes configurations. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 68444e0cd8d7..fd7f49535f0c 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1003,8 +1003,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, int count = 0; /* - * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC - * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. + * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are + * set statically to 0. */ if (fmt->data_width == 24) @@ -1021,6 +1021,30 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, oldi_cfg |= BIT(0); /* ENABLE */ + switch (dispc->oldi_mode) { + case OLDI_MODE_OFF: + oldi_cfg &= ~BIT(0); /* DISABLE */ + break; + + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* All configuration is done for this mode. */ + break; + + case OLDI_SINGLE_LINK_CLONE_MODE: + oldi_cfg |= BIT(5); /* CLONE MODE */ + break; + + case OLDI_DUAL_LINK_MODE: + oldi_cfg |= BIT(11); /* DUALMODESYNC */ + oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */ + break; + + default: + dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n", + __func__); + return; + } + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&