From patchwork Fri Sep 30 07:33:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 611168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24FA3C4332F for ; Fri, 30 Sep 2022 07:35:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230321AbiI3Hfu (ORCPT ); Fri, 30 Sep 2022 03:35:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230250AbiI3Hft (ORCPT ); Fri, 30 Sep 2022 03:35:49 -0400 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.154.221.58]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B378210F719; Fri, 30 Sep 2022 00:35:45 -0700 (PDT) X-QQ-mid: bizesmtp82t1664523211t84a3mb1 Received: from ubuntu.localdomain ( [113.72.146.201]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 30 Sep 2022 15:33:29 +0800 (CST) X-QQ-SSF: 01000000000000305000000A0000000 X-QQ-FEAT: 1c0FlmCJYTe9L4VwpR5QJP8ykXYxKgZZKBwmOnHNdYV/dTbg7nCTTk5pfbjnc 7P7GSBPFa2Hbpxn4vkZeeuVFj3pLGFvw8Mbq+IAZYntImYeps4hzn0dxNjTEkO3liEptczz IJhIMmtigWGnxmn5aCEG7FTINZoALqpYGFJeqldwj4qK7rQpvd9NK48O7KAQiAxXBkdTbS3 mpdCchbfRg52Mi+ILogYGHil/qKUA654KHqVXFB+7pnL1HLcgd45KOdmx/Z35q+d44qeJ2/ akV+e7JDgrKOaGX5HT8pfCNSVHKwLS10y3MJ3ZdIfphOMviceNPWJfzF8hVF0h6zakvAXMB HC1c1g3/iaLYviHff5/9hHx+1j+0VM8wF3DQ2x5HrRhWlROB9QjeEw+t7mkHu0GikbXkJqM X-QQ-GoodBg: 0 From: Hal Feng To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , Hal Feng , linux-kernel@vger.kernel.org Subject: [PATCH v1 24/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Date: Fri, 30 Sep 2022 15:33:28 +0800 Message-Id: <20220930073328.6204-1-hal.feng@linux.starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:linux.starfivetech.com:qybglogicsvr:qybglogicsvr2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jianlong Huang Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Jianlong Huang Signed-off-by: Hal Feng --- .../pinctrl/pinctrl-starfive-jh7110.h | 931 ++++++++++++++++++ 1 file changed, 931 insertions(+) create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h new file mode 100644 index 000000000000..159cfcf6b915 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h @@ -0,0 +1,931 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__ + +/* aon_iomux pin */ +#define PAD_TESTEN 0 +#define PAD_RGPIO0 1 +#define PAD_RGPIO1 2 +#define PAD_RGPIO2 3 +#define PAD_RGPIO3 4 +#define PAD_RSTN 5 +#define PAD_GMAC0_MDC 6 +#define PAD_GMAC0_MDIO 7 +#define PAD_GMAC0_RXD0 8 +#define PAD_GMAC0_RXD1 9 +#define PAD_GMAC0_RXD2 10 +#define PAD_GMAC0_RXD3 11 +#define PAD_GMAC0_RXDV 12 +#define PAD_GMAC0_RXC 13 +#define PAD_GMAC0_TXD0 14 +#define PAD_GMAC0_TXD1 15 +#define PAD_GMAC0_TXD2 16 +#define PAD_GMAC0_TXD3 17 +#define PAD_GMAC0_TXEN 18 +#define PAD_GMAC0_TXC 19 + +/* aon_iomux dout */ +#define GPO_AON_CLK_32K_OUT 2 +#define GPO_AON_PTC0_PWM4 3 +#define GPO_AON_PTC0_PWM5 4 +#define GPO_AON_PTC0_PWM6 5 +#define GPO_AON_PTC0_PWM7 6 +#define GPO_AON_CLK_GCLK0 7 +#define GPO_AON_CLK_GCLK1 8 +#define GPO_AON_CLK_GCLK2 9 + +/* aon_iomux doen */ +#define OEN_AON_PTC0_OE_N_4 2 +#define OEN_AON_PTC0_OE_N_5 3 +#define OEN_AON_PTC0_OE_N_6 4 +#define OEN_AON_PTC0_OE_N_7 5 + +/* aon_iomux gin */ +#define GPI_AON_PMU_GPIO_WAKEUP_0 0 +#define GPI_AON_PMU_GPIO_WAKEUP_1 1 +#define GPI_AON_PMU_GPIO_WAKEUP_2 2 +#define GPI_AON_PMU_GPIO_WAKEUP_3 3 + +/* aon_iomux gmac0 syscon */ +#define PADCFG_PAD_GMAC0_MDC_SYSCON 0x58 +#define PADCFG_PAD_GMAC0_MDIO_SYSCON 0x5c +#define PADCFG_PAD_GMAC0_RXD0_SYSCON 0x60 +#define PADCFG_PAD_GMAC0_RXD1_SYSCON 0x64 +#define PADCFG_PAD_GMAC0_RXD2_SYSCON 0x68 +#define PADCFG_PAD_GMAC0_RXD3_SYSCON 0x6c +#define PADCFG_PAD_GMAC0_RXDV_SYSCON 0x70 +#define PADCFG_PAD_GMAC0_RXC_SYSCON 0x74 +#define PADCFG_PAD_GMAC0_TXD0_SYSCON 0x78 +#define PADCFG_PAD_GMAC0_TXD1_SYSCON 0x7c +#define PADCFG_PAD_GMAC0_TXD2_SYSCON 0x80 +#define PADCFG_PAD_GMAC0_TXD3_SYSCON 0x84 +#define PADCFG_PAD_GMAC0_TXEN_SYSCON 0x88 +#define PADCFG_PAD_GMAC0_TXC_SYSCON 0x8c + +/* aon_iomux func sel */ +#define AON_IOMUX_CFGSAIF_144_ADDR 0x90 +#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT 0x0 +#define PAD_GMAC0_RXC_FUNC_SEL_MASK 0x3 + +#define PAD_GMAC0_RXC_FUNC_SEL \ + AON_IOMUX_CFGSAIF_144_ADDR \ + PAD_GMAC0_RXC_FUNC_SEL_SHIFT \ + PAD_GMAC0_RXC_FUNC_SEL_MASK + +/* sys_iomux pin */ +#define PAD_GPIO0 0 +#define PAD_GPIO1 1 +#define PAD_GPIO2 2 +#define PAD_GPIO3 3 +#define PAD_GPIO4 4 +#define PAD_GPIO5 5 +#define PAD_GPIO6 6 +#define PAD_GPIO7 7 +#define PAD_GPIO8 8 +#define PAD_GPIO9 9 +#define PAD_GPIO10 10 +#define PAD_GPIO11 11 +#define PAD_GPIO12 12 +#define PAD_GPIO13 13 +#define PAD_GPIO14 14 +#define PAD_GPIO15 15 +#define PAD_GPIO16 16 +#define PAD_GPIO17 17 +#define PAD_GPIO18 18 +#define PAD_GPIO19 19 +#define PAD_GPIO20 20 +#define PAD_GPIO21 21 +#define PAD_GPIO22 22 +#define PAD_GPIO23 23 +#define PAD_GPIO24 24 +#define PAD_GPIO25 25 +#define PAD_GPIO26 26 +#define PAD_GPIO27 27 +#define PAD_GPIO28 28 +#define PAD_GPIO29 29 +#define PAD_GPIO30 30 +#define PAD_GPIO31 31 +#define PAD_GPIO32 32 +#define PAD_GPIO33 33 +#define PAD_GPIO34 34 +#define PAD_GPIO35 35 +#define PAD_GPIO36 36 +#define PAD_GPIO37 37 +#define PAD_GPIO38 38 +#define PAD_GPIO39 39 +#define PAD_GPIO40 40 +#define PAD_GPIO41 41 +#define PAD_GPIO42 42 +#define PAD_GPIO43 43 +#define PAD_GPIO44 44 +#define PAD_GPIO45 45 +#define PAD_GPIO46 46 +#define PAD_GPIO47 47 +#define PAD_GPIO48 48 +#define PAD_GPIO49 49 +#define PAD_GPIO50 50 +#define PAD_GPIO51 51 +#define PAD_GPIO52 52 +#define PAD_GPIO53 53 +#define PAD_GPIO54 54 +#define PAD_GPIO55 55 +#define PAD_GPIO56 56 +#define PAD_GPIO57 57 +#define PAD_GPIO58 58 +#define PAD_GPIO59 59 +#define PAD_GPIO60 60 +#define PAD_GPIO61 61 +#define PAD_GPIO62 62 +#define PAD_GPIO63 63 +#define PAD_SD0_CLK 64 +#define PAD_SD0_CMD 65 +#define PAD_SD0_DATA0 66 +#define PAD_SD0_DATA1 67 +#define PAD_SD0_DATA2 68 +#define PAD_SD0_DATA3 69 +#define PAD_SD0_DATA4 70 +#define PAD_SD0_DATA5 71 +#define PAD_SD0_DATA6 72 +#define PAD_SD0_DATA7 73 +#define PAD_SD0_STRB 74 +#define PAD_GMAC1_MDC 75 +#define PAD_GMAC1_MDIO 76 +#define PAD_GMAC1_RXD0 77 +#define PAD_GMAC1_RXD1 78 +#define PAD_GMAC1_RXD2 79 +#define PAD_GMAC1_RXD3 80 +#define PAD_GMAC1_RXDV 81 +#define PAD_GMAC1_RXC 82 +#define PAD_GMAC1_TXD0 83 +#define PAD_GMAC1_TXD1 84 +#define PAD_GMAC1_TXD2 85 +#define PAD_GMAC1_TXD3 86 +#define PAD_GMAC1_TXEN 87 +#define PAD_GMAC1_TXC 88 +#define PAD_QSPI_SCLK 89 +#define PAD_QSPI_CSn0 90 +#define PAD_QSPI_DATA0 91 +#define PAD_QSPI_DATA1 92 +#define PAD_QSPI_DATA2 93 +#define PAD_QSPI_DATA3 94 + +#define GPO_LOW 0 +#define GPO_HIGH 1 +#define GPO_WAVE511_0_O_UART_TXSOUT 2 +#define GPO_CAN0_CTRL_STBY 3 +#define GPO_CAN0_CTRL_TST_NEXT_BIT 4 +#define GPO_CAN0_CTRL_TST_SAMPLE_POINT 5 +#define GPO_CAN0_CTRL_TXD 6 +#define GPO_USB0_DRIVE_VBUS_IO 7 +#define GPO_QSPI0_CSN1 8 +#define GPO_SPDIF0_SPDIFO 9 +#define GPO_HDMI0_CEC_SDA_OUT 10 +#define GPO_HDMI0_DDC_SCL_OUT 11 +#define GPO_HDMI0_DDC_SDA_OUT 12 +#define GPO_WDT0_WDOGRES 13 +#define GPO_I2C0_IC_CLK_OUT_A 14 +#define GPO_I2C0_IC_DATA_OUT_A 15 +#define GPO_SDIO0_BACK_END_POWER 16 +#define GPO_SDIO0_CARD_POWER_EN 17 +#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N 18 +#define GPO_SDIO0_RST_N 19 +#define GPO_UART0_SOUT 20 +#define GPO_JTAG_DSP_TDO 21 +#define GPO_JTAG_CPU_CERTIFICATION_TDO 22 +#define GPO_PDM_4MIC0_DMIC_MCLK 23 +#define GPO_PTC0_PWM_0 24 +#define GPO_PTC0_PWM_1 25 +#define GPO_PTC0_PWM_2 26 +#define GPO_PTC0_PWM_3 27 +#define GPO_PWMDAC0_LEFT_OUTPUT 28 +#define GPO_PWMDAC0_RIGHT_OUTPUT 29 +#define GPO_SPI0_SSPCLKOUT 30 +#define GPO_SPI0_SSPFSSOUT 31 +#define GPO_SPI0_SSPTXD 32 +#define GPO_GMAC0_CLK_PHY 33 +#define GPO_I2SRX0_BCLK_MST 34 +#define GPO_I2SRX0_LRCK_MST 35 +#define GPO_I2STX0_BCLK_MST 36 +#define GPO_I2STX0_LRCK_MST 37 +#define GPO_CRG0_MCLK_OUT 38 +#define GPO_TDM0_CLK_MST 39 +#define GPO_TDM0_PCM_SYNCOUT 40 +#define GPO_TDM0_PCM_TXD 41 +#define GPO_U7MC_TRACE0_TDATA_0 42 +#define GPO_U7MC_TRACE0_TDATA_1 43 +#define GPO_U7MC_TRACE0_TDATA_2 44 +#define GPO_U7MC_TRACE0_TDATA_3 45 +#define GPO_U7MC_TRACE0_TREF 46 +#define GPO_CAN1_CTRL_STBY 47 +#define GPO_CAN1_CTRL_TST_NEXT_BIT 48 +#define GPO_CAN1_CTRL_TST_SAMPLE_POINT 49 +#define GPO_CAN1_CTRL_TXD 50 +#define GPO_I2C1_IC_CLK_OUT_A 51 +#define GPO_I2C1_IC_DATA_OUT_A 52 +#define GPO_SDIO1_BACK_END_POWER 53 +#define GPO_SDIO1_CARD_POWER_EN 54 +#define GPO_SDIO1_CCLK_OUT 55 +#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N 56 +#define GPO_SDIO1_CCMD_OUT 57 +#define GPO_SDIO1_CDATA_OUT_0 58 +#define GPO_SDIO1_CDATA_OUT_1 59 +#define GPO_SDIO1_CDATA_OUT_2 60 +#define GPO_SDIO1_CDATA_OUT_3 61 +#define GPO_SDIO1_CDATA_OUT_4 62 +#define GPO_SDIO1_CDATA_OUT_5 63 +#define GPO_SDIO1_CDATA_OUT_6 64 +#define GPO_SDIO1_CDATA_OUT_7 65 +#define GPO_SDIO1_RST_N 66 +#define GPO_UART1_RTS_N 67 +#define GPO_UART1_SOUT 68 +#define GPO_I2STX_4CH1_SDO0 69 +#define GPO_I2STX_4CH1_SDO1 70 +#define GPO_I2STX_4CH1_SDO2 71 +#define GPO_I2STX_4CH1_SDO3 72 +#define GPO_SPI1_SSPCLKOUT 73 +#define GPO_SPI1_SSPFSSOUT 74 +#define GPO_SPI1_SSPTXD 75 +#define GPO_I2C2_IC_CLK_OUT_A 76 +#define GPO_I2C2_IC_DATA_OUT_A 77 +#define GPO_UART2_RTS_N 78 +#define GPO_UART2_SOUT 79 +#define GPO_SPI2_SSPCLKOUT 80 +#define GPO_SPI2_SSPFSSOUT 81 +#define GPO_SPI2_SSPTXD 82 +#define GPO_I2C3_IC_CLK_OUT_A 83 +#define GPO_I2C3_IC_DATA_OUT_A 84 +#define GPO_UART3_SOUT 85 +#define GPO_SPI3_SSPCLKOUT 86 +#define GPO_SPI3_SSPFSSOUT 87 +#define GPO_SPI3_SSPTXD 88 +#define GPO_I2C4_IC_CLK_OUT_A 89 +#define GPO_I2C4_IC_DATA_OUT_A 90 +#define GPO_UART4_RTS_N 91 +#define GPO_UART4_SOUT 92 +#define GPO_SPI4_SSPCLKOUT 93 +#define GPO_SPI4_SSPFSSOUT 94 +#define GPO_SPI4_SSPTXD 95 +#define GPO_I2C5_IC_CLK_OUT_A 96 +#define GPO_I2C5_IC_DATA_OUT_A 97 +#define GPO_UART5_RTS_N 98 +#define GPO_UART5_SOUT 99 +#define GPO_SPI5_SSPCLKOUT 100 +#define GPO_SPI5_SSPFSSOUT 101 +#define GPO_SPI5_SSPTXD 102 +#define GPO_I2C6_IC_CLK_OUT_A 103 +#define GPO_I2C6_IC_DATA_OUT_A 104 +#define GPO_SPI6_SSPCLKOUT 105 +#define GPO_SPI6_SSPFSSOUT 106 +#define GPO_SPI6_SSPTXD 107 +#define GPO_NONE 108 + +#define OEN_LOW 0 +#define OEN_HIGH 1 +#define OEN_HDMI0_CEC_SDA_OEN 2 +#define OEN_HDMI0_DDC_SCL_OEN 3 +#define OEN_HDMI0_DDC_SDA_OEN 4 +#define OEN_I2C0_IC_CLK_OE 5 +#define OEN_I2C0_IC_DATA_OE 6 +#define OEN_JTAG_DSP_TDO_OEN 7 +#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE 8 +#define OEN_PTC0_PWM_0_OE_N 9 +#define OEN_PTC0_PWM_1_OE_N 10 +#define OEN_PTC0_PWM_2_OE_N 11 +#define OEN_PTC0_PWM_3_OE_N 12 +#define OEN_SPI0_NSSPCTLOE 13 +#define OEN_SPI0_NSSPOE 14 +#define OEN_TDM0_NPCM_SYNCOE 15 +#define OEN_TDM0_NPCM_TXDOE 16 +#define OEN_I2C1_IC_CLK_OE 17 +#define OEN_I2C1_IC_DATA_OE 18 +#define OEN_SDIO1_CCMD_OUT_EN 19 +#define OEN_SDIO1_CDATA_OUT_EN_0 20 +#define OEN_SDIO1_CDATA_OUT_EN_1 21 +#define OEN_SDIO1_CDATA_OUT_EN_2 22 +#define OEN_SDIO1_CDATA_OUT_EN_3 23 +#define OEN_SDIO1_CDATA_OUT_EN_4 24 +#define OEN_SDIO1_CDATA_OUT_EN_5 25 +#define OEN_SDIO1_CDATA_OUT_EN_6 26 +#define OEN_SDIO1_CDATA_OUT_EN_7 27 +#define OEN_SPI1_NSSPCTLOE 28 +#define OEN_SPI1_NSSPOE 29 +#define OEN_I2C2_IC_CLK_OE 30 +#define OEN_I2C2_IC_DATA_OE 31 +#define OEN_SPI2_NSSPCTLOE 32 +#define OEN_SPI2_NSSPOE 33 +#define OEN_I2C3_IC_CLK_OE 34 +#define OEN_I2C3_IC_DATA_OE 35 +#define OEN_SPI3_NSSPCTLOE 36 +#define OEN_SPI3_NSSPOE 37 +#define OEN_I2C4_IC_CLK_OE 38 +#define OEN_I2C4_IC_DATA_OE 39 +#define OEN_SPI4_NSSPCTLOE 40 +#define OEN_SPI4_NSSPOE 41 +#define OEN_I2C5_IC_CLK_OE 42 +#define OEN_I2C5_IC_DATA_OE 43 +#define OEN_SPI5_NSSPCTLOE 44 +#define OEN_SPI5_NSSPOE 45 +#define OEN_I2C6_IC_CLK_OE 46 +#define OEN_I2C6_IC_DATA_OE 47 +#define OEN_SPI6_NSSPCTLOE 48 +#define OEN_SPI6_NSSPOE 49 +#define OEN_NONE 50 + +#define GPI_WAVE511_0_I_UART_RXSIN 0 +#define GPI_CAN0_CTRL_RXD 1 +#define GPI_USB0_OVERCURRENT_N_IO 2 +#define GPI_SPDIF0_SPDIFI 3 +#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN 4 +#define GPI_HDMI0_CEC_SDA_IN 5 +#define GPI_HDMI0_DDC_SCL_IN 6 +#define GPI_HDMI0_DDC_SDA_IN 7 +#define GPI_HDMI0_HPD 8 +#define GPI_I2C0_IC_CLK_IN_A 9 +#define GPI_I2C0_IC_DATA_IN_A 10 +#define GPI_SDIO0_CARD_DETECT_N 11 +#define GPI_SDIO0_CARD_INT_N 12 +#define GPI_SDIO0_CARD_WRITE_PRT 13 +#define GPI_UART0_SIN 14 +#define GPI_JTAG_DSP_TCK 15 +#define GPI_JTAG_DSP_TDI 16 +#define GPI_JTAG_DSP_TMS 17 +#define GPI_JTAG_DSP_TRST_N 18 +#define GPI_JTAG_CPU_CERTIFICATION_TDI 19 +#define GPI_JTAG_CPU_CERTIFICATION_TMS 20 +#define GPI_PDM_4MIC0_DMIC0_DIN 21 +#define GPI_PDM_4MIC0_DMIC1_DIN 22 +#define GPI_I2SRX0_EXT_SDIN0 23 +#define GPI_I2SRX0_EXT_SDIN1 24 +#define GPI_I2SRX0_EXT_SDIN2 25 +#define GPI_SPI0_SSPCLKIN 26 +#define GPI_SPI0_SSPFSSIN 27 +#define GPI_SPI0_SSPRXD 28 +#define GPI_JTAG_CPU_CERTIFICATION_TCK 29 +#define GPI_CRG0_EXT_MCLK 30 +#define GPI_I2SRX0_BCLK_SLV 31 +#define GPI_I2SRX0_LRCK_SLV 32 +#define GPI_I2STX0_BCLK_SLV 33 +#define GPI_I2STX0_LRCK_SLV 34 +#define GPI_TDM0_CLK_SLV 35 +#define GPI_TDM0_PCM_RXD 36 +#define GPI_TDM0_PCM_SYNCIN 37 +#define GPI_CAN1_CTRL_RXD 38 +#define GPI_I2C1_IC_CLK_IN_A 39 +#define GPI_I2C1_IC_DATA_IN_A 40 +#define GPI_SDIO1_CARD_DETECT_N 41 +#define GPI_SDIO1_CARD_INT_N 42 +#define GPI_SDIO1_CARD_WRITE_PRT 43 +#define GPI_SDIO1_CCMD_IN 44 +#define GPI_SDIO1_CDATA_IN_0 45 +#define GPI_SDIO1_CDATA_IN_1 46 +#define GPI_SDIO1_CDATA_IN_2 47 +#define GPI_SDIO1_CDATA_IN_3 48 +#define GPI_SDIO1_CDATA_IN_4 49 +#define GPI_SDIO1_CDATA_IN_5 50 +#define GPI_SDIO1_CDATA_IN_6 51 +#define GPI_SDIO1_CDATA_IN_7 52 +#define GPI_SDIO1_DATA_STROBE 53 +#define GPI_UART1_CTS_N 54 +#define GPI_UART1_SIN 55 +#define GPI_SPI1_SSPCLKIN 56 +#define GPI_SPI1_SSPFSSIN 57 +#define GPI_SPI1_SSPRXD 58 +#define GPI_I2C2_IC_CLK_IN_A 59 +#define GPI_I2C2_IC_DATA_IN_A 60 +#define GPI_UART2_CTS_N 61 +#define GPI_UART2_SIN 62 +#define GPI_SPI2_SSPCLKIN 63 +#define GPI_SPI2_SSPFSSIN 64 +#define GPI_SPI2_SSPRXD 65 +#define GPI_I2C3_IC_CLK_IN_A 66 +#define GPI_I2C3_IC_DATA_IN_A 67 +#define GPI_UART3_SIN 68 +#define GPI_SPI3_SSPCLKIN 69 +#define GPI_SPI3_SSPFSSIN 70 +#define GPI_SPI3_SSPRXD 71 +#define GPI_I2C4_IC_CLK_IN_A 72 +#define GPI_I2C4_IC_DATA_IN_A 73 +#define GPI_UART4_CTS_N 74 +#define GPI_UART4_SIN 75 +#define GPI_SPI4_SSPCLKIN 76 +#define GPI_SPI4_SSPFSSIN 77 +#define GPI_SPI4_SSPRXD 78 +#define GPI_I2C5_IC_CLK_IN_A 79 +#define GPI_I2C5_IC_DATA_IN_A 80 +#define GPI_UART5_CTS_N 81 +#define GPI_UART5_SIN 82 +#define GPI_SPI5_SSPCLKIN 83 +#define GPI_SPI5_SSPFSSIN 84 +#define GPI_SPI5_SSPRXD 85 +#define GPI_I2C6_IC_CLK_IN_A 86 +#define GPI_I2C6_IC_DATA_IN_A 87 +#define GPI_SPI6_SSPCLKIN 88 +#define GPI_SPI6_SSPFSSIN 89 +#define GPI_SPI6_SSPRXD 90 +#define GPI_NONE 91 + +/* sys_iomux syscon */ +#define PADCFG_PAD_GMAC1_MDC_SYSCON 0x24c +#define PADCFG_PAD_GMAC1_MDIO_SYSCON 0x250 +#define PADCFG_PAD_GMAC1_RXD0_SYSCON 0x254 +#define PADCFG_PAD_GMAC1_RXD1_SYSCON 0x258 +#define PADCFG_PAD_GMAC1_RXD2_SYSCON 0x25c +#define PADCFG_PAD_GMAC1_RXD3_SYSCON 0x260 +#define PADCFG_PAD_GMAC1_RXDV_SYSCON 0x264 +#define PADCFG_PAD_GMAC1_RXC_SYSCON 0x268 +#define PADCFG_PAD_GMAC1_TXD0_SYSCON 0x26c +#define PADCFG_PAD_GMAC1_TXD1_SYSCON 0x270 +#define PADCFG_PAD_GMAC1_TXD2_SYSCON 0x274 +#define PADCFG_PAD_GMAC1_TXD3_SYSCON 0x278 +#define PADCFG_PAD_GMAC1_TXEN_SYSCON 0x27c +#define PADCFG_PAD_GMAC1_TXC_SYSCON 0x280 + +/* sys_iomux func sel setting */ +#define SYS_IOMUX_CFGSAIF_668_ADDR 0x29c +#define PAD_GMAC1_RXC_FUNC_SEL_SHIFT 0x0 +#define PAD_GMAC1_RXC_FUNC_SEL_MASK 0x3 +#define PAD_GPIO10_FUNC_SEL_SHIFT 0x2 +#define PAD_GPIO10_FUNC_SEL_MASK 0x1C +#define PAD_GPIO11_FUNC_SEL_SHIFT 0x5 +#define PAD_GPIO11_FUNC_SEL_MASK 0xE0 +#define PAD_GPIO12_FUNC_SEL_SHIFT 0x8 +#define PAD_GPIO12_FUNC_SEL_MASK 0x700 +#define PAD_GPIO13_FUNC_SEL_SHIFT 0xB +#define PAD_GPIO13_FUNC_SEL_MASK 0x3800 +#define PAD_GPIO14_FUNC_SEL_SHIFT 0xE +#define PAD_GPIO14_FUNC_SEL_MASK 0x1C000 +#define PAD_GPIO15_FUNC_SEL_SHIFT 0x11 +#define PAD_GPIO15_FUNC_SEL_MASK 0xE0000 +#define PAD_GPIO16_FUNC_SEL_SHIFT 0x14 +#define PAD_GPIO16_FUNC_SEL_MASK 0x700000 +#define PAD_GPIO17_FUNC_SEL_SHIFT 0x17 +#define PAD_GPIO17_FUNC_SEL_MASK 0x3800000 +#define PAD_GPIO18_FUNC_SEL_SHIFT 0x1A +#define PAD_GPIO18_FUNC_SEL_MASK 0x1C000000 +#define PAD_GPIO19_FUNC_SEL_SHIFT 0x1D +#define PAD_GPIO19_FUNC_SEL_MASK 0xE0000000 +#define SYS_IOMUX_CFGSAIF_672_ADDR 0x2a0 +#define PAD_GPIO20_FUNC_SEL_SHIFT 0x0 +#define PAD_GPIO20_FUNC_SEL_MASK 0x7 +#define PAD_GPIO21_FUNC_SEL_SHIFT 0x3 +#define PAD_GPIO21_FUNC_SEL_MASK 0x38 +#define PAD_GPIO22_FUNC_SEL_SHIFT 0x6 +#define PAD_GPIO22_FUNC_SEL_MASK 0x1C0 +#define PAD_GPIO23_FUNC_SEL_SHIFT 0x9 +#define PAD_GPIO23_FUNC_SEL_MASK 0xE00 +#define PAD_GPIO24_FUNC_SEL_SHIFT 0xC +#define PAD_GPIO24_FUNC_SEL_MASK 0x7000 +#define PAD_GPIO25_FUNC_SEL_SHIFT 0xF +#define PAD_GPIO25_FUNC_SEL_MASK 0x38000 +#define PAD_GPIO26_FUNC_SEL_SHIFT 0x12 +#define PAD_GPIO26_FUNC_SEL_MASK 0x1C0000 +#define PAD_GPIO27_FUNC_SEL_SHIFT 0x15 +#define PAD_GPIO27_FUNC_SEL_MASK 0xE00000 +#define PAD_GPIO28_FUNC_SEL_SHIFT 0x18 +#define PAD_GPIO28_FUNC_SEL_MASK 0x7000000 +#define PAD_GPIO29_FUNC_SEL_SHIFT 0x1B +#define PAD_GPIO29_FUNC_SEL_MASK 0x38000000 +#define SYS_IOMUX_CFGSAIF_676_ADDR 0x2a4 +#define PAD_GPIO30_FUNC_SEL_SHIFT 0x0 +#define PAD_GPIO30_FUNC_SEL_MASK 0x7 +#define PAD_GPIO31_FUNC_SEL_SHIFT 0x3 +#define PAD_GPIO31_FUNC_SEL_MASK 0x38 +#define PAD_GPIO32_FUNC_SEL_SHIFT 0x6 +#define PAD_GPIO32_FUNC_SEL_MASK 0x1C0 +#define PAD_GPIO33_FUNC_SEL_SHIFT 0x9 +#define PAD_GPIO33_FUNC_SEL_MASK 0xE00 +#define PAD_GPIO34_FUNC_SEL_SHIFT 0xC +#define PAD_GPIO34_FUNC_SEL_MASK 0x7000 +#define PAD_GPIO35_FUNC_SEL_SHIFT 0xF +#define PAD_GPIO35_FUNC_SEL_MASK 0x18000 +#define PAD_GPIO36_FUNC_SEL_SHIFT 0x11 +#define PAD_GPIO36_FUNC_SEL_MASK 0xE0000 +#define PAD_GPIO37_FUNC_SEL_SHIFT 0x14 +#define PAD_GPIO37_FUNC_SEL_MASK 0x700000 +#define PAD_GPIO38_FUNC_SEL_SHIFT 0x17 +#define PAD_GPIO38_FUNC_SEL_MASK 0x3800000 +#define PAD_GPIO39_FUNC_SEL_SHIFT 0x1A +#define PAD_GPIO39_FUNC_SEL_MASK 0x1C000000 +#define PAD_GPIO40_FUNC_SEL_SHIFT 0x1D +#define PAD_GPIO40_FUNC_SEL_MASK 0xE0000000 +#define SYS_IOMUX_CFGSAIF_680_ADDR 0x2a8 +#define PAD_GPIO41_FUNC_SEL_SHIFT 0x0 +#define PAD_GPIO41_FUNC_SEL_MASK 0x7 +#define PAD_GPIO42_FUNC_SEL_SHIFT 0x3 +#define PAD_GPIO42_FUNC_SEL_MASK 0x38 +#define PAD_GPIO43_FUNC_SEL_SHIFT 0x6 +#define PAD_GPIO43_FUNC_SEL_MASK 0x1C0 +#define PAD_GPIO44_FUNC_SEL_SHIFT 0x9 +#define PAD_GPIO44_FUNC_SEL_MASK 0xE00 +#define PAD_GPIO45_FUNC_SEL_SHIFT 0xC +#define PAD_GPIO45_FUNC_SEL_MASK 0x7000 +#define PAD_GPIO46_FUNC_SEL_SHIFT 0xF +#define PAD_GPIO46_FUNC_SEL_MASK 0x38000 +#define PAD_GPIO47_FUNC_SEL_SHIFT 0x12 +#define PAD_GPIO47_FUNC_SEL_MASK 0x1C0000 +#define PAD_GPIO48_FUNC_SEL_SHIFT 0x15 +#define PAD_GPIO48_FUNC_SEL_MASK 0xE00000 +#define PAD_GPIO49_FUNC_SEL_SHIFT 0x18 +#define PAD_GPIO49_FUNC_SEL_MASK 0x7000000 +#define PAD_GPIO50_FUNC_SEL_SHIFT 0x1B +#define PAD_GPIO50_FUNC_SEL_MASK 0x38000000 +#define PAD_GPIO51_FUNC_SEL_SHIFT 0x1E +#define PAD_GPIO51_FUNC_SEL_MASK 0xC0000000 +#define SYS_IOMUX_CFGSAIF_684_ADDR 0x2ac +#define PAD_GPIO52_FUNC_SEL_SHIFT 0x0 +#define PAD_GPIO52_FUNC_SEL_MASK 0x3 +#define PAD_GPIO53_FUNC_SEL_SHIFT 0x2 +#define PAD_GPIO53_FUNC_SEL_MASK 0xC +#define PAD_GPIO54_FUNC_SEL_SHIFT 0x4 +#define PAD_GPIO54_FUNC_SEL_MASK 0x30 +#define PAD_GPIO55_FUNC_SEL_SHIFT 0x6 +#define PAD_GPIO55_FUNC_SEL_MASK 0x1C0 +#define PAD_GPIO56_FUNC_SEL_SHIFT 0x9 +#define PAD_GPIO56_FUNC_SEL_MASK 0xE00 +#define PAD_GPIO57_FUNC_SEL_SHIFT 0xC +#define PAD_GPIO57_FUNC_SEL_MASK 0x7000 +#define PAD_GPIO58_FUNC_SEL_SHIFT 0xF +#define PAD_GPIO58_FUNC_SEL_MASK 0x38000 +#define PAD_GPIO59_FUNC_SEL_SHIFT 0x12 +#define PAD_GPIO59_FUNC_SEL_MASK 0x1C0000 +#define PAD_GPIO60_FUNC_SEL_SHIFT 0x15 +#define PAD_GPIO60_FUNC_SEL_MASK 0xE00000 +#define PAD_GPIO61_FUNC_SEL_SHIFT 0x18 +#define PAD_GPIO61_FUNC_SEL_MASK 0x7000000 +#define PAD_GPIO62_FUNC_SEL_SHIFT 0x1B +#define PAD_GPIO62_FUNC_SEL_MASK 0x38000000 +#define PAD_GPIO63_FUNC_SEL_SHIFT 0x1E +#define PAD_GPIO63_FUNC_SEL_MASK 0xC0000000 +#define SYS_IOMUX_CFGSAIF_688_ADDR 0x2b0 +#define PAD_GPIO6_FUNC_SEL_SHIFT 0x0 +#define PAD_GPIO6_FUNC_SEL_MASK 0x3 +#define PAD_GPIO7_FUNC_SEL_SHIFT 0x2 +#define PAD_GPIO7_FUNC_SEL_MASK 0x1C +#define PAD_GPIO8_FUNC_SEL_SHIFT 0x5 +#define PAD_GPIO8_FUNC_SEL_MASK 0xE0 +#define PAD_GPIO9_FUNC_SEL_SHIFT 0x8 +#define PAD_GPIO9_FUNC_SEL_MASK 0x700 +#define ISP_VIN_DVP_DATA0_FUNC_SEL_SHIFT 0xB +#define ISP_VIN_DVP_DATA0_FUNC_SEL_MASK 0x3800 +#define ISP_VIN_DVP_DATA10_FUNC_SEL_SHIFT 0xE +#define ISP_VIN_DVP_DATA10_FUNC_SEL_MASK 0x1C000 +#define ISP_VIN_DVP_DATA11_FUNC_SEL_SHIFT 0x11 +#define ISP_VIN_DVP_DATA11_FUNC_SEL_MASK 0xE0000 +#define ISP_VIN_DVP_DATA1_FUNC_SEL_SHIFT 0x14 +#define ISP_VIN_DVP_DATA1_FUNC_SEL_MASK 0x700000 +#define ISP_VIN_DVP_DATA2_FUNC_SEL_SHIFT 0x17 +#define ISP_VIN_DVP_DATA2_FUNC_SEL_MASK 0x3800000 +#define ISP_VIN_DVP_DATA3_FUNC_SEL_SHIFT 0x1A +#define ISP_VIN_DVP_DATA3_FUNC_SEL_MASK 0x1C000000 +#define ISP_VIN_DVP_DATA4_FUNC_SEL_SHIFT 0x1D +#define ISP_VIN_DVP_DATA4_FUNC_SEL_MASK 0xE0000000 +#define SYS_IOMUX_CFGSAIF_692_ADDR 0x2b4 +#define ISP_VIN_DVP_DATA5_FUNC_SEL_SHIFT 0x0 +#define ISP_VIN_DVP_DATA5_FUNC_SEL_MASK 0x7 +#define ISP_VIN_DVP_DATA6_FUNC_SEL_SHIFT 0x3 +#define ISP_VIN_DVP_DATA6_FUNC_SEL_MASK 0x38 +#define ISP_VIN_DVP_DATA7_FUNC_SEL_SHIFT 0x6 +#define ISP_VIN_DVP_DATA7_FUNC_SEL_MASK 0x1C0 +#define ISP_VIN_DVP_DATA8_FUNC_SEL_SHIFT 0x9 +#define ISP_VIN_DVP_DATA8_FUNC_SEL_MASK 0xE00 +#define ISP_VIN_DVP_DATA9_FUNC_SEL_SHIFT 0xC +#define ISP_VIN_DVP_DATA9_FUNC_SEL_MASK 0x7000 +#define ISP_VIN_DVP_HVALID_FUNC_SEL_SHIFT 0xF +#define ISP_VIN_DVP_HVALID_FUNC_SEL_MASK 0x38000 +#define ISP_VIN_DVP_VVALID_FUNC_SEL_SHIFT 0x12 +#define ISP_VIN_DVP_VVALID_FUNC_SEL_MASK 0x1C0000 +#define DVP_CLK_FUNC_SEL_SHIFT 0x15 +#define DVP_CLK_FUNC_SEL_MASK 0xE00000 + +#define PAD_GMAC1_RXC_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GMAC1_RXC_FUNC_SEL_SHIFT \ + PAD_GMAC1_RXC_FUNC_SEL_MASK +#define PAD_GPIO10_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO10_FUNC_SEL_SHIFT \ + PAD_GPIO10_FUNC_SEL_MASK +#define PAD_GPIO11_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO11_FUNC_SEL_SHIFT \ + PAD_GPIO11_FUNC_SEL_MASK +#define PAD_GPIO12_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO12_FUNC_SEL_SHIFT \ + PAD_GPIO12_FUNC_SEL_MASK +#define PAD_GPIO13_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO13_FUNC_SEL_SHIFT \ + PAD_GPIO13_FUNC_SEL_MASK +#define PAD_GPIO14_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO14_FUNC_SEL_SHIFT \ + PAD_GPIO14_FUNC_SEL_MASK +#define PAD_GPIO15_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO15_FUNC_SEL_SHIFT \ + PAD_GPIO15_FUNC_SEL_MASK +#define PAD_GPIO16_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO16_FUNC_SEL_SHIFT \ + PAD_GPIO16_FUNC_SEL_MASK +#define PAD_GPIO17_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO17_FUNC_SEL_SHIFT \ + PAD_GPIO17_FUNC_SEL_MASK +#define PAD_GPIO18_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO18_FUNC_SEL_SHIFT \ + PAD_GPIO18_FUNC_SEL_MASK +#define PAD_GPIO19_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_668_ADDR \ + PAD_GPIO19_FUNC_SEL_SHIFT \ + PAD_GPIO19_FUNC_SEL_MASK +#define PAD_GPIO20_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO20_FUNC_SEL_SHIFT \ + PAD_GPIO20_FUNC_SEL_MASK +#define PAD_GPIO21_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO21_FUNC_SEL_SHIFT \ + PAD_GPIO21_FUNC_SEL_MASK +#define PAD_GPIO22_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO22_FUNC_SEL_SHIFT \ + PAD_GPIO22_FUNC_SEL_MASK +#define PAD_GPIO23_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO23_FUNC_SEL_SHIFT \ + PAD_GPIO23_FUNC_SEL_MASK +#define PAD_GPIO24_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO24_FUNC_SEL_SHIFT \ + PAD_GPIO24_FUNC_SEL_MASK +#define PAD_GPIO25_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO25_FUNC_SEL_SHIFT \ + PAD_GPIO25_FUNC_SEL_MASK +#define PAD_GPIO26_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO26_FUNC_SEL_SHIFT \ + PAD_GPIO26_FUNC_SEL_MASK +#define PAD_GPIO27_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO27_FUNC_SEL_SHIFT \ + PAD_GPIO27_FUNC_SEL_MASK +#define PAD_GPIO28_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO28_FUNC_SEL_SHIFT \ + PAD_GPIO28_FUNC_SEL_MASK +#define PAD_GPIO29_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_672_ADDR \ + PAD_GPIO29_FUNC_SEL_SHIFT \ + PAD_GPIO29_FUNC_SEL_MASK +#define PAD_GPIO30_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO30_FUNC_SEL_SHIFT \ + PAD_GPIO30_FUNC_SEL_MASK +#define PAD_GPIO31_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO31_FUNC_SEL_SHIFT \ + PAD_GPIO31_FUNC_SEL_MASK +#define PAD_GPIO32_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO32_FUNC_SEL_SHIFT \ + PAD_GPIO32_FUNC_SEL_MASK +#define PAD_GPIO33_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO33_FUNC_SEL_SHIFT \ + PAD_GPIO33_FUNC_SEL_MASK +#define PAD_GPIO34_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO34_FUNC_SEL_SHIFT \ + PAD_GPIO34_FUNC_SEL_MASK +#define PAD_GPIO35_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO35_FUNC_SEL_SHIFT \ + PAD_GPIO35_FUNC_SEL_MASK +#define PAD_GPIO36_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO36_FUNC_SEL_SHIFT \ + PAD_GPIO36_FUNC_SEL_MASK +#define PAD_GPIO37_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO37_FUNC_SEL_SHIFT \ + PAD_GPIO37_FUNC_SEL_MASK +#define PAD_GPIO38_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO38_FUNC_SEL_SHIFT \ + PAD_GPIO38_FUNC_SEL_MASK +#define PAD_GPIO39_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO39_FUNC_SEL_SHIFT \ + PAD_GPIO39_FUNC_SEL_MASK +#define PAD_GPIO40_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_676_ADDR \ + PAD_GPIO40_FUNC_SEL_SHIFT \ + PAD_GPIO40_FUNC_SEL_MASK +#define PAD_GPIO41_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO41_FUNC_SEL_SHIFT \ + PAD_GPIO41_FUNC_SEL_MASK +#define PAD_GPIO42_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO42_FUNC_SEL_SHIFT \ + PAD_GPIO42_FUNC_SEL_MASK +#define PAD_GPIO43_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO43_FUNC_SEL_SHIFT \ + PAD_GPIO43_FUNC_SEL_MASK +#define PAD_GPIO44_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO44_FUNC_SEL_SHIFT \ + PAD_GPIO44_FUNC_SEL_MASK +#define PAD_GPIO45_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO45_FUNC_SEL_SHIFT \ + PAD_GPIO45_FUNC_SEL_MASK +#define PAD_GPIO46_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO46_FUNC_SEL_SHIFT \ + PAD_GPIO46_FUNC_SEL_MASK +#define PAD_GPIO47_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO47_FUNC_SEL_SHIFT \ + PAD_GPIO47_FUNC_SEL_MASK +#define PAD_GPIO48_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO48_FUNC_SEL_SHIFT \ + PAD_GPIO48_FUNC_SEL_MASK +#define PAD_GPIO49_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO49_FUNC_SEL_SHIFT \ + PAD_GPIO49_FUNC_SEL_MASK +#define PAD_GPIO50_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO50_FUNC_SEL_SHIFT \ + PAD_GPIO50_FUNC_SEL_MASK +#define PAD_GPIO51_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_680_ADDR \ + PAD_GPIO51_FUNC_SEL_SHIFT \ + PAD_GPIO51_FUNC_SEL_MASK +#define PAD_GPIO52_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO52_FUNC_SEL_SHIFT \ + PAD_GPIO52_FUNC_SEL_MASK +#define PAD_GPIO53_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO53_FUNC_SEL_SHIFT \ + PAD_GPIO53_FUNC_SEL_MASK +#define PAD_GPIO54_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO54_FUNC_SEL_SHIFT \ + PAD_GPIO54_FUNC_SEL_MASK +#define PAD_GPIO55_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO55_FUNC_SEL_SHIFT \ + PAD_GPIO55_FUNC_SEL_MASK +#define PAD_GPIO56_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO56_FUNC_SEL_SHIFT \ + PAD_GPIO56_FUNC_SEL_MASK +#define PAD_GPIO57_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO57_FUNC_SEL_SHIFT \ + PAD_GPIO57_FUNC_SEL_MASK +#define PAD_GPIO58_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO58_FUNC_SEL_SHIFT \ + PAD_GPIO58_FUNC_SEL_MASK +#define PAD_GPIO59_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO59_FUNC_SEL_SHIFT \ + PAD_GPIO59_FUNC_SEL_MASK +#define PAD_GPIO60_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO60_FUNC_SEL_SHIFT \ + PAD_GPIO60_FUNC_SEL_MASK +#define PAD_GPIO61_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO61_FUNC_SEL_SHIFT \ + PAD_GPIO61_FUNC_SEL_MASK +#define PAD_GPIO62_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO62_FUNC_SEL_SHIFT \ + PAD_GPIO62_FUNC_SEL_MASK +#define PAD_GPIO63_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_684_ADDR \ + PAD_GPIO63_FUNC_SEL_SHIFT \ + PAD_GPIO63_FUNC_SEL_MASK +#define PAD_GPIO6_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + PAD_GPIO6_FUNC_SEL_SHIFT \ + PAD_GPIO6_FUNC_SEL_MASK +#define PAD_GPIO7_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + PAD_GPIO7_FUNC_SEL_SHIFT \ + PAD_GPIO7_FUNC_SEL_MASK +#define PAD_GPIO8_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + PAD_GPIO8_FUNC_SEL_SHIFT \ + PAD_GPIO8_FUNC_SEL_MASK +#define PAD_GPIO9_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + PAD_GPIO9_FUNC_SEL_SHIFT \ + PAD_GPIO9_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA0_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + ISP_VIN_DVP_DATA0_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA0_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA10_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + ISP_VIN_DVP_DATA10_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA10_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA11_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + ISP_VIN_DVP_DATA11_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA11_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA1_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + ISP_VIN_DVP_DATA1_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA1_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA2_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + ISP_VIN_DVP_DATA2_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA2_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA3_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + ISP_VIN_DVP_DATA3_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA3_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA4_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_688_ADDR \ + ISP_VIN_DVP_DATA4_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA4_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA5_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + ISP_VIN_DVP_DATA5_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA5_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA6_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + ISP_VIN_DVP_DATA6_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA6_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA7_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + ISP_VIN_DVP_DATA7_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA7_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA8_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + ISP_VIN_DVP_DATA8_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA8_FUNC_SEL_MASK +#define ISP_VIN_DVP_DATA9_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + ISP_VIN_DVP_DATA9_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_DATA9_FUNC_SEL_MASK +#define ISP_VIN_DVP_HVALID_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + ISP_VIN_DVP_HVALID_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_HVALID_FUNC_SEL_MASK +#define ISP_VIN_DVP_VVALID_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + ISP_VIN_DVP_VVALID_FUNC_SEL_SHIFT \ + ISP_VIN_DVP_VVALID_FUNC_SEL_MASK +#define DVP_CLK_FUNC_SEL \ + SYS_IOMUX_CFGSAIF_692_ADDR \ + DVP_CLK_FUNC_SEL_SHIFT \ + DVP_CLK_FUNC_SEL_MASK + +/* POS[0] */ +#define TESTEN_POS(data) (((data) << 0x0) & 0x1) + +/* SMT[0] POS[1] */ +#define RSTN_SMT(data) (((data) << 0x0) & 0x1) +#define RSTN_POS(data) (((data) << 0x1) & 0x2) + +/* DS[1:0] */ +#define OSC_DS(data) (((data) << 0x0) & 0x3) + +/* sys ioconfig */ +/* IE[0] DS[2:1] PU[3] PD[4] SLEW[5] SMT[6] POS[7] */ +#define GPIO_IE(data) (((data) << 0x0) & 0x1) +#define GPIO_DS(data) (((data) << 0x1) & 0x6) +#define GPIO_PU(data) (((data) << 0x3) & 0x8) +#define GPIO_PD(data) (((data) << 0x4) & 0x7) +#define GPIO_SLEW(data) (((data) << 0x5) & 0x20) +#define GPIO_SMT(data) (((data) << 0x6) & 0x40) +#define GPIO_POS(data) (((data) << 0x7) & 0x80) + +#define IO(config) ((config) & 0xFF) +#define DOUT(dout) ((dout) & 0xFF) +#define DOEN(doen) ((doen) & 0xFF) +#define DIN(din_reg) ((din_reg) & 0xFF) + +/* syscon value */ +#define IO_3_3V 0 /* 00: 3.3v */ +#define IO_2_5V 1 /* 01: 2.5v */ +#define IO_1_8V 2 /* 10: 1.8v */ + +#endif From patchwork Fri Sep 30 07:38:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 611165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ED22C433F5 for ; Fri, 30 Sep 2022 07:41:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbiI3HlN (ORCPT ); Fri, 30 Sep 2022 03:41:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229780AbiI3HlJ (ORCPT ); Fri, 30 Sep 2022 03:41:09 -0400 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.155.67.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F9CB1032E2; Fri, 30 Sep 2022 00:41:04 -0700 (PDT) X-QQ-mid: bizesmtp64t1664523533tfs8q1ju Received: from localhost.localdomain ( [113.72.146.201]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 30 Sep 2022 15:38:51 +0800 (CST) X-QQ-SSF: 01000000000000305000000A0000000 X-QQ-FEAT: k8Irs33ik7vaMfpcnYWCuh3AHagj5K0mh271a0EEiwEVFUL7rSfkc84AaA7xx FgVUPVwT/bikpDFHdgNhxbLCszQfXzRjkBFWClSgjKwYqaFgUEc+6KJehrpi+KbWQOhgJ9D hfDzq8j5+S8X0DeV5We0ny9HZyOuhv2nWBulRgG4Ojbch1Ef9mB8WUs8B/SJI1uvt6ci5C4 C0iwQU7s+ajU5SVtZpib1WaES9ba4RsGW63jrR5XOO6AVPlpWIqwlrdTdq6Y/GuNytIrnE4 aGKYYRTzuqP7U/k12ijT6UMYg9Qr18UwtUWSikyluGgcZG7QyFmcymmM7/7kfVuQSYPdAMR cPQ7PxQIDV6a1ZmNDoHMahsZ6B4QbodHR6LIR2uftqy/MW5Bgf+VvQRNTs7+T7CvQIa1U+g G+A3mq2f1JSSsGDzG8X2+w== X-QQ-GoodBg: 0 From: Hal Feng To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , Hal Feng , linux-kernel@vger.kernel.org Subject: [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings Date: Fri, 30 Sep 2022 15:38:45 +0800 Message-Id: <20220930073845.6309-1-hal.feng@linux.starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:linux.starfivetech.com:qybglogicsvr:qybglogicsvr2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jianlong Huang Add pinctrl bindings for StarFive JH7110 SoC. Signed-off-by: Jianlong Huang Signed-off-by: Hal Feng --- .../pinctrl/starfive,jh7110-pinctrl.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml new file mode 100644 index 000000000000..482012ad8a14 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Pin Controller Device Tree Bindings + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + +maintainers: + - Jianlong Huang + +properties: + compatible: + enum: + - starfive,jh7110-sys-pinctrl + - starfive,jh7110-aon-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: control + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + description: The GPIO parent interrupt. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + ngpios: + enum: + - 64 + - 4 + +required: + - compatible + - reg + - reg-names + - clocks + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-[0-9]+$': + type: object + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, system signal configuration, pin groups for + vin/vout module, pin voltage, mux functions for output, mux functions + for output enable, mux functions for input. + + properties: + starfive,pins: + description: | + The list of pin identifiers that properties in the node apply to. + This should be set using the PAD_GPIOX macros. + This has to be specified. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + + starfive,pinmux: + description: | + The list of GPIOs and their mux functions that properties in the + node apply to. This should be set using the PAD_GPIOX_FUNC_SEL + macro with its value. + This is optional for some pins. + The value of PAD_GPIOX_FUNC_SEL macro can selects: + 0: GPIOX mux function 0, + 1: GPIOX mux function 1, + 2: GPIOX mux function 2. + + starfive,pin-ioconfig: + description: | + This is used to configure the core settings of system signals. + The combination of GPIO_IE or GPIO_DS or GPIO_PU or GPIO_PD or + GPIO_SLEW or GPIO_SMT or GPIO_POS. + $ref: /schemas/types.yaml#/definitions/uint32 + + starfive,padmux: + description: | + The padmux is for vin/vout module to select pin groups. + 0: vout will be set at pins from PAD_GPIO7 to PAD_GPIO34, + when PAD_GPIOX_FUNC_SEL is set as 1. + vin will be set at pins from PAD_GPIO6 to PAD_GPIO20. + when PAD_GPIOX_FUNC_SEL is set as 2. + 1: vout will be set at pins from PAD_GPIO36 to PAD_GPIO63, + when PAD_GPIOX_FUNC_SEL is set as 1. + vin will be set at pins from PAD_GPIO21 to PAD_GPIO35. + when PAD_GPIOX_FUNC_SEL is set as 2. + 2: vin will be set at pins from PAD_GPIO36 to PAD_GPIO50, + when PAD_GPIOX_FUNC_SEL is set as 2 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + starfive,pin-syscon: + description: | + This is used to set pin voltage, + 0: 3.3V, 1: 2.5V, 2: 1.8V. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + starfive,pin-gpio-dout: + description: | + This is used to set their mux functions for output. + This should be set using the GPO_XXX macro, + such as GPO_LOW, GPO_UART0_SOUT. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 107 + + starfive,pin-gpio-doen: + description: | + This is used to set their mux functions for output enable. + This should be set using the OEN_XXX macro, + such as OEN_LOW, OEN_I2C0_IC_CLK_OE. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 49 + + starfive,pin-gpio-din: + description: | + This is used to set their mux functions for input. + This should be set using the GPI_XXX macro, + such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 90 + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + #include + #include + + gpio: gpio@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + reg-names = "control"; + clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>; + resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>; + interrupts = <86>; + interrupt-controller; + #gpio-cells = <2>; + ngpios = <64>; + status = "okay"; + + uart0_pins: uart0-pins { + uart0-pins-tx { + starfive,pins = ; + starfive,pin-ioconfig = ; + starfive,pin-gpio-dout = ; + starfive,pin-gpio-doen = ; + }; + + uart0-pins-rx { + starfive,pins = ; + starfive,pinmux = ; + starfive,pin-ioconfig = ; + starfive,pin-gpio-doen = ; + starfive,pin-gpio-din = ; + }; + }; + }; + + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + +... From patchwork Fri Sep 30 07:49:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 611164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFA13C4332F for ; Fri, 30 Sep 2022 07:51:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbiI3Hvf (ORCPT ); Fri, 30 Sep 2022 03:51:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230163AbiI3Hvd (ORCPT ); Fri, 30 Sep 2022 03:51:33 -0400 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.155.67.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DA7473905; Fri, 30 Sep 2022 00:51:30 -0700 (PDT) X-QQ-mid: bizesmtp64t1664524157twghgn92 Received: from ubuntu.localdomain ( [113.72.146.201]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 30 Sep 2022 15:49:16 +0800 (CST) X-QQ-SSF: 01000000000000305000000A0000000 X-QQ-FEAT: dcYQFNbI8vF/ZXIzspBCLiWGx6eyLdAUf1gWuSEO7ysHQNV/9IjEcIeS4KKRd lalkonPRD5gcTNlomR0FEimLp1F5v54Rm9TkjWBvaoSp4js0LWldVMrqJ8MhzIEa2tjtFvK lkEyTSxqBfba3wV+R7/YvA5x5cMT88S2uN+dkxv6uEXaBQAVho45gGuJD7RDhvecbZ/MUNX EWlDKtuGQnf42hyGCknR76rPCmAAujz2471cw/aUMY219VF/+C4VaUZj/g7Rx0F4Gc8x4wf YPChfwizTe2nZTHGFhQ+kERGNj2g5a9mcG+iYaiYfX7NaqmxMcR9Dblex/TcPYKcFSSsDNr UPqZcQ+PoOjwVh28PdBjDP7wGNbT7AUbonMZczOifE73S5YkaEpg2YeHXXWWN5I3JZHgTIO MtM+S/rQ0s4= X-QQ-GoodBg: 0 From: Hal Feng To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , Hal Feng , linux-kernel@vger.kernel.org Subject: [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree Date: Fri, 30 Sep 2022 15:49:14 +0800 Message-Id: <20220930074914.6757-1-hal.feng@linux.starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:linux.starfivetech.com:qybglogicsvr:qybglogicsvr2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Emil Renner Berthing Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd. Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Hal Feng --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++ 1 file changed, 449 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi new file mode 100644 index 000000000000..46f418d4198a --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing + */ + +/dts-v1/; +#include +#include +#include + +/ { + compatible = "starfive,jh7110"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <16384>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imac"; + tlb-split; + status = "disabled"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu1: cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu2: cpu@2 { + compatible = "sifive,u74-mc", "riscv"; + reg = <2>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu3: cpu@3 { + compatible = "sifive,u74-mc", "riscv"; + reg = <3>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu4: cpu@4 { + compatible = "sifive,u74-mc", "riscv"; + reg = <4>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; + }; + + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + clk_rtc: clk_rtc { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + gmac0_rmii_refin: gmac0_rmii_refin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + gmac0_rgmii_rxin: gmac0_rgmii_rxin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + gmac1_rmii_refin: gmac1_rmii_refin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + gmac1_rgmii_rxin: gmac1_rgmii_rxin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + i2stx_bclk_ext: i2stx_bclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + i2stx_lrck_ext: i2stx_lrck_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <192000>; + }; + + i2srx_bclk_ext: i2srx_bclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + i2srx_lrck_ext: i2srx_lrck_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <192000>; + }; + + tdm_ext: tdm_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <49152000>; + }; + + mclk_ext: mclk_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <49152000>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh7110-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + plic: plic@c000000 { + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <136>; + }; + + ccache: cache-controller@2010000 { + compatible = "starfive,jh7110-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x4000>; + interrupts = <1>, <3>, <4>, <2>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + }; + + syscrg: syscrg@13020000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x13020000 0x0 0x10000>; + + syscrg_clk: clock-controller@13020000 { + compatible = "starfive,jh7110-clkgen-sys"; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext"; + #clock-cells = <1>; + }; + + syscrg_rst: reset-controller@13020000 { + compatible = "starfive,jh7110-reset"; + #reset-cells = <1>; + starfive,assert-offset = <0x2F8>; + starfive,status-offset= <0x308>; + starfive,nr-resets = ; + }; + }; + + aoncrg: aoncrg@17000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x17000000 0x0 0x10000>; + + aoncrg_clk: clock-controller@17000000 { + compatible = "starfive,jh7110-clkgen-aon"; + clocks = <&osc>, <&clk_rtc>, + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, + <&syscrg_clk JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg_clk JH7110_SYSCLK_APB_BUS_FUNC>; + clock-names = "osc", "clk_rtc", + "gmac0_rmii_refin", "gmac0_rgmii_rxin", + "stg_axiahb", "apb_bus_func"; + #clock-cells = <1>; + }; + + aoncrg_rst: reset-controller@17000000 { + compatible = "starfive,jh7110-reset"; + #reset-cells = <1>; + starfive,assert-offset = <0x38>; + starfive,status-offset= <0x3C>; + starfive,nr-resets = ; + }; + }; + + gpio: gpio@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + reg-names = "control"; + clocks = <&syscrg_clk JH7110_SYSCLK_IOMUX>; + resets = <&syscrg_rst JH7110_SYSRST_IOMUX>; + interrupts = <86>; + interrupt-controller; + #gpio-cells = <2>; + ngpios = <64>; + }; + + gpioa: gpio@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x0 0x17020000 0x0 0x10000>; + reg-names = "control"; + resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>; + interrupts = <85>; + interrupt-controller; + #gpio-cells = <2>; + ngpios = <4>; + }; + + uart0: serial@10000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10000000 0x0 0x10000>; + clocks = <&syscrg_clk JH7110_SYSCLK_UART0_CORE>, + <&syscrg_clk JH7110_SYSCLK_UART0_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg_rst JH7110_SYSRST_UART0_APB>, + <&syscrg_rst JH7110_SYSRST_UART0_CORE>; + interrupts = <32>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@10010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10010000 0x0 0x10000>; + clocks = <&syscrg_clk JH7110_SYSCLK_UART1_CORE>, + <&syscrg_clk JH7110_SYSCLK_UART1_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg_rst JH7110_SYSRST_UART1_APB>, + <&syscrg_rst JH7110_SYSRST_UART1_CORE>; + interrupts = <33>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@10020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&syscrg_clk JH7110_SYSCLK_UART2_CORE>, + <&syscrg_clk JH7110_SYSCLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg_rst JH7110_SYSRST_UART2_APB>, + <&syscrg_rst JH7110_SYSRST_UART2_CORE>; + interrupts = <34>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; + clocks = <&syscrg_clk JH7110_SYSCLK_UART3_CORE>, + <&syscrg_clk JH7110_SYSCLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg_rst JH7110_SYSRST_UART3_APB>, + <&syscrg_rst JH7110_SYSRST_UART3_CORE>; + interrupts = <45>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@12010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12010000 0x0 0x10000>; + clocks = <&syscrg_clk JH7110_SYSCLK_UART4_CORE>, + <&syscrg_clk JH7110_SYSCLK_UART4_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg_rst JH7110_SYSRST_UART4_APB>, + <&syscrg_rst JH7110_SYSRST_UART4_CORE>; + interrupts = <46>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@12020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12020000 0x0 0x10000>; + clocks = <&syscrg_clk JH7110_SYSCLK_UART5_CORE>, + <&syscrg_clk JH7110_SYSCLK_UART5_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg_rst JH7110_SYSRST_UART5_APB>, + <&syscrg_rst JH7110_SYSRST_UART5_CORE>; + interrupts = <47>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; +}; From patchwork Fri Sep 30 09:06:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 611157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8ADBC4332F for ; Fri, 30 Sep 2022 09:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230382AbiI3JJM (ORCPT ); Fri, 30 Sep 2022 05:09:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229566AbiI3JJL (ORCPT ); Fri, 30 Sep 2022 05:09:11 -0400 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.154.221.58]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAB9D2ED4A; Fri, 30 Sep 2022 02:09:08 -0700 (PDT) X-QQ-mid: bizesmtp78t1664528816tuqcmaei Received: from ubuntu.localdomain ( [113.72.146.201]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 30 Sep 2022 17:06:54 +0800 (CST) X-QQ-SSF: 01000000000000305000000A0000000 X-QQ-FEAT: dcYQFNbI8vHgGBegdo4q9m3MYLIYCHcw61t0e3fQ/Hq7EkLkmrCEJbkHKfFlG J4zmi7grr3n/OnwCkitlLiu4qcHnTOsYdPqejqBFnT0LtYo71L1edvOVk8EqtBU/4NITA1v PtvMIi33G6+geE5Dd7Xac7PKFO83VGfrb9v3HUE71s36L+Ak4KHisHaZkXU39WXe8TV7AUX q+V7+WA4YGqKpmQTORK9G3XgM1C5YwLvoydQ6vz8XQ8mL/G9PJW987+tEw4XK5Hu7XQzgcN KjPitbWT1T8TMnUvEQDlipeEru32FxvLp89vTIwWeP2uI+17rxGu3MROCL82u0OFZBPCrY+ J8aBzuhMWa2Us40P8GNsprTnvf4zhQfu4pLTNgpXugz2pvHj18+EXRpgSYrCSlqRLsMhXA8 O7fk+0n7ykI= X-QQ-GoodBg: 0 From: Hal Feng To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , Hal Feng , linux-kernel@vger.kernel.org Subject: [PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW Date: Fri, 30 Sep 2022 17:06:53 +0800 Message-Id: <20220930090653.7449-1-hal.feng@linux.starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:linux.starfivetech.com:qybglogicsvr:qybglogicsvr2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add CONFIG_SERIAL_8250_DW=y, which is a necessary option for StarFive JH7110 and JH7100 SoCs to boot with serial ports. Signed-off-by: Hal Feng Reviewed-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index aed332a9d4ea..0c44484cd3a4 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -122,6 +122,7 @@ CONFIG_MICROSEMI_PHY=y CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y From patchwork Fri Sep 30 12:23:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 611149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A130C433F5 for ; Fri, 30 Sep 2022 12:25:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231449AbiI3MZz (ORCPT ); Fri, 30 Sep 2022 08:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231680AbiI3MZn (ORCPT ); Fri, 30 Sep 2022 08:25:43 -0400 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.155.67.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD36773317; Fri, 30 Sep 2022 05:25:34 -0700 (PDT) X-QQ-mid: bizesmtp71t1664540601timrcnbn Received: from ubuntu.localdomain ( [113.72.146.201]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 30 Sep 2022 20:23:20 +0800 (CST) X-QQ-SSF: 01000000000000305000000A0000000 X-QQ-FEAT: dS+JUNSIibdYmLj5t1I9ugN+S0ksnIEycmIIAPYyEFfZJVg9V/kdWfTdMQPEk fjiuX7Oae/U06nm1p3ELka+dZsKdTvpPxceFNxZs2W5d9q7tN+Mlh/tTsnCLp+g6MD8EPCS /Omd+8wurSlmyVZfI2W/RsS4n2SttiwKTr4ZAKOIT9PVufqV9TzIFqghUyiauNZC9Ivg2gS eYUqfNTfp36XhmArpqvagc+H+BPz+pO2/qJ/vSyY+mlbNx2FTcSMVqpeA7+yi8QJ5ISZxqT wVnKrNoH4hnS19Rz8hErC91RmQbG1g+8wjDRa2yNP2JEJ6cXnZdrQjOle67cSq7QT7C55Mw 60KgXmT3qTPNobR9taWYEIhn5WBP7AMaxciOBVayF+QGM0k/4WYweBP1+XhVPm20wpK3aHZ eXD32uXPZCs= X-QQ-GoodBg: 0 From: Hal Feng To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , Hal Feng , linux-kernel@vger.kernel.org Subject: [PATCH v1 30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options Date: Fri, 30 Sep 2022 20:23:18 +0800 Message-Id: <20220930122318.9244-1-hal.feng@linux.starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:linux.starfivetech.com:qybglogicsvr:qybglogicsvr2 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Kconfig options to select the specified StarFive SoC. Select necessary Kconfig options required by the specified SoC for booting. Signed-off-by: Hal Feng --- arch/riscv/Kconfig.socs | 27 ++++++++++++++++++++++++++- arch/riscv/boot/dts/starfive/Makefile | 4 ++-- drivers/clk/starfive/Kconfig | 14 ++++++-------- drivers/pinctrl/starfive/Kconfig | 6 ++---- drivers/reset/Kconfig | 1 - 5 files changed, 36 insertions(+), 16 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 10f68a4359f9..321c448e7b6f 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,10 +22,35 @@ config SOC_STARFIVE bool "StarFive SoCs" select PINCTRL select RESET_CONTROLLER + select RESET_STARFIVE + help + This enables support for StarFive SoC platform hardware. + +if SOC_STARFIVE + +config SOC_JH7100 + bool "StarFive JH7100 SoC support" + depends on SOC_STARFIVE select SIFIVE_L2 select SIFIVE_PLIC + select CLK_STARFIVE_JH7100 + select PINCTRL_STARFIVE_JH7100 + default SOC_STARFIVE help - This enables support for StarFive SoC platform hardware. + This enables support for StarFive JH7100 SoC. + +config SOC_JH7110 + bool "StarFive JH7110 SoC support" + depends on SOC_STARFIVE + select SIFIVE_L2 + select SIFIVE_PLIC + select CLK_STARFIVE_JH7110_SYS + select PINCTRL_STARFIVE_JH7110 + default SOC_STARFIVE + help + This enables support for StarFive JH7110 SoC. + +endif config SOC_VIRT bool "QEMU Virt Machine" diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index e1237dbc6aac..a6ecd3c2ec7d 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb -dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-v2.dtb +dtb-$(CONFIG_SOC_JH7100) += jh7100-beaglev-starlight.dtb +dtb-$(CONFIG_SOC_JH7110) += jh7110-starfive-visionfive-v2.dtb diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 42aad3b553cb..d0490e9f42db 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -5,36 +5,34 @@ config CLK_STARFIVE config CLK_STARFIVE_JH7100 bool "StarFive JH7100 clock support" - depends on SOC_STARFIVE || COMPILE_TEST + depends on SOC_JH7100 || COMPILE_TEST select CLK_STARFIVE - default SOC_STARFIVE help Say yes here to support the clock controller on the StarFive JH7100 SoC. config CLK_STARFIVE_JH7100_AUDIO tristate "StarFive JH7100 audio clock support" - depends on SOC_STARFIVE || COMPILE_TEST + depends on SOC_JH7100 || COMPILE_TEST select CLK_STARFIVE - default m if SOC_STARFIVE + default m if SOC_JH7100 help Say Y or M here to support the audio clocks on the StarFive JH7100 SoC. config CLK_STARFIVE_JH7110_SYS bool "StarFive JH7110 system clock support" - depends on SOC_STARFIVE || COMPILE_TEST + depends on SOC_JH7110 || COMPILE_TEST select CLK_STARFIVE - default SOC_STARFIVE help Say yes here to support the system clock controller on the StarFive JH7110 SoC. config CLK_STARFIVE_JH7110_AON tristate "StarFive JH7110 always-on clock support" - depends on SOC_STARFIVE || COMPILE_TEST + depends on SOC_JH7110 || COMPILE_TEST select CLK_STARFIVE - default m if SOC_STARFIVE + default m if SOC_JH7110 help Say yes here to support the always-on clock controller on the StarFive JH7110 SoC. diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index fde39f4a7922..d09bdf6d3029 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -2,7 +2,7 @@ config PINCTRL_STARFIVE_JH7100 tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC" - depends on SOC_STARFIVE || COMPILE_TEST + depends on SOC_JH7100 || COMPILE_TEST depends on OF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS @@ -10,7 +10,6 @@ config PINCTRL_STARFIVE_JH7100 select GPIOLIB select GPIOLIB_IRQCHIP select OF_GPIO - default SOC_STARFIVE help Say yes here to support pin control on the StarFive JH7100 SoC. This also provides an interface to the GPIO pins not used by other @@ -28,10 +27,9 @@ config PINCTRL_STARFIVE config PINCTRL_STARFIVE_JH7110 bool "Pinctrl and GPIO driver for the StarFive JH7110 SoC" - depends on SOC_STARFIVE || COMPILE_TEST + depends on SOC_JH7110 || COMPILE_TEST depends on OF select PINCTRL_STARFIVE - default SOC_STARFIVE help Say yes here to support pin control on the StarFive JH7110 SoC. This also provides an interface to the GPIO pins not used by other diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 8121de5ecc3c..c001879bd890 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -228,7 +228,6 @@ config RESET_SOCFPGA config RESET_STARFIVE bool "StarFive SoC Reset Driver" depends on SOC_STARFIVE || COMPILE_TEST - default SOC_STARFIVE help This enables the reset controller driver for the StarFive SoCs.