From patchwork Wed Oct 5 22:12:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 612612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F5A4C43217 for ; Wed, 5 Oct 2022 22:12:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229623AbiJEWMy (ORCPT ); Wed, 5 Oct 2022 18:12:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229574AbiJEWMt (ORCPT ); Wed, 5 Oct 2022 18:12:49 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C80383076 for ; Wed, 5 Oct 2022 15:12:48 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id bq9so27827396wrb.4 for ; Wed, 05 Oct 2022 15:12:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=sQtmC5CT1BYx1wr4cDsdhyqbJnf1PNOi9nZ8obHDjYY=; b=i9T+BWoyfOh4YwlSNxED/MNU5eEtRg/wQxRHg6AMMJnEhJpCZJxJIsMHYeysa/gZt0 zd5i4SC9fwfWTZPwWF7UtL1y0Ou8XdBQ5fZ4CPn4naErwOryPTtgjDSdzepvRfDRnB5l fB+28iqqQbaJEwSY/16k32aztbDoiP7W9FZ9m521A98TXEylSZxaJrOC1NLyamxRRVo6 yJCVeDEn8Wi/jpBcKDcFDFsuBWGhTF95c5xvfDpc7biLpfGHGqVI0vzjjDa7f7yt1z6Y vnjOUQi6LU5ejqMHeabB9wGgjjJuQjNCT/i7HdUOkDC09zmw0rYsdytRzgiKbZWNKABJ IEkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=sQtmC5CT1BYx1wr4cDsdhyqbJnf1PNOi9nZ8obHDjYY=; b=A9aKxI8QOcGiz/7yMdWjktIk1ZXT8wI3jY3puiFDn488hJWgiCBUYvPDmIy4Mgep/8 foyP87vtqfaPvELZwtA7uK40sEGfqEqDwpry1gTXr7J6PC+17HHb+4aYnyHqIo92mUg8 tV2gQYd8yMnlvcK7aUnhIazPxwCqc3EJAXSyIIQxSXaJv9YW13bNxuCyQanNDz9BOfVI C3Y2A1aJp3XKrvE4wJ11Xvwe7QHYDr3QFGPaIn9HWqpqmgdkIFWsfPK0FdM05tRZGgZv QGs1Uqpl22JfWqc8IBk6QVI5xtjheak/4MW2CO4K2NqXDbLpA0/UkMr9eZcUXMu+kLGw vxVw== X-Gm-Message-State: ACrzQf3/zdUyeIPRBsTWvsSmV8xUjfGklaW1+qKv9UjDHRPh6iu4n/+w CDvu8EbxrtoW0oXtHRfnjzF4qA== X-Google-Smtp-Source: AMsMyM7l8QwhdPPGYpixZnOKyo8MYpftQTDDNl1qzPKEnGbteRMvBT2RuKcjazpjxYJ2mUmgntHJ7Q== X-Received: by 2002:a5d:5983:0:b0:22c:b9a0:e874 with SMTP id n3-20020a5d5983000000b0022cb9a0e874mr1075363wri.306.1665007966655; Wed, 05 Oct 2022 15:12:46 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:46 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 01/10] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm-dw-apb-timers-pwm2 Date: Wed, 5 Oct 2022 23:12:33 +0100 Message-Id: <20221005221242.470734-2-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the bindings for Synopsys' DesignWare PWM block as we will be adding DT/platform support to the Linux driver soon. Signed-off-by: Ben Dooks Reviewed-by: Krzysztof Kozlowski --- v5: - fixed order of properties - corrected clock to two items v4: - fixed typos, added reg v3: - add description and example - merge the snps,pwm-number into this patch - rename snps,pwm to snps,dw-apb-timers-pwm2 v2: - fix #pwm-cells to be 3 - fix indentation and ordering issues --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..9aabdb373afa --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + pwm: pwm@180000 { + compatible = "snps,dw-apb-timers-pwm2"; + reg = <0x180000 0x200>; + #pwm-cells = <3>; + clocks = <&bus>, <&timer>; + clock-names = "bus", "timer"; + }; From patchwork Wed Oct 5 22:12:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 612611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BE8EC4321E for ; Wed, 5 Oct 2022 22:12:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229544AbiJEWMz (ORCPT ); Wed, 5 Oct 2022 18:12:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229519AbiJEWMv (ORCPT ); Wed, 5 Oct 2022 18:12:51 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B8CD83069 for ; Wed, 5 Oct 2022 15:12:50 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id b7so20217576wrq.9 for ; Wed, 05 Oct 2022 15:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=VSxSa3rea769WcJeCZBGNkJoHT2kIKG/V+nPY89aK3CfQRIT8MMN9BaN/doC1InOFa 6fqL0v1UA5Z1Acp4mdOx9NboMCQHfhaEm34AyEe7VMrz+jMoHYo/gRv0hV6d/1NP/Lfa 7TZ873O/ppGZlkmfFJ0Rz37fORUXoonDeMwOPTsFEfpdmTkrm6g4UtvpVta6Kwywqaj9 XLTZtQf04xQgzJUAyvsCDSmHWXM5oM+kKGR9CAomBI3BRyFYdmROqMgSX3DbMRDKkNQ6 FEUEUTBE+Y+0fAeFqozz5OKBhftilOsww2VBKbiW1cpz5IQXNu3SyNqHz1qIKzZGKRuH wDng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=b9gYSP4FTk3Kmaqd1SSmqx0wyq1cCqLcdahKGkLylto+ZFlWlk04vA6RdhPmN7UVBR 5lv6TnqbWyBUQQXxKB0Frxa1fp+PX465stoPub7w4bzFH0NrOm8tH2DRKSTD/cDGdnne WlAydetaNpbDNEHzSIUZ9Y2ZNq/3qw8o1WaI1YUxEgA5R2E1J3q2fjLswPdN4Ux5in96 YRAFHXaLt/7CZWMRv5vCdT928cm2J8MWVDFD53yOKqfazuEwqVlpT7zaft/f+WFTKb7S Zjq6aPvjM2H2LeJEJxv3Lw1ix1TwKWEhgE1KbI+RJLwARn/zCRiwMBVESJqMOOL3/bI1 bSBg== X-Gm-Message-State: ACrzQf2ZlPgwPc4D0+u8b/M8ZqTfhTCVjI5yvtaLVE3BfUTm/wGUXt08 knUYsVfaDzvGp3X9v5giH4+fjQ== X-Google-Smtp-Source: AMsMyM482vi2maJSOPEx3SNNXxYZFc6clxuujhf+yB8wdjpjq6Wh4uT014rkevtaTy87y9llX+CB5A== X-Received: by 2002:a5d:428c:0:b0:22e:5d4e:c71e with SMTP id k12-20020a5d428c000000b0022e5d4ec71emr1016893wrq.19.1665007969099; Wed, 05 Oct 2022 15:12:49 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:48 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 03/10] pwm: dwc: change &pci->dev to dev in probe Date: Wed, 5 Oct 2022 23:12:35 +0100 Message-Id: <20221005221242.470734-4-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dwc_pwm_probe() assignes dev to be &pci->dev but then uses &pci->dev throughout the function. Change these all to the be 'dev' variable to make lines shorter. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 7568300bb11e..c706ef9a7ba1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -202,14 +202,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL); + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; ret = pcim_enable_device(pci); if (ret) { - dev_err(&pci->dev, - "Failed to enable device (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); return ret; } @@ -217,14 +216,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); if (ret) { - dev_err(&pci->dev, - "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); return ret; } dwc->base = pcim_iomap_table(pci)[0]; if (!dwc->base) { - dev_err(&pci->dev, "Base address missing\n"); + dev_err(dev, "Base address missing\n"); return -ENOMEM; } From patchwork Wed Oct 5 22:12:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 612610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FB53C43217 for ; Wed, 5 Oct 2022 22:13:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229673AbiJEWM5 (ORCPT ); Wed, 5 Oct 2022 18:12:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229624AbiJEWMy (ORCPT ); Wed, 5 Oct 2022 18:12:54 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E7898320A for ; Wed, 5 Oct 2022 15:12:53 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id j7so22473768wrr.3 for ; Wed, 05 Oct 2022 15:12:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=JVsjMt/QqWDQIkbN9ThQA44X6Q8M6+q3vjfLdgd5aDk=; b=lns6fCmSp1PmCoJBnYkhAb1nQxyf69647ZdqX1ZEZsl0yxpJhWobRqY0R/rhtzgEZj KVIoTT60Tv0pIZmmnD9m1I195DBzHzTEMOxrAoWfI5nItLrKzGvaTTVo4TuGA8A/bwgI FvgrWLjPE6WSNO7zMIcJD1Dbk2dH4yKS87CRB2Q6aHz4NUP1/OaW4s0QkcFpco4tZKUn 3GDVX64VGS8OPsMDf9BW8bF+ncgYPOJeZIQvAnnJffEuG8OHg/E+24nQs13P9sDbbPSC 41g6QzIOh713i2HKRk1UEbxwKUrzreIA0Jfr0gtOGlvY1S1Niqt7u2/jWKOn3DhpeI53 cZSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=JVsjMt/QqWDQIkbN9ThQA44X6Q8M6+q3vjfLdgd5aDk=; b=ajFlda8cwclYvr9pbSXXLfy3IkgvhUlFn+nt5ynnk6zFg+HaCZZyhC8knZe5O/EsOr 7jFTkn1HajVroEJ7dyYq2cusj6TxX83esUBMvOEmRb7AVTr1R8HM98IzLZEE9N6Np0lh HTRCCbNXPrJYSZG8FK/9/nJ9deK89earVb+SkXcxbQf7oZlx1RGsSdLB4x4hfwTEDNC9 h7zEep0LjD6jo6xPsx24zszkxqd4Gtf8ipX7g6PCDu1BiW/zEtE8wQLqeTYjQfy1GwM2 zPU47fx7xnSR3cUjUfbh4umrOzTa9yOZ/x5lIe8oR7vsKSPhakd1Bxi5mD3ziuYY4SDz 11DQ== X-Gm-Message-State: ACrzQf0cmThZO3vGeBBM5gKZqFUh6/pDYKIG+q0AsIVzzHwDBP4wMiDY l067RKZ2gbeVL9b8FdPigmAU+Q== X-Google-Smtp-Source: AMsMyM64144/H+SMQ4cld0JX811x0IsidPU2IR5ZlGuFZbVWusIQE0gBZpA9vl7SFsyXTQungnHxew== X-Received: by 2002:adf:eacf:0:b0:22e:369:2081 with SMTP id o15-20020adfeacf000000b0022e03692081mr1071029wrn.339.1665007971560; Wed, 05 Oct 2022 15:12:51 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:50 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 05/10] pwm: dwc: use devm_pwmchip_add Date: Wed, 5 Oct 2022 23:12:37 +0100 Message-Id: <20221005221242.470734-6-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use devm_pwmchip_add() to add the pwm chip to avoid having to manually remove it (useful for the next patch which adds the platform-device support). Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 61f11e0a9319..56cde9da2c0e 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -242,7 +242,7 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - ret = pwmchip_add(&dwc->chip); + ret = devm_pwmchip_add(dev, &dwc->chip); if (ret) return ret; @@ -254,12 +254,8 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) static void dwc_pwm_remove(struct pci_dev *pci) { - struct dwc_pwm *dwc = pci_get_drvdata(pci); - pm_runtime_forbid(&pci->dev); pm_runtime_get_noresume(&pci->dev); - - pwmchip_remove(&dwc->chip); } #ifdef CONFIG_PM_SLEEP From patchwork Wed Oct 5 22:12:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 612609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D50CC4167B for ; Wed, 5 Oct 2022 22:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229578AbiJEWNA (ORCPT ); Wed, 5 Oct 2022 18:13:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229591AbiJEWM4 (ORCPT ); Wed, 5 Oct 2022 18:12:56 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C8618306B for ; Wed, 5 Oct 2022 15:12:54 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id f11so25187340wrm.6 for ; Wed, 05 Oct 2022 15:12:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=sf7gmbsgKDhqFstk8g51OmZhGoNVa8xIzDvITlkpkK0=; b=WMV2J3/IFDWrBmhUz7DjYlXvyBwYCsWL8B1uZzM1kac+0ped3GCPIQ22sUsasTb2/j 3cK8HCab8PpQqNlpw/oksHeRDolKTvMllTUR3NZVTJn92FLe8c7p0I9qAqJ+2zo4Dgvp 3i+bWmVCSnKaZR5LnNHUKHKl1SdQVWSvImewl6CSePIksbS40J8hv/3JHx2VW2vBcx5D 65fK7x9C7ei26oH6HHRfsVNKhJ/7iQA1VxAJrCpx0qUHjxlATMI+i3lh7qYWyEF3ADFF ea+0LsPUxpzC2+JmkJUbxD3rPHKAiaMa0hi9t5uOOX/wAhOAbRZ8s8d5kUJA554tMljR JcRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=sf7gmbsgKDhqFstk8g51OmZhGoNVa8xIzDvITlkpkK0=; b=b9VetZWVgc0LFOnMWkC8gOXVuf+zBbql+fgG0OZ0c29BMzIY0OisYaK/w4KJsjjahe Q7kv2ahG8MkO2ML4fuHzxBLzBq9Mt5u5UvF6k0qw+vgYm/1GVMW9ueSrsBPiIcY3mJQ9 5oD77RNgUcsZYHWgqQMZQ70pjFlEEJy6whSrtDtrMI+5wpB300TtoBmKp5KJgoaAl0mt tg1Wlmsv8e4RD5PyKmG+r6F31GcL+HwYj3SXqE/mDlETER1yKhjlDuDNXatDfp2JF05j knUTzpTuGenRKcNjkXAUMSuVghSh3gnDMejm0kRLMW4+IvFmqeeQEBoHdGFgOHl28URR B7BQ== X-Gm-Message-State: ACrzQf3nd32IQozGe3SZQLjDnv2itJtOozjQDL1iR7JNqzfTITh9dA5x /JA67x2hwcva1r8dCzisggd/0g== X-Google-Smtp-Source: AMsMyM4mYKdGYq7ZXAXLcrVvSb15fttWtQdS3kRb10WzSVAdrzKMr1NtK5TXM+1ncZUWg8EICO7bag== X-Received: by 2002:adf:ec01:0:b0:22e:35ce:7a65 with SMTP id x1-20020adfec01000000b0022e35ce7a65mr1070880wrn.498.1665007973676; Wed, 05 Oct 2022 15:12:53 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:53 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 07/10] pwm: dwc: make timer clock configurable Date: Wed, 5 Oct 2022 23:12:39 +0100 Message-Id: <20221005221242.470734-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks --- v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc-pci.c | 1 + drivers/pwm/pwm-dwc.c | 10 ++++++---- drivers/pwm/pwm-dwc.h | 2 ++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c index 2213d0e7f3c8..949423e368f9 100644 --- a/drivers/pwm/pwm-dwc-pci.c +++ b/drivers/pwm/pwm-dwc-pci.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "pwm-dwc.h" diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 90a8ae1252a1..1251620ab771 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -47,13 +48,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -128,12 +129,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty += 1; - duty *= DWC_CLK_PERIOD_NS; + duty *= dwc->clk_ns; state->duty_cycle = duty; period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period += 1; - period *= DWC_CLK_PERIOD_NS; + period *= dwc->clk_ns; period += duty; state->period = period; @@ -156,6 +157,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; + dwc->clk_ns = 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index c8dd690eefb3..dc451cb2eff5 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -40,6 +40,8 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:55 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 09/10] pwm: dwc: add PWM bit unset in get_state call Date: Wed, 5 Oct 2022 23:12:41 +0100 Message-Id: <20221005221242.470734-10-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 1251620ab771..5ef0fe7ea3e9 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -121,23 +121,30 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, { struct dwc_pwm *dwc = to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; pm_runtime_get_sync(chip->dev); - state->enabled = !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty += 1; - duty *= dwc->clk_ns; - state->duty_cycle = duty; + state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); - period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period += 1; - period *= dwc->clk_ns; - period += duty; - state->period = period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty = (ld + 1) * dwc->clk_ns; + period = (ld2 + 1) * dwc->clk_ns; + period += duty; + } else { + duty = (ld + 1) * dwc->clk_ns; + period = duty * 2; + } + state->period = period; + state->duty_cycle = duty; state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev);