From patchwork Wed Oct 5 17:43:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 612618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4186C43219 for ; Wed, 5 Oct 2022 17:44:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230388AbiJERoT (ORCPT ); Wed, 5 Oct 2022 13:44:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230209AbiJERoS (ORCPT ); Wed, 5 Oct 2022 13:44:18 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE8783A483; Wed, 5 Oct 2022 10:44:17 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id j16so15065469wrh.5; Wed, 05 Oct 2022 10:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=J6AdrG61fFuk3qFrjsmnmW/v2lHEYSKDOmlc3Uttj2I=; b=jiMuHvxyLhrd3kGwgfpUsnOt7hf+tBiYex6HV/Mo3+9CfzkqQDf6kj0FOvI6w7IOgx 8rOazqdOFH/IK4kOu/nGAE0Gwd6tz9zqFRiK5SfaUIJXNPBb+cLIiRxK/dzP8zBDbTh0 bmJ+RXjS9uoWTvXUf6lO8s7sgUeuSv5Q/CzCWgz4PuqV+33o4K14FqNUgpr5tuaGFjwD 9rRwMirpE+krkiGstEYsvIXsCx1PSUOdPjdDtnA1aNLOvgETT45mqxJRkjIucnOTEr7r HS1oYEmDw5gNgzR4CYmaL+LIiOyijjWsOWxkmgiROpWTPe/B7erVlKS7bcDDlOvOR1Yh +pww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=J6AdrG61fFuk3qFrjsmnmW/v2lHEYSKDOmlc3Uttj2I=; b=SdGY6ItuTb3cbmrXmLER4fxNqFXjSyexZzTC7ISTP0htYFRrCQZdx5YRMh81oNJE9t Pk2o4kCBVdKZFcH5NkjoW+DdtgiBJF4zAyZrAKlZshLf6b8SYJ9C6JJm6fXFbeLBTfMZ C+y+x/GsrYLuu6G3oHEV2EQTq3bVUiXWoSZ5ius8NKSCca/8Sx9arOOze9t1JKIQ5OF4 3h2i0sYWOOqSCz3W5K9ZcleqhmjHIyQeW9qJG7m0TRziRDSRjHY/Kry6S4bklzSKUa3q j1ipanYpncy9+uA9qsjGPs74bKCnNCq/UBOelVWOjC7XZvoASwaBlaLGC8/HV+6cPl+/ Yj+A== X-Gm-Message-State: ACrzQf19mWLi97x56udYj+7wctpu0hJnE3jqVVzlL98MSmh3u+DoY4Kk dAU4TQ5OgCjcIO7NGK5+N/A= X-Google-Smtp-Source: AMsMyM7LORL+FOnuDtH5sB3TJMSNlDx7UAQ83NOa0L/mNBleJUp+Cs/QLwJCYNTum2QiG1rzKE0y+A== X-Received: by 2002:a5d:474b:0:b0:22e:3180:f748 with SMTP id o11-20020a5d474b000000b0022e3180f748mr520389wrs.504.1664991856242; Wed, 05 Oct 2022 10:44:16 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.98]) by smtp.gmail.com with ESMTPSA id c6-20020a5d4146000000b0022a403954c3sm16075491wrq.42.2022.10.05.10.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 10:44:15 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Andy Teng , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/10] arm64: dts: mediatek: mt6779: Remove syscon compatible from pin controller Date: Wed, 5 Oct 2022 20:43:34 +0300 Message-Id: <20221005174343.24240-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221005174343.24240-1-y.oudjana@protonmail.com> References: <20221005174343.24240-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yassine Oudjana Remove syscon compatible string from pin controller to follow DT bindings and pass checks. Adding the syscon compatible to the DT bindings documentation instead causes a different check error due to the syscon document specifying a maximum of 1 item in the reg property, while this has 9. Nothing is using the pin controller as a syscon at the moment so it should be a safe thing to do. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- arch/arm64/boot/dts/mediatek/mt6779.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 9bdf5145966c..a6fa5212da4e 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -160,7 +160,7 @@ infracfg_ao: clock-controller@10001000 { }; pio: pinctrl@10005000 { - compatible = "mediatek,mt6779-pinctrl", "syscon"; + compatible = "mediatek,mt6779-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x11c20000 0 0x1000>, <0 0x11d10000 0 0x1000>, From patchwork Wed Oct 5 17:43:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 612617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9BC3C433F5 for ; Wed, 5 Oct 2022 17:44:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbiJERoa (ORCPT ); Wed, 5 Oct 2022 13:44:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230422AbiJERo1 (ORCPT ); Wed, 5 Oct 2022 13:44:27 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 267177E03D; Wed, 5 Oct 2022 10:44:22 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id ay36so11252122wmb.0; Wed, 05 Oct 2022 10:44:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=s74OAcrnJmEwMIg5y8kD13FcfZI0oHtteoKyxHIc6vU=; b=DRMySqDqwjrbpH70gOwqe0WMGRTSDMFh8/yL8ljpndp7oyx4hSQIulbomwARRFYlE7 WNzFT6jUCXwOwSNWqpb9EQYxTCF6mGPD2cGVkfcZx0tF/Pdm17wVwtivzwCayG9LUQFA x2ZOVQuVKBVcTRyfcDnXDlpkjFDCs7adnnmhKy7kinx3CXVjmr/q/PuN+BR4b5l2l4xU u86NoTByjk/y3+tFTM763rnbjP0jE/Bi13WWOP+SMhGRGYQEjl/w04YKZ8i3dbh7Vnlg VuAdpmFh4QzZV86dhCLi1/A6deyPOGN37M11+TcBA7Ic3RPIJ9+hbH6mIOohuJpxFiCK yBPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=s74OAcrnJmEwMIg5y8kD13FcfZI0oHtteoKyxHIc6vU=; b=adhtOieFN7qA2t0h+RRvgwDdp5k1mA7UARMoGagg/criNFZR5YVQIIMRSdENUwS58h AY1HLohE42q+7e4XxNFMvvkDcE1H+zkWZcJvEBQYFZGVshKsyL5JLJiC9OFYE6u68Qjh kgoPSlN0PWGNcTC0vd83/Tg7y4cm9pBT/RzJITBqPDC9QlKrdwMCQgagcYL53qz6WHkb xRsjkp4AXqnxsJI19PAF62Fp0d0UQdYKc9D0+xr2ftVyciOdytWMOOwwn3eZt103NzBd Mj66Tbw8numd8Ib/YHU8G/OOJvr23rbzks/DPDh+ULshKEFfEPaCwVWk6m7E1JqC+iqo RzIA== X-Gm-Message-State: ACrzQf0qcH5tT31GD1FRC/QQc6tYl/wVCJOQKV9CQ0M1cQxnRXsIVKrh 8BJAzfzNURPIfc0+NOHRrLQ= X-Google-Smtp-Source: AMsMyM6GP+roXxlZWBu8IJ3eVceDIiaqoVBHkMfHPKC43E8xi3E9O/UHR1awiOndfRsF+i0omj7tOA== X-Received: by 2002:a7b:c457:0:b0:3bf:f1eb:e943 with SMTP id l23-20020a7bc457000000b003bff1ebe943mr504773wmi.52.1664991860481; Wed, 05 Oct 2022 10:44:20 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.98]) by smtp.gmail.com with ESMTPSA id c6-20020a5d4146000000b0022a403954c3sm16075491wrq.42.2022.10.05.10.44.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 10:44:19 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Andy Teng , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/10] dt-bindings: pinctrl: mediatek, mt6779-pinctrl: Make gpio-ranges optional Date: Wed, 5 Oct 2022 20:43:36 +0300 Message-Id: <20221005174343.24240-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221005174343.24240-1-y.oudjana@protonmail.com> References: <20221005174343.24240-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yassine Oudjana The pin controller can function without specifying gpio-ranges. Remove it from required properties. Remove it for that reason and to prepare for adding other pin controllers which currently don't have the gpio-ranges property defined where they are used in DTS. This should allow dtbs_check to pass on those device trees. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index c6290bcdded6..d45f0e75a698 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -67,7 +67,6 @@ required: - reg-names - gpio-controller - "#gpio-cells" - - gpio-ranges - interrupt-controller - interrupts - "#interrupt-cells" From patchwork Wed Oct 5 17:43:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 612616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38E05C4332F for ; Wed, 5 Oct 2022 17:44:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230466AbiJERod (ORCPT ); Wed, 5 Oct 2022 13:44:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230453AbiJERoa (ORCPT ); Wed, 5 Oct 2022 13:44:30 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA0C67F09F; Wed, 5 Oct 2022 10:44:27 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id z13-20020a7bc7cd000000b003b5054c6f9bso1423683wmk.2; Wed, 05 Oct 2022 10:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=R5V9XL61CvLrWTitaAk3IV4z/7vaqFwBxHB+dhQiJmU=; b=VNuTzrG95urLF81YJdZboObgF6osUcvRWPCKgG0kxSvNaihUVHoSmdmDPraIjawVY0 Jv/07CbaY2fz2b9Z70wL1U7IbbzcNocW/6iFcuEC4zoefp4QJz3LBRcIWJMAWUQVbFsw /J5KPRo/RNI4J6UJa3nz9l+j/mprFLiX6kbsXsw2168SYy75+8sfFR09UxJEBOdj1+HR TQURzmbnc3qNFteNiS9R/+nR0ia+plqrVZaHKAwYJ79whx+2ECwgPrAAFenA+Eh6MYxa ZGJvUegV8cv03E+rhn2P60AZK/jXz7tijNayIhS0u8FuFqLXaCYsV1v13bMmwk+UG6hy Xf6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=R5V9XL61CvLrWTitaAk3IV4z/7vaqFwBxHB+dhQiJmU=; b=Pjau5LSiBa/0e0J2zOCdcnLZszdcudIhiMllkI6mdjqUYsw5VqST8DwZBSDqNfMMCl sxJcaVtYDgSg8TB/+LoHiO8s5JYybuYb5opoK09mKjXdAXxpsJ4mEJg9of/Geujf5lUn K1GL2FB1t2Bq15AcjE6VNs0pN/zmfyI6gGAU/R2C/7SKBxLsX9Emtmn6LqQP//J+voBN pqUMI8B5z1sSuYymrs2bYXP6gNXiis7eq9AbJFcW4G3xb+oVFXDJpzZlR+2vNLJRN21v B5qHkoSFt/T17onVaV5EpINwl80rywdvJoQKHThGnOcSCFlLTWAq6HkAtsotRWbjqzG6 Qqag== X-Gm-Message-State: ACrzQf24V3VuqU1BlkDrL6WRUhseqzIeJc7zazUERFlJZOUC25Llee/j ZvkUKTw3Jsb7z8E39Lqbwoc= X-Google-Smtp-Source: AMsMyM4cwnR+z1FcZoKQl6zwvm87KZHzi1VndZvrpT+wTyDDiFZ4ksar90GqtLG/6XvbLmerjJaC8w== X-Received: by 2002:a1c:7c12:0:b0:3b4:73e1:bdd7 with SMTP id x18-20020a1c7c12000000b003b473e1bdd7mr4300206wmc.32.1664991866047; Wed, 05 Oct 2022 10:44:26 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.98]) by smtp.gmail.com with ESMTPSA id c6-20020a5d4146000000b0022a403954c3sm16075491wrq.42.2022.10.05.10.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 10:44:25 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Andy Teng , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/10] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6795 Date: Wed, 5 Oct 2022 20:43:39 +0300 Message-Id: <20221005174343.24240-7-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221005174343.24240-1-y.oudjana@protonmail.com> References: <20221005174343.24240-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yassine Oudjana Combine MT6795 pin controller document into MT6779 one. In the process, replace the current interrupts property description with the one from the MT6795 document since it makes more sense. Also amend property descriptions with more detailed information that was available in the MT6795 document, and replace the current pinmux node name patterns with ones from it since they are more common across mediatek pin controller bindings. Signed-off-by: Yassine Oudjana --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 90 +++++-- .../pinctrl/mediatek,pinctrl-mt6795.yaml | 225 ------------------ 2 files changed, 73 insertions(+), 242 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index a2141eb0854e..64d4b6a3b5bd 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -8,6 +8,7 @@ title: Mediatek MT6779 Pin Controller maintainers: - Andy Teng + - AngeloGioacchino Del Regno - Sean Wang description: @@ -18,6 +19,7 @@ properties: compatible: enum: - mediatek,mt6779-pinctrl + - mediatek,mt6795-pinctrl - mediatek,mt6797-pinctrl reg: @@ -43,9 +45,8 @@ properties: interrupt-controller: true interrupts: - maxItems: 1 description: | - Specifies the summary IRQ. + The interrupt output to sysirq. "#interrupt-cells": const: 2 @@ -81,6 +82,28 @@ allOf: - const: iocfg_lt - const: iocfg_tl - const: eint + + interrupts: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: mediatek,mt6795-pinctrl + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: base + - const: eint + + interrupts: + minItems: 2 + maxItems: 2 - if: properties: compatible: @@ -111,32 +134,65 @@ allOf: - "#interrupt-cells" patternProperties: - '-[0-9]*$': + '-pins$': type: object additionalProperties: false patternProperties: - '-pins*$': + '^pins': type: object description: | A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = ; + } + }; + /* GPIO45 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = ; + } + }; + }; + $ref: "pinmux-node.yaml" properties: pinmux: description: - integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in boot/dts/-pinfunc.h directly. + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h + directly. bias-disable: true - bias-pull-up: true - - bias-pull-down: true + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull up PUPD/R0/R1 type define value. + description: | + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull down PUPD/R0/R1 type define value. + description: | + For normal pull down type, it is not necessary to specify R1R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. input-enable: true @@ -151,7 +207,7 @@ patternProperties: input-schmitt-disable: true drive-strength: - enum: [2, 4, 8, 12, 16] + enum: [2, 4, 6, 8, 10, 12, 14, 16] slew-rate: enum: [0, 1] @@ -218,8 +274,8 @@ examples: #interrupt-cells = <2>; interrupts = ; - mmc0_pins_default: mmc0-0 { - cmd-dat-pins { + mmc0_pins_default: mmc0-pins { + pins-cmd-dat { pinmux = , , , @@ -232,11 +288,11 @@ examples: input-enable; mediatek,pull-up-adv = <1>; }; - clk-pins { + pins-clk { pinmux = ; mediatek,pull-down-adv = <2>; }; - rst-pins { + pins-rst { pinmux = ; mediatek,pull-up-adv = <0>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml deleted file mode 100644 index 483fcdc60487..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml +++ /dev/null @@ -1,225 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Mediatek MT6795 Pin Controller - -maintainers: - - AngeloGioacchino Del Regno - - Sean Wang - -description: | - The Mediatek's Pin controller is used to control SoC pins. - -properties: - compatible: - const: mediatek,mt6795-pinctrl - - gpio-controller: true - - '#gpio-cells': - description: | - Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. - const: 2 - - gpio-ranges: - description: GPIO valid number range. - maxItems: 1 - - reg: - description: - Physical address base for gpio base and eint registers. - minItems: 2 - - reg-names: - items: - - const: base - - const: eint - - interrupt-controller: true - - '#interrupt-cells': - const: 2 - - interrupts: - description: The interrupt outputs to sysirq. - minItems: 2 - maxItems: 2 - -# PIN CONFIGURATION NODES -patternProperties: - '-pins$': - type: object - additionalProperties: false - patternProperties: - '^pins': - type: object - additionalProperties: false - description: | - A pinctrl node should contain at least one subnodes representing the - pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. - An example of using macro: - pincontroller { - /* GPIO0 set as multifunction GPIO0 */ - gpio-pins { - pins { - pinmux = ; - } - }; - /* GPIO45 set as multifunction SDA0 */ - i2c0-pins { - pins { - pinmux = ; - } - }; - }; - $ref: "pinmux-node.yaml" - - properties: - pinmux: - description: | - Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - - bias-pull-down: - oneOf: - - type: boolean - - enum: [100, 101, 102, 103] - description: mt6795 pull down PUPD/R0/R1 type define value. - description: | - For normal pull down type, it is not necessary to specify R1R0 - values; When pull down type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. - - bias-pull-up: - oneOf: - - type: boolean - - enum: [100, 101, 102, 103] - description: mt6795 pull up PUPD/R0/R1 type define value. - description: | - For normal pull up type, it is not necessary to specify R1R0 - values; When pull up type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. - - bias-disable: true - - output-high: true - - output-low: true - - input-enable: true - - input-disable: true - - input-schmitt-enable: true - - input-schmitt-disable: true - - mediatek,pull-up-adv: - description: | - Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - mediatek,pull-down-adv: - description: | - Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - required: - - pinmux - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - - reg-names - - interrupts - - interrupt-controller - - '#interrupt-cells' - - gpio-controller - - '#gpio-cells' - - gpio-ranges - -additionalProperties: false - -examples: - - | - #include - #include - #include - - soc { - #address-cells = <2>; - #size-cells = <2>; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt6795-pinctrl"; - reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; - reg-names = "base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 196>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - - i2c0-pins { - pins-sda-scl { - pinmux = , - ; - }; - }; - - mmc0-pins { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - bias-pull-down = ; - }; - - pins-rst { - pinmux = ; - bias-pull-up = ; - }; - }; - }; - }; From patchwork Wed Oct 5 17:43:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 612615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB2CEC433FE for ; Wed, 5 Oct 2022 17:44:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230462AbiJERog (ORCPT ); Wed, 5 Oct 2022 13:44:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230403AbiJERoc (ORCPT ); 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Wed, 05 Oct 2022 10:44:27 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Andy Teng , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/10] arm64: dts: mediatek: mt6797: Make pin configuration nodes follow DT bindings Date: Wed, 5 Oct 2022 20:43:40 +0300 Message-Id: <20221005174343.24240-8-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221005174343.24240-1-y.oudjana@protonmail.com> References: <20221005174343.24240-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yassine Oudjana Add -pins suffix to pin configuration nodes to follow DT bindings and pass dtbs_check. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 15616231022a..0c2b477184ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -135,70 +135,70 @@ pio: pinctrl@10005000 { gpio-controller; #gpio-cells = <2>; - uart0_pins_a: uart0 { + uart0_pins_a: uart0-pins { pins0 { pinmux = , ; }; }; - uart1_pins_a: uart1 { + uart1_pins_a: uart1-pins { pins1 { pinmux = , ; }; }; - i2c0_pins_a: i2c0 { + i2c0_pins_a: i2c0-pins { pins0 { pinmux = , ; }; }; - i2c1_pins_a: i2c1 { + i2c1_pins_a: i2c1-pins { pins1 { pinmux = , ; }; }; - i2c2_pins_a: i2c2 { + i2c2_pins_a: i2c2-pins { pins2 { pinmux = , ; }; }; - i2c3_pins_a: i2c3 { + i2c3_pins_a: i2c3-pins { pins3 { pinmux = , ; }; }; - i2c4_pins_a: i2c4 { + i2c4_pins_a: i2c4-pins { pins4 { pinmux = , ; }; }; - i2c5_pins_a: i2c5 { + i2c5_pins_a: i2c5-pins { pins5 { pinmux = , ; }; }; - i2c6_pins_a: i2c6 { + i2c6_pins_a: i2c6-pins { pins6 { pinmux = , ; }; }; - i2c7_pins_a: i2c7 { + i2c7_pins_a: i2c7-pins { pins7 { pinmux = , ; From patchwork Wed Oct 5 17:43:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 612614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5DAAC433FE for ; Wed, 5 Oct 2022 17:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231133AbiJERpI (ORCPT ); Wed, 5 Oct 2022 13:45:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229915AbiJERov (ORCPT ); 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Wed, 05 Oct 2022 10:44:31 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Andy Teng , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/10] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Document MT6735 pin controller bindings Date: Wed, 5 Oct 2022 20:43:42 +0300 Message-Id: <20221005174343.24240-10-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221005174343.24240-1-y.oudjana@protonmail.com> References: <20221005174343.24240-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yassine Oudjana Add bindings for the pin controller found on MediaTek MT6735 and MT6735M SoCs, including describing a method to manually specify a pin and function in the pinmux property making defining bindings for each pin/function combination unnecessary. The pin controllers on those SoCs are generally identical, with the only difference being the lack of MSDC2 pins (198-203) on MT6735M. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index f10d1d5543cb..66a0178caa8e 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -18,6 +18,8 @@ description: properties: compatible: enum: + - mediatek,mt6735-pinctrl + - mediatek,mt6735m-pinctrl - mediatek,mt6765-pinctrl - mediatek,mt6779-pinctrl - mediatek,mt6795-pinctrl @@ -61,6 +63,29 @@ required: allOf: - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt6735-pinctrl + - mediatek,mt6735m-pinctrl + then: + properties: + reg: + minItems: 8 + maxItems: 8 + + reg-names: + items: + - const: gpio + - const: iocfg0 + - const: iocfg1 + - const: iocfg2 + - const: iocfg3 + - const: iocfg4 + - const: iocfg5 + - const: eint - if: properties: compatible: @@ -185,6 +210,22 @@ patternProperties: } }; }; + The MTK_PIN_NO macro can also be used to select a pin and specify + a function index: + pincontroller { + /* Pin 19 set to function 0 (multifunction GPIO) */ + gpio-pins { + pins { + pinmux = <(MTK_PIN_NO(19) | 0)>; + }; + }; + /* Pin 172 set to function 1 (primary function) */ + msdc1-pins { + pins-cmd { + pinmux = <(MTK_PIN_NO(172) | 1)>; + }; + }; + }; $ref: "pinmux-node.yaml" properties: