From patchwork Thu Oct 6 21:25:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 613031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A67BC433F5 for ; Thu, 6 Oct 2022 21:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232377AbiJFVZx (ORCPT ); Thu, 6 Oct 2022 17:25:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232109AbiJFVZt (ORCPT ); Thu, 6 Oct 2022 17:25:49 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CD5AA50D3; Thu, 6 Oct 2022 14:25:36 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id AFB65660231C; Thu, 6 Oct 2022 22:25:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1665091534; bh=207iZwka39gr/mlqiQ+F1Jry3qyqaSd/jbong5V9Bto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HwkEnXrNv1sqBVTN/gmddeLe+mlKl6FYtyGHdSMEZW4MOtkL25rXifkRVppsaH7qt BiWchIV/lHklcHSBE9PVJCc0UKzKptsrauRAux0qGjVlq2PdTuCS4B8Di4fcW6U7FR TGwq7XYZQqrvNqHccplX5gIAicFqDgAMdhmx7zpRikKWQ1mZVQyYcjqEhPbKYgL4e8 Zx1f9gW9un+4gX8pz3O8cLgx3DIUJRIzL9+GPhCcCnlrMxH3ysAaXIYOGRM5SOJibS H+mWX92rIBbP3tq3tmzFv5Q+mZw/Vb1nNMEnMnN8+TADn1lF2YmL9qAPwNQIhn6ePJ yerEkUBqf7wfA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 1/5] arm64: dts: mediatek: asurada: Add display regulators Date: Thu, 6 Oct 2022 17:25:24 -0400 Message-Id: <20221006212528.103790-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221006212528.103790-1-nfraprado@collabora.com> References: <20221006212528.103790-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the regulators present on the Asurada platform that are used to power the internal and external displays. Tested-by: Chen-Yu Tsai Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v2: - Added missing vin-supply to regulators - Removed min/max-microvolt from regulators that are simple switches .../boot/dts/mediatek/mt8192-asurada.dtsi | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 4b314435f8fd..fafca7428539 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -23,6 +23,43 @@ memory@40000000 { reg = <0 0x40000000 0 0x80000000>; }; + pp1000_dpbrdg: regulator-1v0-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1000_dpbrdg_en_pins>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 19 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vs2_buck_reg>; + }; + + pp1000_mipibrdg: regulator-1v0-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1000_mipibrdg_en_pins>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vs2_buck_reg>; + }; + + pp1800_dpbrdg: regulator-1v8-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1800_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 126 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vio18_ldo_reg>; + }; + /* system wide LDO 1.8V power rail */ pp1800_ldo_g: regulator-1v8-g { compatible = "regulator-fixed"; @@ -34,6 +71,28 @@ pp1800_ldo_g: regulator-1v8-g { vin-supply = <&pp3300_g>; }; + pp1800_mipibrdg: regulator-1v8-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1800_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 128 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6359_vio18_ldo_reg>; + }; + + pp3300_dpbrdg: regulator-3v3-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp3300_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_dpbrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 26 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_g>; + }; + /* system wide switching 3.3V power rail */ pp3300_g: regulator-3v3-g { compatible = "regulator-fixed"; @@ -56,6 +115,17 @@ pp3300_ldo_z: regulator-3v3-z { vin-supply = <&ppvar_sys>; }; + pp3300_mipibrdg: regulator-3v3-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp3300_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_mipibrdg_en_pins>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 127 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_g>; + }; + /* separately switched 3.3V power rail */ pp3300_u: regulator-3v3-u { compatible = "regulator-fixed"; @@ -719,6 +789,48 @@ pins-wifi-kill { }; }; + pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + pp3300_wlan_pins: pp3300-wlan-pins { pins-pcie-en-pp3300-wlan { pinmux = ; From patchwork Thu Oct 6 21:25:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 613030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3628AC4167D for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1665091536; bh=G8nm/nR1H1cInj6GeXU+i9brDXiOkH96KSJVMB1aK08=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oeA/leyVaazoZ4TNaJlrJXFjfZf4avkodJMN+bDzDFEbwj9d2+1FodkkUbFsrdtbD 5AWlCPpo/fv3he4TYJZ1LtNZk+hWROaVrJoM2IXxw/WsSgU5aZ/ygj6qE3fLqGDsU2 BtcMsTk+Fl1j9QkCzKi1zT8iep/lMzikgHEN9ti6C+iLwdjg89W0Ka398sMknlqwMR KfBZmPQzHXo0C5q6sxiNoyf3a17Wb1GIAl/OfS37rksiFRX4WPtAbZT+CAsImiHH+H qEyOOTPuj2ep3Y2l17XwqMR80PWNrAP2Rd3xr4VCqVGe15ZpBUegyASWYepKhdIaMz p2RYtSHWplFuA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 2/5] arm64: dts: mediatek: asurada: Add display backlight Date: Thu, 6 Oct 2022 17:25:25 -0400 Message-Id: <20221006212528.103790-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221006212528.103790-1-nfraprado@collabora.com> References: <20221006212528.103790-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the display backlight for the Asurada platform. It relies on the display PWM controller, so also enable and configure this component. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Signed-off-by: Nícolas F. R. A. Prado --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index fafca7428539..666021ca4d4f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -23,6 +23,16 @@ memory@40000000 { reg = <0 0x40000000 0 0x80000000>; }; + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + power-supply = <&ppvar_sys>; + enable-gpios = <&pio 152 0>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + }; + pp1000_dpbrdg: regulator-1v0-dpbrdg { compatible = "regulator-fixed"; regulator-name = "pp1000_dpbrdg"; @@ -838,6 +848,17 @@ pins-pcie-en-pp3300-wlan { }; }; + pwm0_pins: pwm0-default-pins { + pins-pwm { + pinmux = ; + }; + + pins-inhibit { + pinmux = ; + output-high; + }; + }; + scp_pins: scp-pins { pins-vreq-vao { pinmux = ; @@ -899,6 +920,13 @@ &pmic { interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; }; +&pwm0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; +}; + &scp { status = "okay"; From patchwork Thu Oct 6 21:25:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 613597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 165C9C4332F for ; Thu, 6 Oct 2022 21:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232446AbiJFVZz (ORCPT ); Thu, 6 Oct 2022 17:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232184AbiJFVZw (ORCPT ); Thu, 6 Oct 2022 17:25:52 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AC82A50DC; Thu, 6 Oct 2022 14:25:39 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id CDF20660231F; Thu, 6 Oct 2022 22:25:36 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1665091538; bh=dXF4O4gpDnjt0O5eIiuVLOMCgRI/gmY9KdHbdkGVZ3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XUD8hw3DmVqJhDC4Io8seOVm10K/f+Z6vxROh99D/QSplerbbCjYnYGkkUCO1ETaK xtEYx0e/O3RSL6TwWdH9hUewsd65TwGAGpf4BLkUkcwAQdG5dNybJMzfJink0loOws 6mZsYWCJ0lPfBLSh9MhlXSQjijPNSkQlYgxuOIZ7kE5QKgmjGtZMNWKwpB1SteWTgd gXXRf46tZCISp+KHlHQtEzi6+e7HKDnblxWN3oks1HrTdrbgfcSk7Nine58hqjSU1y vf8RTumusWH2jEuwzP+93tWY8HRHSR3Qq5AXVgUB2dDfsOzu/vH02gPWkPHrkQ6Q7S x7Uk0M6vYM/Og== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 3/5] arm64: dts: mediatek: asurada: Enable internal display Date: Thu, 6 Oct 2022 17:25:26 -0400 Message-Id: <20221006212528.103790-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221006212528.103790-1-nfraprado@collabora.com> References: <20221006212528.103790-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The asurada platform has an ANX7625 bridge connecting the DSI's output to the internal eDP panel. Add and enable these devices in order to get a usable internal display. Tested-by: Chen-Yu Tsai Signed-off-by: Nícolas F. R. A. Prado --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 666021ca4d4f..ace44827de17 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -198,6 +198,14 @@ wifi_restricted_dma_region: wifi@c0000000 { }; }; +&dsi0 { + status = "okay"; +}; + +&dsi_out { + remote-endpoint = <&anx7625_in>; +}; + &i2c0 { status = "okay"; @@ -246,6 +254,53 @@ &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; + + anx_bridge: anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&anx7625_pins>; + enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_mipibrdg>; + vdd18-supply = <&pp1800_mipibrdg>; + vdd33-supply = <&pp3300_mipibrdg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&pp3300_mipibrdg>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + }; + }; }; &i2c7 { @@ -256,6 +311,10 @@ &i2c7 { pinctrl-0 = <&i2c7_pins>; }; +&mipi_tx0 { + status = "okay"; +}; + &mmc0 { status = "okay"; @@ -587,6 +646,20 @@ &pio { "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + anx7625_pins: anx7625-default-pins { + pins-out { + pinmux = , + ; + output-low; + }; + + pins-in { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; + cr50_int: cr50-irq-default-pins { pins-gsc-ap-int-odl { pinmux = ; From patchwork Thu Oct 6 21:25:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 613598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 979B0C433FE for ; Thu, 6 Oct 2022 21:25:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232432AbiJFVZy (ORCPT ); Thu, 6 Oct 2022 17:25:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232103AbiJFVZt (ORCPT ); Thu, 6 Oct 2022 17:25:49 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEB1CA50DD; Thu, 6 Oct 2022 14:25:40 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5F9FE660231D; Thu, 6 Oct 2022 22:25:38 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1665091539; bh=lp5EA9zGiSNS2l0ttqeR42/SM/7JzB0RtZb7ngSR3KM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DFOFOc86o7i+cXXHR1jvnkT4TxuB4o7GvpiUQj01jEDCdjdwWWU3VVbKm3keuKMoD itRayMm8vpl/kVlLPpfmItqNeEB4Q+TQUGrloK7bOI2jEcH66s9QJ9mq6wPPZMsyGo H8M22+NK1x0VUrtqPASPc1V81mWpdgllTshwuQ83n2M8fSvwSW2h1JRNcjuAiyMSMZ iWY/TD4Aowe8IVthAwJxIcbKXm4CiPsRnG7cYdnmLbL3qa6utqwFaDLuOx3rD1W/Sj bUTpXzeufkhN+k/aKct2WaOt8g20/+9+1ROvRglEIWB3Is5ye8YMjXOtFYm/PU+v++ f5FFH6lZc9s9Q== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 4/5] arm64: dts: mediatek: asurada: Enable audio support Date: Thu, 6 Oct 2022 17:25:27 -0400 Message-Id: <20221006212528.103790-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221006212528.103790-1-nfraprado@collabora.com> References: <20221006212528.103790-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable audio support for the Asurada platform. This consists of the machine sound card, the rt1015p codec for the speakers, the rt5682 codec for the headset, and the dmic codec for the internal microphone. HDMI audio support is left out for now since the DisplayPort chip required isn't enabled yet. Signed-off-by: Nícolas F. R. A. Prado --- Changes in v2: - Added this commit .../boot/dts/mediatek/mt8192-asurada.dtsi | 282 ++++++++++++++++++ 1 file changed, 282 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index ace44827de17..dac2d4f5e670 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -33,6 +33,12 @@ backlight_lcd0: backlight-lcd0 { default-brightness-level = <576>; }; + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + pp1000_dpbrdg: regulator-1v0-dpbrdg { compatible = "regulator-fixed"; regulator-name = "pp1000_dpbrdg"; @@ -196,6 +202,79 @@ wifi_restricted_dma_region: wifi@c0000000 { reg = <0 0xc0000000 0 0x4000000>; }; }; + + rt1015p: rt1015p { + compatible = "realtek,rt1015p"; + pinctrl-names = "default"; + pinctrl-0 = <&rt1015p_pins>; + sdb-gpios = <&pio 147 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + + sound: mt8192-sound { + compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682"; + mediatek,platform = <&afe>; + pinctrl-names = "aud_clk_mosi_off", + "aud_clk_mosi_on", + "aud_dat_mosi_off", + "aud_dat_mosi_on", + "aud_dat_miso_off", + "aud_dat_miso_on", + "vow_dat_miso_off", + "vow_dat_miso_on", + "vow_clk_miso_off", + "vow_clk_miso_on", + "aud_nle_mosi_off", + "aud_nle_mosi_on", + "aud_dat_miso2_off", + "aud_dat_miso2_on", + "aud_gpio_i2s3_off", + "aud_gpio_i2s3_on", + "aud_gpio_i2s8_off", + "aud_gpio_i2s8_on", + "aud_gpio_i2s9_off", + "aud_gpio_i2s9_on", + "aud_dat_mosi_ch34_off", + "aud_dat_mosi_ch34_on", + "aud_dat_miso_ch34_off", + "aud_dat_miso_ch34_on", + "aud_gpio_tdm_off", + "aud_gpio_tdm_on"; + pinctrl-0 = <&aud_clk_mosi_off_pins>; + pinctrl-1 = <&aud_clk_mosi_on_pins>; + pinctrl-2 = <&aud_dat_mosi_off_pins>; + pinctrl-3 = <&aud_dat_mosi_on_pins>; + pinctrl-4 = <&aud_dat_miso_off_pins>; + pinctrl-5 = <&aud_dat_miso_on_pins>; + pinctrl-6 = <&vow_dat_miso_off_pins>; + pinctrl-7 = <&vow_dat_miso_on_pins>; + pinctrl-8 = <&vow_clk_miso_off_pins>; + pinctrl-9 = <&vow_clk_miso_on_pins>; + pinctrl-10 = <&aud_nle_mosi_off_pins>; + pinctrl-11 = <&aud_nle_mosi_on_pins>; + pinctrl-12 = <&aud_dat_miso2_off_pins>; + pinctrl-13 = <&aud_dat_miso2_on_pins>; + pinctrl-14 = <&aud_gpio_i2s3_off_pins>; + pinctrl-15 = <&aud_gpio_i2s3_on_pins>; + pinctrl-16 = <&aud_gpio_i2s8_off_pins>; + pinctrl-17 = <&aud_gpio_i2s8_on_pins>; + pinctrl-18 = <&aud_gpio_i2s9_off_pins>; + pinctrl-19 = <&aud_gpio_i2s9_on_pins>; + pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; + pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; + pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; + pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; + pinctrl-24 = <&aud_gpio_tdm_off_pins>; + pinctrl-25 = <&aud_gpio_tdm_on_pins>; + + headset-codec { + sound-dai = <&rt5682>; + }; + + speaker-codecs { + sound-dai = <&rt1015p>; + }; + }; }; &dsi0 { @@ -227,6 +306,19 @@ &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; + + rt5682: rt5682@1a { + compatible = "realtek,rt5682i"; + reg = <0x1a>; + interrupts-extended = <&pio 18 IRQ_TYPE_LEVEL_LOW>; + realtek,jd-src = <1>; + realtek,btndet-delay = <16>; + #sound-dai-cells = <0>; + + AVDD-supply = <&mt6359_vio18_ldo_reg>; + MICVDD-supply = <&pp3300_g>; + VBAT-supply = <&pp3300_ldo_z>; + }; }; &i2c2 { @@ -660,6 +752,165 @@ pins-in { }; }; + aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { + pins-mosi-off { + pinmux = , + ; + }; + }; + + aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { + pins-mosi-on { + pinmux = , + ; + drive-strength = <10>; + }; + }; + + aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { + pins-miso-off { + pinmux = ; + }; + }; + + aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { + pins-miso-on { + pinmux = ; + }; + }; + + aud_dat_miso_off_pins: aud-dat-miso-off-pins { + pins-miso-off { + pinmux = , + ; + }; + }; + + aud_dat_miso_on_pins: aud-dat-miso-on-pins { + pins-miso-on { + pinmux = , + ; + drive-strength = <10>; + }; + }; + + aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { + pins-miso-off { + pinmux = ; + }; + }; + + aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { + pins-miso-on { + pinmux = ; + }; + }; + + aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { + pins-mosi-off { + pinmux = ; + }; + }; + + aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { + pins-mosi-on { + pinmux = ; + }; + }; + + aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { + pins-mosi-off { + pinmux = , + ; + }; + }; + + aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { + pins-mosi-on { + pinmux = , + ; + drive-strength = <10>; + }; + }; + + aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { + pins-i2s3-off { + pinmux = , + , + ; + }; + }; + + aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { + pins-i2s3-on { + pinmux = , + , + ; + }; + }; + + aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { + pins-i2s8-off { + pinmux = , + , + , + ; + }; + }; + + aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { + pins-i2s8-on { + pinmux = , + , + , + ; + }; + }; + + aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { + pins-i2s9-off { + pinmux = ; + }; + }; + + aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { + pins-i2s9-on { + pinmux = ; + }; + }; + + aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { + pins-tdm-off { + pinmux = , + , + , + ; + }; + }; + + aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { + pins-tdm-on { + pinmux = , + , + , + ; + }; + }; + + aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { + pins-nle-mosi-off { + pinmux = , + ; + }; + }; + + aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { + pins-nle-mosi-on { + pinmux = , + ; + }; + }; + cr50_int: cr50-irq-default-pins { pins-gsc-ap-int-odl { pinmux = ; @@ -932,6 +1183,13 @@ pins-inhibit { }; }; + rt1015p_pins: rt1015p-default-pins { + pins { + pinmux = ; + output-low; + }; + }; + scp_pins: scp-pins { pins-vreq-vao { pinmux = ; @@ -987,6 +1245,30 @@ pins-report-sw { output-low; }; }; + + vow_clk_miso_off_pins: vow-clk-miso-off-pins { + pins-miso-off { + pinmux = ; + }; + }; + + vow_clk_miso_on_pins: vow-clk-miso-on-pins { + pins-miso-on { + pinmux = ; + }; + }; + + vow_dat_miso_off_pins: vow-dat-miso-off-pins { + pins-miso-off { + pinmux = ; + }; + }; + + vow_dat_miso_on_pins: vow-dat-miso-on-pins { + pins-miso-on { + pinmux = ; + }; + }; }; &pmic { From patchwork Thu Oct 6 21:25:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 613029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49226C43219 for ; Thu, 6 Oct 2022 21:25:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232449AbiJFVZ5 (ORCPT ); Thu, 6 Oct 2022 17:25:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232190AbiJFVZw (ORCPT ); Thu, 6 Oct 2022 17:25:52 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 421A9A571A; Thu, 6 Oct 2022 14:25:42 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [IPv6:2600:4041:5b1a:cd00:524d:e95d:1a9c:492a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id E3D5D660230F; Thu, 6 Oct 2022 22:25:39 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1665091541; bh=2X8il5bV5d/ZjSiVrXx4NYjDMYkt9VJPEiLKp1Ds5UY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YQCxAaumyufWsY7kjrWXZrig+YtTpIyZC545MeQjJNmM0uUROlUBdNi4Fjg5IKu7A FqweZhPE9o+aC9SbqEZdFOO8cZ8Wy8toQyyYSwQD9BQOVcOG4k3HfzjUc6DalJdXF2 Nrz6h+EJ2XGFnMa1QTZhqS9sxUbsuDiBlOXvs6ZjsA9kK5Nn+SJlwxa1XS2OYGDGAz C0zg5EDs5yBcBEhj9XkzS7SZBGMX943umqu1E6VG1O9PJz9kJH7eOgsqz08CkNMmYQ m5OlYWFJM++EWPQCv6NyCIIu75+iJRNz4X+UWzvEmd9sCQMZLLAPQY3x7t/mGtDIWK C4tkmTAOr6IUA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: kernel@collabora.com, Chen-Yu Tsai , AngeloGioacchino Del Regno , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 5/5] arm64: dts: mediatek: asurada: Add aliases for i2c and mmc Date: Thu, 6 Oct 2022 17:25:28 -0400 Message-Id: <20221006212528.103790-6-nfraprado@collabora.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221006212528.103790-1-nfraprado@collabora.com> References: <20221006212528.103790-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add aliases for the i2c and mmc nodes on the Asurada platform DT to ensure that we get stable ids for those devices on userspace. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v2: - Added this commit arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index dac2d4f5e670..758ca42a6156 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -11,6 +11,18 @@ / { aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + mmc0 = &mmc0; + mmc1 = &mmc1; serial0 = &uart0; };