From patchwork Sun Oct 16 17:21:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 615582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01921C43217 for ; Sun, 16 Oct 2022 17:22:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229865AbiJPRWj (ORCPT ); Sun, 16 Oct 2022 13:22:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229887AbiJPRWg (ORCPT ); Sun, 16 Oct 2022 13:22:36 -0400 Received: from mail-qt1-x82d.google.com (mail-qt1-x82d.google.com [IPv6:2607:f8b0:4864:20::82d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B292930F74 for ; Sun, 16 Oct 2022 10:22:32 -0700 (PDT) Received: by mail-qt1-x82d.google.com with SMTP id z8so6547357qtv.5 for ; Sun, 16 Oct 2022 10:22:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JNDJJ9hQsj05js8AN30e2xU89fqRcxDiB8ewRytYETQ=; b=NK8IQzN/NmcAd2K1X5zPe5+iT1kNxjiVk+FyGrWPj+S6z858EtjqlxH0Fhz9EhGZWo HY0hUfzTqpiKwm11TH8ljQU4eKhOdVDBaaFWmjmVvqFkQx+AiQOLPGbkYrT/XZ4/c/4O lvYRpFrkVHEu5Tx1sTNXTw18B4+m1YV1Ga+0Arle7B6QP+YuY/Gdeq7IWg7fpQNKvJEY /pRobPKbhFKJ+M2vXT48rOClieF4OcEYTsc8Rh69Cv0MD+jSz7egfZcMbyFfuo5MUOwN BFX24I3V4CkMvk0EogkgenScuI75vb/R66zQ4o/v+vrxytLjoTFYTPhYzoMXwMHClG68 HawA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JNDJJ9hQsj05js8AN30e2xU89fqRcxDiB8ewRytYETQ=; b=3L8eNIjrrfjilcQI1/c6sw/z00GYLTDwrxpF6c+dPnWuYYW07Roy/BzFtGZQGyeoDQ c6nc8pAlY5HM6l5FFwnXoX2C1+VXwfNqwLZTsvrCTJ4Y27mrMvIIY39oRdgvSBVrNxxT CjQC80wKeRRgtUd0dfuo6bMdcoaBbqI6X/k+AWvfc9nvShjJb63QV+POiLB6v2I/jYSZ X7K/Y6HMUa1ZWxhWXlBk+ck4aEvDhe/9gQiigeU2Qbudurh5E7mf9zlotKFVRTYbFesE vGs1mwYCXiogES9ScIyNV24rlkIYKCt34Mrkh2lUTKOnRQ/cnIsbCUC7i2G9yjh/PRdQ DI5w== X-Gm-Message-State: ACrzQf2bG+T3khn1P8ygFt8ePDlTilaUjioeoszqlTvCw+J3YKxau2RJ 9BprG46/kc7qSLlmvlep5m9Hvw== X-Google-Smtp-Source: AMsMyM5F7Z2XedPYLoj42o5X9CaXDbS/Rbsc9zRFo7cwBTEqv84fll0Mo5l5l+eOoJe+1Y8nm7+udw== X-Received: by 2002:ac8:7fd3:0:b0:39c:c89d:4953 with SMTP id b19-20020ac87fd3000000b0039cc89d4953mr5904512qtk.161.1665940951754; Sun, 16 Oct 2022 10:22:31 -0700 (PDT) Received: from krzk-bin.hsd1.pa.comcast.net ([2601:42:0:3450:9b13:d679:7b5b:6921]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b003431446588fsm6051008qtt.5.2022.10.16.10.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 10:22:31 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 01/17] arm64: dts: qcom: sm8250: align TLMM pin configuration with DT schema Date: Sun, 16 Oct 2022 13:21:56 -0400 Message-Id: <20221016172212.49105-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Drop also unneeded split between mux and config. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 +- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 38 +- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 16 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 556 +++++++----------- 4 files changed, 239 insertions(+), 383 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index bf8077a1cf9a..62aa32f460ad 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1210,33 +1210,33 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; - lt9611_irq_pin: lt9611-irq { + lt9611_irq_pin: lt9611-irq-state { pins = "gpio63"; function = "gpio"; bias-disable; }; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio77"; function = "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index a102aa5efa32..9db6136321b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -799,31 +799,19 @@ wcd_tx: wcd9380-tx@0,3 { &tlmm { gpio-reserved-ranges = <28 4>, <40 4>; - wcd938x_reset_default: wcd938x_reset_default { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - output-high; - }; - }; - - wcd938x_reset_sleep: wcd938x_reset_sleep { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - bias-disable; - output-low; - }; + wcd938x_reset_default: wcd938x-reset-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + output-high; + }; + + wcd938x_reset_sleep: wcd938x-reset-sleep-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 549e0a2aa9fe..72162852fae7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -582,34 +582,34 @@ &slpi { &tlmm { gpio-reserved-ranges = <40 4>, <52 4>; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <16>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <16>; bias-pull-up; }; }; - mdm2ap_default: mdm2ap-default { + mdm2ap_default: mdm2ap-default-state { pins = "gpio1", "gpio3"; function = "gpio"; drive-strength = <8>; bias-disable; }; - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins = "gpio39"; function = "gpio"; drive-strength = <2>; @@ -617,14 +617,14 @@ ts_int_default: ts-int-default { input-enable; }; - ap2mdm_default: ap2mdm-default { + ap2mdm_default: ap2mdm-default-state { pins = "gpio56", "gpio57"; function = "gpio"; drive-strength = <16>; bias-disable; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio77"; function = "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index e0416d611b66..7eac3ba90c63 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3798,8 +3798,8 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 181>; wakeup-parent = <&pdc>; - cci0_default: cci0-default { - cci0_i2c0_default: cci0-i2c0-default { + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { /* SDA, SCL */ pins = "gpio101", "gpio102"; function = "cci_i2c"; @@ -3808,7 +3808,7 @@ cci0_i2c0_default: cci0-i2c0-default { drive-strength = <2>; /* 2 mA */ }; - cci0_i2c1_default: cci0-i2c1-default { + cci0_i2c1_default: cci0-i2c1-default-pins { /* SDA, SCL */ pins = "gpio103", "gpio104"; function = "cci_i2c"; @@ -3818,8 +3818,8 @@ cci0_i2c1_default: cci0-i2c1-default { }; }; - cci0_sleep: cci0-sleep { - cci0_i2c0_sleep: cci0-i2c0-sleep { + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { /* SDA, SCL */ pins = "gpio101", "gpio102"; function = "cci_i2c"; @@ -3828,7 +3828,7 @@ cci0_i2c0_sleep: cci0-i2c0-sleep { bias-pull-down; }; - cci0_i2c1_sleep: cci0-i2c1-sleep { + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { /* SDA, SCL */ pins = "gpio103", "gpio104"; function = "cci_i2c"; @@ -3838,8 +3838,8 @@ cci0_i2c1_sleep: cci0-i2c1-sleep { }; }; - cci1_default: cci1-default { - cci1_i2c0_default: cci1-i2c0-default { + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { /* SDA, SCL */ pins = "gpio105","gpio106"; function = "cci_i2c"; @@ -3848,7 +3848,7 @@ cci1_i2c0_default: cci1-i2c0-default { drive-strength = <2>; /* 2 mA */ }; - cci1_i2c1_default: cci1-i2c1-default { + cci1_i2c1_default: cci1-i2c1-default-pins { /* SDA, SCL */ pins = "gpio107","gpio108"; function = "cci_i2c"; @@ -3858,8 +3858,8 @@ cci1_i2c1_default: cci1-i2c1-default { }; }; - cci1_sleep: cci1-sleep { - cci1_i2c0_sleep: cci1-i2c0-sleep { + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { /* SDA, SCL */ pins = "gpio105","gpio106"; function = "cci_i2c"; @@ -3868,7 +3868,7 @@ cci1_i2c0_sleep: cci1-i2c0-sleep { drive-strength = <2>; /* 2 mA */ }; - cci1_i2c1_sleep: cci1-i2c1-sleep { + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { /* SDA, SCL */ pins = "gpio107","gpio108"; function = "cci_i2c"; @@ -3878,22 +3878,22 @@ cci1_i2c1_sleep: cci1-i2c1-sleep { }; }; - pri_mi2s_active: pri-mi2s-active { - sclk { + pri_mi2s_active: pri-mi2s-active-state { + sclk-pins { pins = "gpio138"; function = "mi2s0_sck"; drive-strength = <8>; bias-disable; }; - ws { + ws-pins { pins = "gpio141"; function = "mi2s0_ws"; drive-strength = <8>; output-high; }; - data0 { + data0-pins { pins = "gpio139"; function = "mi2s0_data0"; drive-strength = <8>; @@ -3901,7 +3901,7 @@ data0 { output-high; }; - data1 { + data1-pins { pins = "gpio140"; function = "mi2s0_data1"; drive-strength = <8>; @@ -3909,632 +3909,500 @@ data1 { }; }; - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio28", "gpio29"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio28", "gpio29"; + function = "qup0"; + drive-strength = <2>; + bias-disable; }; - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-disable; }; - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio115", "gpio116"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio115", "gpio116"; + function = "qup2"; + drive-strength = <2>; + bias-disable; }; - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio119", "gpio120"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio119", "gpio120"; + function = "qup3"; + drive-strength = <2>; + bias-disable; }; - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio8", "gpio9"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio8", "gpio9"; + function = "qup4"; + drive-strength = <2>; + bias-disable; }; - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio12", "gpio13"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio12", "gpio13"; + function = "qup5"; + drive-strength = <2>; + bias-disable; }; - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio16", "gpio17"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio16", "gpio17"; + function = "qup6"; + drive-strength = <2>; + bias-disable; }; - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio20", "gpio21"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio20", "gpio21"; + function = "qup7"; + drive-strength = <2>; + bias-disable; }; - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio24", "gpio25"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio24", "gpio25"; + function = "qup8"; + drive-strength = <2>; + bias-disable; }; - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio125", "gpio126"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio125", "gpio126"; + function = "qup9"; + drive-strength = <2>; + bias-disable; }; - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio129", "gpio130"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio129", "gpio130"; + function = "qup10"; + drive-strength = <2>; + bias-disable; }; - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio60", "gpio61"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio60", "gpio61"; + function = "qup11"; + drive-strength = <2>; + bias-disable; }; - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio32", "gpio33"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio32", "gpio33"; + function = "qup12"; + drive-strength = <2>; + bias-disable; }; - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio36", "gpio37"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio36", "gpio37"; + function = "qup13"; + drive-strength = <2>; + bias-disable; }; - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio40", "gpio41"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio40", "gpio41"; + function = "qup14"; + drive-strength = <2>; + bias-disable; }; - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio44", "gpio45"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio44", "gpio45"; + function = "qup15"; + drive-strength = <2>; + bias-disable; }; - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio48", "gpio49"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c16_default: qup-i2c16-default-state { + pins = "gpio48", "gpio49"; + function = "qup16"; + drive-strength = <2>; + bias-disable; }; - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio52", "gpio53"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c17_default: qup-i2c17-default-state { + pins = "gpio52", "gpio53"; + function = "qup17"; + drive-strength = <2>; + bias-disable; }; - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio56", "gpio57"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c18_default: qup-i2c18-default-state { + pins = "gpio56", "gpio57"; + function = "qup18"; + drive-strength = <2>; + bias-disable; }; - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c19_default: qup-i2c19-default-state { + pins = "gpio0", "gpio1"; + function = "qup19"; + drive-strength = <2>; + bias-disable; }; - qup_spi0_cs: qup-spi0-cs { + qup_spi0_cs: qup-spi0-cs-state { pins = "gpio31"; function = "qup0"; }; - qup_spi0_cs_gpio: qup-spi0-cs-gpio { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins = "gpio31"; function = "gpio"; }; - qup_spi0_data_clk: qup-spi0-data-clk { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins = "gpio28", "gpio29", "gpio30"; function = "qup0"; }; - qup_spi1_cs: qup-spi1-cs { + qup_spi1_cs: qup-spi1-cs-state { pins = "gpio7"; function = "qup1"; }; - qup_spi1_cs_gpio: qup-spi1-cs-gpio { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins = "gpio7"; function = "gpio"; }; - qup_spi1_data_clk: qup-spi1-data-clk { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins = "gpio4", "gpio5", "gpio6"; function = "qup1"; }; - qup_spi2_cs: qup-spi2-cs { + qup_spi2_cs: qup-spi2-cs-state { pins = "gpio118"; function = "qup2"; }; - qup_spi2_cs_gpio: qup-spi2-cs-gpio { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins = "gpio118"; function = "gpio"; }; - qup_spi2_data_clk: qup-spi2-data-clk { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins = "gpio115", "gpio116", "gpio117"; function = "qup2"; }; - qup_spi3_cs: qup-spi3-cs { + qup_spi3_cs: qup-spi3-cs-state { pins = "gpio122"; function = "qup3"; }; - qup_spi3_cs_gpio: qup-spi3-cs-gpio { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins = "gpio122"; function = "gpio"; }; - qup_spi3_data_clk: qup-spi3-data-clk { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins = "gpio119", "gpio120", "gpio121"; function = "qup3"; }; - qup_spi4_cs: qup-spi4-cs { + qup_spi4_cs: qup-spi4-cs-state { pins = "gpio11"; function = "qup4"; }; - qup_spi4_cs_gpio: qup-spi4-cs-gpio { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins = "gpio11"; function = "gpio"; }; - qup_spi4_data_clk: qup-spi4-data-clk { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins = "gpio8", "gpio9", "gpio10"; function = "qup4"; }; - qup_spi5_cs: qup-spi5-cs { + qup_spi5_cs: qup-spi5-cs-state { pins = "gpio15"; function = "qup5"; }; - qup_spi5_cs_gpio: qup-spi5-cs-gpio { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins = "gpio15"; function = "gpio"; }; - qup_spi5_data_clk: qup-spi5-data-clk { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins = "gpio12", "gpio13", "gpio14"; function = "qup5"; }; - qup_spi6_cs: qup-spi6-cs { + qup_spi6_cs: qup-spi6-cs-state { pins = "gpio19"; function = "qup6"; }; - qup_spi6_cs_gpio: qup-spi6-cs-gpio { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins = "gpio19"; function = "gpio"; }; - qup_spi6_data_clk: qup-spi6-data-clk { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins = "gpio16", "gpio17", "gpio18"; function = "qup6"; }; - qup_spi7_cs: qup-spi7-cs { + qup_spi7_cs: qup-spi7-cs-state { pins = "gpio23"; function = "qup7"; }; - qup_spi7_cs_gpio: qup-spi7-cs-gpio { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins = "gpio23"; function = "gpio"; }; - qup_spi7_data_clk: qup-spi7-data-clk { + qup_spi7_data_clk: qup-spi7-data-clk-state { pins = "gpio20", "gpio21", "gpio22"; function = "qup7"; }; - qup_spi8_cs: qup-spi8-cs { + qup_spi8_cs: qup-spi8-cs-state { pins = "gpio27"; function = "qup8"; }; - qup_spi8_cs_gpio: qup-spi8-cs-gpio { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins = "gpio27"; function = "gpio"; }; - qup_spi8_data_clk: qup-spi8-data-clk { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins = "gpio24", "gpio25", "gpio26"; function = "qup8"; }; - qup_spi9_cs: qup-spi9-cs { + qup_spi9_cs: qup-spi9-cs-state { pins = "gpio128"; function = "qup9"; }; - qup_spi9_cs_gpio: qup-spi9-cs-gpio { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins = "gpio128"; function = "gpio"; }; - qup_spi9_data_clk: qup-spi9-data-clk { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins = "gpio125", "gpio126", "gpio127"; function = "qup9"; }; - qup_spi10_cs: qup-spi10-cs { + qup_spi10_cs: qup-spi10-cs-state { pins = "gpio132"; function = "qup10"; }; - qup_spi10_cs_gpio: qup-spi10-cs-gpio { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins = "gpio132"; function = "gpio"; }; - qup_spi10_data_clk: qup-spi10-data-clk { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins = "gpio129", "gpio130", "gpio131"; function = "qup10"; }; - qup_spi11_cs: qup-spi11-cs { + qup_spi11_cs: qup-spi11-cs-state { pins = "gpio63"; function = "qup11"; }; - qup_spi11_cs_gpio: qup-spi11-cs-gpio { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins = "gpio63"; function = "gpio"; }; - qup_spi11_data_clk: qup-spi11-data-clk { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins = "gpio60", "gpio61", "gpio62"; function = "qup11"; }; - qup_spi12_cs: qup-spi12-cs { + qup_spi12_cs: qup-spi12-cs-state { pins = "gpio35"; function = "qup12"; }; - qup_spi12_cs_gpio: qup-spi12-cs-gpio { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins = "gpio35"; function = "gpio"; }; - qup_spi12_data_clk: qup-spi12-data-clk { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins = "gpio32", "gpio33", "gpio34"; function = "qup12"; }; - qup_spi13_cs: qup-spi13-cs { + qup_spi13_cs: qup-spi13-cs-state { pins = "gpio39"; function = "qup13"; }; - qup_spi13_cs_gpio: qup-spi13-cs-gpio { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins = "gpio39"; function = "gpio"; }; - qup_spi13_data_clk: qup-spi13-data-clk { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins = "gpio36", "gpio37", "gpio38"; function = "qup13"; }; - qup_spi14_cs: qup-spi14-cs { + qup_spi14_cs: qup-spi14-cs-state { pins = "gpio43"; function = "qup14"; }; - qup_spi14_cs_gpio: qup-spi14-cs-gpio { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins = "gpio43"; function = "gpio"; }; - qup_spi14_data_clk: qup-spi14-data-clk { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins = "gpio40", "gpio41", "gpio42"; function = "qup14"; }; - qup_spi15_cs: qup-spi15-cs { + qup_spi15_cs: qup-spi15-cs-state { pins = "gpio47"; function = "qup15"; }; - qup_spi15_cs_gpio: qup-spi15-cs-gpio { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins = "gpio47"; function = "gpio"; }; - qup_spi15_data_clk: qup-spi15-data-clk { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins = "gpio44", "gpio45", "gpio46"; function = "qup15"; }; - qup_spi16_cs: qup-spi16-cs { + qup_spi16_cs: qup-spi16-cs-state { pins = "gpio51"; function = "qup16"; }; - qup_spi16_cs_gpio: qup-spi16-cs-gpio { + qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { pins = "gpio51"; function = "gpio"; }; - qup_spi16_data_clk: qup-spi16-data-clk { + qup_spi16_data_clk: qup-spi16-data-clk-state { pins = "gpio48", "gpio49", "gpio50"; function = "qup16"; }; - qup_spi17_cs: qup-spi17-cs { + qup_spi17_cs: qup-spi17-cs-state { pins = "gpio55"; function = "qup17"; }; - qup_spi17_cs_gpio: qup-spi17-cs-gpio { + qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { pins = "gpio55"; function = "gpio"; }; - qup_spi17_data_clk: qup-spi17-data-clk { + qup_spi17_data_clk: qup-spi17-data-clk-state { pins = "gpio52", "gpio53", "gpio54"; function = "qup17"; }; - qup_spi18_cs: qup-spi18-cs { + qup_spi18_cs: qup-spi18-cs-state { pins = "gpio59"; function = "qup18"; }; - qup_spi18_cs_gpio: qup-spi18-cs-gpio { + qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { pins = "gpio59"; function = "gpio"; }; - qup_spi18_data_clk: qup-spi18-data-clk { + qup_spi18_data_clk: qup-spi18-data-clk-state { pins = "gpio56", "gpio57", "gpio58"; function = "qup18"; }; - qup_spi19_cs: qup-spi19-cs { + qup_spi19_cs: qup-spi19-cs-state { pins = "gpio3"; function = "qup19"; }; - qup_spi19_cs_gpio: qup-spi19-cs-gpio { + qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { pins = "gpio3"; function = "gpio"; }; - qup_spi19_data_clk: qup-spi19-data-clk { + qup_spi19_data_clk: qup-spi19-data-clk-state { pins = "gpio0", "gpio1", "gpio2"; function = "qup19"; }; - qup_uart2_default: qup-uart2-default { - mux { - pins = "gpio117", "gpio118"; - function = "qup2"; - }; + qup_uart2_default: qup-uart2-default-state { + pins = "gpio117", "gpio118"; + function = "qup2"; }; - qup_uart6_default: qup-uart6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; + qup_uart6_default: qup-uart6-default-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "qup6"; }; - qup_uart12_default: qup-uart12-default { - mux { - pins = "gpio34", "gpio35"; - function = "qup12"; - }; + qup_uart12_default: qup-uart12-default-state { + pins = "gpio34", "gpio35"; + function = "qup12"; }; - qup_uart17_default: qup-uart17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; + qup_uart17_default: qup-uart17-default-state { + pins = "gpio52", "gpio53", "gpio54", "gpio55"; + function = "qup17"; }; - qup_uart18_default: qup-uart18-default { - mux { - pins = "gpio58", "gpio59"; - function = "qup18"; - }; + qup_uart18_default: qup-uart18-default-state { + pins = "gpio58", "gpio59"; + function = "qup18"; }; - tert_mi2s_active: tert-mi2s-active { - sck { + tert_mi2s_active: tert-mi2s-active-state { + sck-pins { pins = "gpio133"; function = "mi2s2_sck"; drive-strength = <8>; bias-disable; }; - data0 { + data0-pins { pins = "gpio134"; function = "mi2s2_data0"; drive-strength = <8>; @@ -4542,7 +4410,7 @@ data0 { output-high; }; - ws { + ws-pins { pins = "gpio135"; function = "mi2s2_ws"; drive-strength = <8>; @@ -4550,42 +4418,42 @@ ws { }; }; - sdc2_sleep_state: sdc2-sleep { - clk { + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { pins = "sdc2_clk"; drive-strength = <2>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <2>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <2>; bias-pull-up; }; }; - pcie0_default_state: pcie0-default { - perst { + pcie0_default_state: pcie0-default-state { + perst-pins { pins = "gpio79"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio80"; function = "pci_e0"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio81"; function = "gpio"; drive-strength = <2>; @@ -4593,22 +4461,22 @@ wake { }; }; - pcie1_default_state: pcie1-default { - perst { + pcie1_default_state: pcie1-default-state { + perst-pins { pins = "gpio82"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio83"; function = "pci_e1"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio84"; function = "gpio"; drive-strength = <2>; @@ -4616,22 +4484,22 @@ wake { }; }; - pcie2_default_state: pcie2-default { - perst { + pcie2_default_state: pcie2-default-state { + perst-pins { pins = "gpio85"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio86"; function = "pci_e2"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio87"; 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Sun, 16 Oct 2022 10:22:32 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 02/17] arm64: dts: qcom: sm8250-sony-xperia-edo: fix touchscreen bias-disable Date: Sun, 16 Oct 2022 13:21:57 -0400 Message-Id: <20221016172212.49105-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The property to disable bias is "bias-disable". Fixes: e76c7e1f15fe ("arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen") Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 72162852fae7..601a21c381f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -613,7 +613,7 @@ ts_int_default: ts-int-default-state { pins = "gpio39"; function = "gpio"; drive-strength = <2>; - bias-disabled; + bias-disable; input-enable; }; From patchwork Sun Oct 16 17:22:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 615581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F4C8C4321E for ; Sun, 16 Oct 2022 17:22:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229956AbiJPRWt (ORCPT ); Sun, 16 Oct 2022 13:22:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229971AbiJPRWq (ORCPT ); Sun, 16 Oct 2022 13:22:46 -0400 Received: from mail-qk1-x731.google.com (mail-qk1-x731.google.com [IPv6:2607:f8b0:4864:20::731]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8EEF33344 for ; Sun, 16 Oct 2022 10:22:39 -0700 (PDT) Received: by mail-qk1-x731.google.com with SMTP id t25so5460440qkm.2 for ; Sun, 16 Oct 2022 10:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IP8p9vKToYJMy7wcnsAiwE01U8L1mn26stcaAumSsjA=; b=YMXLKK9xvTY9noqnf5q27iT1Khsyi1SUgdPZHhxV8Xo1pNBvnfvaSGBNcvqN0Di5QC IXdNB90nDwhZxxUmC47esow0oLJOnCWI/jE3W5kEt3Km9K6TWm8SRgOHnxE5hia0K8rv rQdtiUdEVYyf3rtICN2M7T5W+ZAiwESN9BGFxVPQfBB8gl9DzkJ/onsQHUf0jD+oTdwU MNh5DmgkNb+0aV/gac44ULr1f71wR1Jpu4YJ34Ib1AUqA7/taxuwTypvk/MoZfkcpTmJ IwJqNBCN6HecRbOlBuCgI98RN7I1K8GzowLHTeKu4HdYcgRZCB7q43cYmBf98kn3wiPk x9AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IP8p9vKToYJMy7wcnsAiwE01U8L1mn26stcaAumSsjA=; b=DppF/P06Zah5xi8oTKo8m5HLX/pRxgvouuDDSwCYm2ExSR7Q7AHoGzZPQWsQ4u3+vU qWwd+fIr588sPoDE8ZzZAnrEvU+wjqN4w6NqSckkBE3DsOXXUSJqDTUoIsnAU0w8nBf3 rKd5GILtrBC1y8l4hjAt7HOLodMITHShL09KRuEwVcN/seF3vbH5Yya++Ai/CAffpzEL qjFknTkgq8klp1yW/z1OdN3wjpy8qFGO7SnZCj6bMzRGCNCgMQArM8DNX7ZPQtPxDe0o ju2Dl5iwKYlFIFslwAUfxzU3Vh77saiyXL/nY7fhCrrpmwGKhHI35atn9DAgwsJOedK2 NuaA== X-Gm-Message-State: ACrzQf2uhoTcQqMDdF2vEuaIABGmtNRP7bMOaS46pwa1pcBNeY1jiJ+X uqKM0u0rPEB32TIFr8dndrt1Dw== X-Google-Smtp-Source: AMsMyM5XUSx92w88r8BqIOmw6M1ooQckCyuDr6aLX08Iaxc3Lu05306F0hVu7oSwahRM3bKs1/hL8A== X-Received: by 2002:a05:620a:10a1:b0:6ed:3b23:6991 with SMTP id h1-20020a05620a10a100b006ed3b236991mr4980209qkk.683.1665940958200; Sun, 16 Oct 2022 10:22:38 -0700 (PDT) Received: from krzk-bin.hsd1.pa.comcast.net ([2601:42:0:3450:9b13:d679:7b5b:6921]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b003431446588fsm6051008qtt.5.2022.10.16.10.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 10:22:37 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 05/17] arm64: dts: qcom: sc7280-herobrine: correct number of gpio-line-names Date: Sun, 16 Oct 2022 13:22:00 -0400 Message-Id: <20221016172212.49105-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org There are 175 GPIOs (gpio0-174). Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi | 1 - 4 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index f0f26af1e421..4e0b013e25f4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -372,5 +372,6 @@ &tlmm { "", /* 170 */ "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", + "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts index ccbe50b6249a..739e81bd6d68 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts @@ -328,6 +328,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index c1a671968725..c8ff13db30b9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -358,6 +358,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 4566722bf4dd..3dff610fb946 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -321,6 +321,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; From patchwork Sun Oct 16 17:22:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 615578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC3FBC433FE for ; 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Sun, 16 Oct 2022 10:22:40 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 07/17] arm64: dts: qcom: msm8953: align TLMM pin configuration with DT schema Date: Sun, 16 Oct 2022 13:22:02 -0400 Message-Id: <20221016172212.49105-8-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm632-fairphone-fp3.dtb: pinctrl@1000000: 'cd-off-pins', 'cd-on-pins', 'gpio-key-default-pins', .... do not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 70 +++++++++++++-------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 6b992a6d56c1..db94e6fd18f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -460,229 +460,229 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; - uart_console_active: uart-console-active-pins { + uart_console_active: uart-console-active-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; drive-strength = <2>; bias-disable; }; - uart_console_sleep: uart-console-sleep-pins { + uart_console_sleep: uart-console-sleep-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; drive-strength = <2>; bias-pull-down; }; - sdc1_clk_on: sdc1-clk-on-pins { + sdc1_clk_on: sdc1-clk-on-state { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - sdc1_clk_off: sdc1-clk-off-pins { + sdc1_clk_off: sdc1-clk-off-state { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - sdc1_cmd_on: sdc1-cmd-on-pins { + sdc1_cmd_on: sdc1-cmd-on-state { pins = "sdc1_cmd"; bias-disable; drive-strength = <10>; }; - sdc1_cmd_off: sdc1-cmd-off-pins { + sdc1_cmd_off: sdc1-cmd-off-state { pins = "sdc1_cmd"; bias-disable; drive-strength = <2>; }; - sdc1_data_on: sdc1-data-on-pins { + sdc1_data_on: sdc1-data-on-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - sdc1_data_off: sdc1-data-off-pins { + sdc1_data_off: sdc1-data-off-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - sdc1_rclk_on: sdc1-rclk-on-pins { + sdc1_rclk_on: sdc1-rclk-on-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc1_rclk_off: sdc1-rclk-off-pins { + sdc1_rclk_off: sdc1-rclk-off-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc2_clk_on: sdc2-clk-on-pins { + sdc2_clk_on: sdc2-clk-on-state { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - sdc2_clk_off: sdc2-clk-off-pins { + sdc2_clk_off: sdc2-clk-off-state { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - sdc2_cmd_on: sdc2-cmd-on-pins { + sdc2_cmd_on: sdc2-cmd-on-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc2_cmd_off: sdc2-cmd-off-pins { + sdc2_cmd_off: sdc2-cmd-off-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - sdc2_data_on: sdc2-data-on-pins { + sdc2_data_on: sdc2-data-on-state { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; - sdc2_data_off: sdc2-data-off-pins { + sdc2_data_off: sdc2-data-off-state { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; }; - sdc2_cd_on: cd-on-pins { + sdc2_cd_on: cd-on-state { pins = "gpio133"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - sdc2_cd_off: cd-off-pins { + sdc2_cd_off: cd-off-state { pins = "gpio133"; function = "gpio"; drive-strength = <2>; bias-disable; }; - gpio_key_default: gpio-key-default-pins { + gpio_key_default: gpio-key-default-state { pins = "gpio85"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - i2c_1_default: i2c-1-default-pins { + i2c_1_default: i2c-1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; - i2c_1_sleep: i2c-1-sleep-pins { + i2c_1_sleep: i2c-1-sleep-state { pins = "gpio2", "gpio3"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_2_default: i2c-2-default-pins { + i2c_2_default: i2c-2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - i2c_2_sleep: i2c-2-sleep-pins { + i2c_2_sleep: i2c-2-sleep-state { pins = "gpio6", "gpio7"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_3_default: i2c-3-default-pins { + i2c_3_default: i2c-3-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; drive-strength = <2>; bias-disable; }; - i2c_3_sleep: i2c-3-sleep-pins { + i2c_3_sleep: i2c-3-sleep-state { pins = "gpio10", "gpio11"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_4_default: i2c-4-default-pins { + i2c_4_default: i2c-4-default-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; - i2c_4_sleep: i2c-4-sleep-pins { + i2c_4_sleep: i2c-4-sleep-state { pins = "gpio14", "gpio15"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_5_default: i2c-5-default-pins { + i2c_5_default: i2c-5-default-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; - i2c_5_sleep: i2c-5-sleep-pins { + i2c_5_sleep: i2c-5-sleep-state { pins = "gpio18", "gpio19"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_6_default: i2c-6-default-pins { + i2c_6_default: i2c-6-default-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; - i2c_6_sleep: i2c-6-sleep-pins { + i2c_6_sleep: i2c-6-sleep-state { pins = "gpio22", "gpio23"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_7_default: i2c-7-default-pins { + i2c_7_default: i2c-7-default-state { pins = "gpio135", "gpio136"; function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; - i2c_7_sleep: i2c-7-sleep-pins { + i2c_7_sleep: i2c-7-sleep-state { pins = "gpio135", "gpio136"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_8_default: i2c-8-default-pins { + i2c_8_default: i2c-8-default-state { pins = "gpio98", "gpio99"; function = "blsp_i2c8"; drive-strength = <2>; bias-disable; }; - i2c_8_sleep: i2c-8-sleep-pins { + i2c_8_sleep: i2c-8-sleep-state { pins = "gpio98", "gpio99"; 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Sun, 16 Oct 2022 10:22:41 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 08/17] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema Date: Sun, 16 Oct 2022 13:22:03 -0400 Message-Id: <20221016172212.49105-9-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm845-lg-judyln.dtb: gpios@c000: 'vol-up-active-pins' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 20f275f8694d..1eb423e4be24 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -604,7 +604,7 @@ pinconf { }; &pm8998_gpio { - vol_up_pin_a: vol-up-active-pins { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; input-enable; From patchwork Sun Oct 16 17:22:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 615580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 263D9C43217 for ; Sun, 16 Oct 2022 17:22:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230009AbiJPRWz (ORCPT ); Sun, 16 Oct 2022 13:22:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229940AbiJPRWw (ORCPT ); Sun, 16 Oct 2022 13:22:52 -0400 Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 033D03387D for ; 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Sun, 16 Oct 2022 10:22:47 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v3 12/17] dt-bindings: pinctrl: qcom,sm8250: use common TLMM pin schema Date: Sun, 16 Oct 2022 13:22:07 -0400 Message-Id: <20221016172212.49105-13-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The common Qualcomm TLMM pin controller schema for pin mux and config already brings requirement of function for gpio pins and the definition of drive-strength. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- Changes since v2: 1. Drop drive-strength, reword commit msg. 2. Add tags. --- .../bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index d7d8e5d3b659..9447b79655e2 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -64,6 +64,7 @@ patternProperties: if: type: object then: + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state properties: pins: description: @@ -99,18 +100,12 @@ patternProperties: tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ] - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 - description: - Selects the drive strength for the specified pins, in mA. - bias-pull-down: true bias-pull-up: true bias-disable: true - + drive-strength: true output-high: true output-low: true @@ -118,16 +113,6 @@ patternProperties: required: - pins - allOf: - - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" - - if: - properties: - pins: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" - then: - required: - - function - additionalProperties: false allOf: From patchwork Sun Oct 16 17:22:09 2022 Content-Type: text/plain; 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Sun, 16 Oct 2022 10:22:51 -0700 (PDT) Received: from krzk-bin.hsd1.pa.comcast.net ([2601:42:0:3450:9b13:d679:7b5b:6921]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b003431446588fsm6051008qtt.5.2022.10.16.10.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 10:22:51 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v3 14/17] dt-bindings: pinctrl: qcom,sm8250: add input-enable Date: Sun, 16 Oct 2022 13:22:09 -0400 Message-Id: <20221016172212.49105-15-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The SM8250 pinctrl driver supports input-enable and DTS already use it (sm8250-sony-xperia-edo-pdx203). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index aa8315a4d9b1..e9619c4a39d8 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -114,6 +114,7 @@ $defs: bias-pull-up: true bias-disable: true drive-strength: true + input-enable: true output-high: true output-low: true From patchwork Sun Oct 16 17:22:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 615576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 987DFC4332F for ; Sun, 16 Oct 2022 17:23:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229691AbiJPRX6 (ORCPT ); Sun, 16 Oct 2022 13:23:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230196AbiJPRXe (ORCPT ); Sun, 16 Oct 2022 13:23:34 -0400 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CDB632BBC for ; Sun, 16 Oct 2022 10:22:55 -0700 (PDT) Received: by mail-qk1-x730.google.com with SMTP id a18so5484026qko.0 for ; Sun, 16 Oct 2022 10:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TrTtCkKyLzViHStMraixk/T1J2EP1l/wg8tY4lebl0M=; b=J3j7cuoR0tchPBNAugVwxQaHRPWigE+h5NfWgLBbK/OUKidD4Q+AevxaWJYOSurEyh 7vvL/btXsa0/oR4jw1J+ynS5L4Wu3NR7cmbdetI8q7YuLFhUNIhQLK6u5Yr6wsOiTYDG ophxB91z5aMvCHPIW8QDyS6WsoXX/Jox1cVkTxb4QXGRLXaRYX36DlUDKtDwWkKBytYR F3kQgEvUgMXRigFdBwevP47efuStmbrU7SnHLU2A4HkAIczeAtctVFijZQgq1VSc5/rK lcuf8+n98CCP4+IUGnUvrs37XCSID8ztrVUf2fZDt6G5SVbkRxmVc2O8TCLBTNiZhYcC 25+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TrTtCkKyLzViHStMraixk/T1J2EP1l/wg8tY4lebl0M=; b=2+2Ef+3maCX081rdJXU6+l/3mc1MEkzNiu/KD97ujf7S6IPBNVzg2XX3CBWhna6WBG OFc1dCRPXA30R79+fXccOtH6ilRXXJuEFPNrFqCPysUQwteRF3r31NXl7/W1YFJvhOWA FuvKcSKQTNG9XlK/Oux6jLm5i+C/iQVD2L97Zi81CuqzkKbvW5GdDMzYY9kBtnDtTzWA m7NvlgVNTiQQNCX0BtMSLH2pKrmpoaxtquW69PrETqySCY+wbHQXIDZC0KAJyvBYc7GU Y5GqVOKBU4dBoFV0dtRc3mpd5ot1uewADnR8Xa+kfDoUSTL9GjoeIafcrAv3rY6KSU8S 1ITQ== X-Gm-Message-State: ACrzQf0TOszGZCrzqKsEYG4gONx5siNHsj0fdZ/MstH6amQlBkczU7tq 3+rFdL98/iQrzLel9L3uhhlKng== X-Google-Smtp-Source: AMsMyM7LSKNC8nU/0lddMOEbriNQ+0Fgwf7hjL3FqwklV1MF3TMMpMRrdUpIG7QbVq4y8wrwS2a7hg== X-Received: by 2002:a05:620a:319d:b0:6ee:c966:318e with SMTP id bi29-20020a05620a319d00b006eec966318emr5149050qkb.347.1665940975074; Sun, 16 Oct 2022 10:22:55 -0700 (PDT) Received: from krzk-bin.hsd1.pa.comcast.net ([2601:42:0:3450:9b13:d679:7b5b:6921]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b003431446588fsm6051008qtt.5.2022.10.16.10.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 10:22:54 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v3 16/17] dt-bindings: pinctrl: qcom, sc7280: add bias-bus-hold and input-enable Date: Sun, 16 Oct 2022 13:22:11 -0400 Message-Id: <20221016172212.49105-17-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The SC7280 pinctrl driver supports bias-bus-hold and input-enable, and DTS already use it (sc7280-idp). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index e56861892050..2a6b5a719d18 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -117,13 +117,11 @@ $defs: Selects the drive strength for the specified pins, in mA. bias-pull-down: true - bias-pull-up: true - + bias-bus-hold: true bias-disable: true - + input-enable: true output-high: true - output-low: true required: From patchwork Sun Oct 16 17:22:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 615575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75AA7C4332F for ; Sun, 16 Oct 2022 17:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230207AbiJPRYB (ORCPT ); Sun, 16 Oct 2022 13:24:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230215AbiJPRXg (ORCPT ); Sun, 16 Oct 2022 13:23:36 -0400 Received: from mail-qv1-xf2e.google.com (mail-qv1-xf2e.google.com [IPv6:2607:f8b0:4864:20::f2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4346A399DE for ; Sun, 16 Oct 2022 10:22:58 -0700 (PDT) Received: by mail-qv1-xf2e.google.com with SMTP id mx8so6264186qvb.8 for ; Sun, 16 Oct 2022 10:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PWSKu7iskvYCRHNzfjjJULSfJxrJyK6VO5AdJbIhDuc=; b=YANfOS18yDjkBv8LX04Ri8LiKcAhZi4/VMCsQXt6LnTXavtuN1oiplbBpWzZxDPEwW zsG3o9TSArP3ryftHI+ZLRLQhr3xtdvVpJEaPKuXKwN6Fea/nSdMpvw1aI6ZaziJqJ1j k2dEzcabkumPpplCJMbceNjLqXNh8usZLM70ALhcp2/S+DCVpM9fJwPQRcBVyhQoU+oG 11GXlINrfvxFT6iQ86Fi5PLjS5p3RfE8e3+VP1Y4BpyppjKo36Iuls92m9oq7xaWJFeC enSrxW1zA5b5PCBCAUVzgExOQximSIGAO3+0F+kCIwgHB5PWOcqLfQtmmRgy0HhczpY2 FAYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PWSKu7iskvYCRHNzfjjJULSfJxrJyK6VO5AdJbIhDuc=; b=mG6AiOiaXo7QsW8+h5QWiegKdrFPrdEB4paU1wTV/ox3blPE6LJO4ND1woo4EEr1eP 50lmbgUtJMUJeahR/TVZeugwDYYQFEyZZmfcIg2Yo1ARAwohn3fd5Z/envGdNGGJA5/+ pmJbwq0yVKwMaLSjSKsyd/zFq4a3LqYdzcd52KVGA/Ed+PR6oY94GehVirYmxS4EeGqY /pGbgZ+DQpVl7m6dBVldPuwHAjWlue5sQdx24flWYGpvs+Q8G/6enq4+ITUwUgpCCQTm 7rwQUhQ0BTsEEBqf05kggRDuw6O1mBurHsozPglcfP7ssJBrNBAYNSRRxYuMKYoCjBgy MRgw== X-Gm-Message-State: ACrzQf3v/PFkgl0gP0ZIAwtjp+/UWXt46qGL5LbjaNIHJPeiZGbHapOM zxpqkaSFzjGVyg5oczYPic5jAw== X-Google-Smtp-Source: AMsMyM5ePjPHsGJMJ77e9k8RUAbAcov3iu/nAS9GlREFP00ztwuEwWDYGbjubKTEfpc1Vdsnk26B+A== X-Received: by 2002:a05:6214:21e5:b0:4b3:f3e0:5432 with SMTP id p5-20020a05621421e500b004b3f3e05432mr5607497qvj.19.1665940976508; Sun, 16 Oct 2022 10:22:56 -0700 (PDT) Received: from krzk-bin.hsd1.pa.comcast.net ([2601:42:0:3450:9b13:d679:7b5b:6921]) by smtp.gmail.com with ESMTPSA id r5-20020ac87945000000b003431446588fsm6051008qtt.5.2022.10.16.10.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 10:22:55 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v3 17/17] dt-bindings: pinctrl: qcom,sc7280: use common TLMM pin schema Date: Sun, 16 Oct 2022 13:22:12 -0400 Message-Id: <20221016172212.49105-18-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> References: <20221016172212.49105-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The common Qualcomm TLMM pin controller schema for pin mux and config already brings requirement of function for gpio pins and the definition of drive-strength. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- Changes since v2: 1. Drop drive-strength, reword commit msg. 2. Add tags. 3. This was previously part of: https://lore.kernel.org/linux-arm-msm/20221011172358.69043-1-krzysztof.kozlowski@linaro.org/T/#m277d25a5f3e9d10ca8221a7fba62ca468a67a60b --- .../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 2a6b5a719d18..d70ab12f227d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -62,6 +62,7 @@ $defs: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state properties: pins: @@ -110,16 +111,11 @@ $defs: uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 - description: - Selects the drive strength for the specified pins, in mA. - bias-pull-down: true bias-pull-up: true bias-bus-hold: true bias-disable: true + drive-strength: true input-enable: true output-high: true output-low: true @@ -127,16 +123,6 @@ $defs: required: - pins - allOf: - - $ref: /schemas/pinctrl/pincfg-node.yaml - - if: - properties: - pins: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" - then: - required: - - function - additionalProperties: false allOf: