From patchwork Mon Oct 17 15:25:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 616318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21428C43217 for ; Mon, 17 Oct 2022 15:26:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230135AbiJQP0r (ORCPT ); Mon, 17 Oct 2022 11:26:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbiJQP0q (ORCPT ); Mon, 17 Oct 2022 11:26:46 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D12F37191 for ; Mon, 17 Oct 2022 08:26:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1436CB81909 for ; Mon, 17 Oct 2022 15:26:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 463EEC4347C; Mon, 17 Oct 2022 15:26:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666020402; bh=FrpsB5GqMNt+LthRzZXRIsR6Armhvx2HZji/9oIAvao=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dHFqYCi8BobaRwxMjx1NMqAOIKmiJStpfULuJlP3ppz0WtangHYoQ+rfujSFhGEgv ETnRWdqAXhmcI8nqibxJmIUUIQkDVkRdtLR/dzgSa2WT1o87fffP03TH7GdIbJFm0C Bk46DfTu0yk+PKpx6xE6134M3ThX+w+gimyYiimylpzEtR4RHTtIpocUvhmdjSw2D5 4XYOaMwcjRuQTYwzt8krJQBl1dA8T/Qo+jrTdbypmqwz7yjJZf4yTjHg6Zn0AKBI1W 1JZkiWfSTCtlWWt4BVcm+Hm++JwxK81IJ2ZYp+NX1dX80SC2V0MwFcjdHADlwclTd5 ZTXdnPsYUgDOw== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v1 1/6] arm64/hwcap: Add support for FEAT_CSSC Date: Mon, 17 Oct 2022 16:25:15 +0100 Message-Id: <20221017152520.1039165-2-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221017152520.1039165-1-broonie@kernel.org> References: <20221017152520.1039165-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4235; i=broonie@kernel.org; h=from:subject; bh=FrpsB5GqMNt+LthRzZXRIsR6Armhvx2HZji/9oIAvao=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjTXPaysKcpY9Yd7nbeFkVFU26JqW8OOddEQtBnz2d URJBx1GJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY01z2gAKCRAk1otyXVSH0CN8B/ 9CeBuLo/TZznqESGhp3KRmd7+1yKp3MhKsuWGxz8yqbyotZXBgE+u6Ud5urUIiHiaPkH3P+P/RzZ1l LGYaV4DHUDqCw49qSFHWY8doml1LTfgo0raIpgRj7mp7ryYp84rUW5Eoig/V7vM05/P3oSCYK6SuXz IGbie94AZbp/3BSUhMefy8Ao8DwGWWcAWNP8/RiKlJqqG2zgTKcvvpS4S8gfay5nz1npApLFxVYOhL JVzi1BqnNcvQqIN+qiJmxJ+9RgZJk7tLf7/gaewN+wAfhCbPwRUAjM8OSouCsoD7blbrqn7zZdemnc EbxQ2iHOS26Y0b48DrO02QEQC+JHWN X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org FEAT_CSSC adds a number of new instructions usable to optimise common short sequences of instructions, add a hwcap indicating that the feature is available and can be used by userspace. Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- Documentation/arm64/elf_hwcaps.rst | 3 +++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 2 ++ arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/tools/sysreg | 7 ++++++- 6 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index bb34287c8e01..58197e9ccb6d 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -275,6 +275,9 @@ HWCAP2_EBF16 HWCAP2_SVE_EBF16 Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010. +HWCAP2_CSSC + Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 298b386d3ebe..a0e080df9a62 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -120,6 +120,7 @@ #define KERNEL_HWCAP_WFXT __khwcap2_feature(WFXT) #define KERNEL_HWCAP_EBF16 __khwcap2_feature(EBF16) #define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16) +#define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 9b245da6f507..a43dddd94b4a 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -93,5 +93,6 @@ #define HWCAP2_WFXT (1UL << 31) #define HWCAP2_EBF16 (1UL << 32) #define HWCAP2_SVE_EBF16 (1UL << 33) +#define HWCAP2_CSSC (1UL << 34) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6062454a9067..130cc9127dde 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -212,6 +212,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), @@ -2774,6 +2775,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 28d4f442b0bc..3160550c0cc9 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -116,6 +116,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_WFXT] = "wfxt", [KERNEL_HWCAP_EBF16] = "ebf16", [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", + [KERNEL_HWCAP_CSSC] = "cssc", }; #ifdef CONFIG_COMPAT diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 384757a7eda9..629d119151bf 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -484,7 +484,12 @@ EndEnum EndSysreg Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 -Res0 63:28 +Res0 63:56 +Enum 55:52 CSSC + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 51:28 Enum 27:24 PAC_frac 0b0000 NI 0b0001 IMP From patchwork Mon Oct 17 15:25:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 615920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1525C4332F for ; Mon, 17 Oct 2022 15:26:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230214AbiJQP0r (ORCPT ); Mon, 17 Oct 2022 11:26:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230135AbiJQP0q (ORCPT ); Mon, 17 Oct 2022 11:26:46 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5967558E4 for ; Mon, 17 Oct 2022 08:26:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6C16F611A8 for ; Mon, 17 Oct 2022 15:26:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 45DF1C433B5; Mon, 17 Oct 2022 15:26:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666020404; bh=uqFGlPxL2sBgmYdEcCsoFzK5krIGZNq9NokISwORtCE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bW3mubSOHhdnFma4Mxo/gffJqkSH7VoAVR5LHKPeNwb7jrHZzP4XNfa3RLcmzQx+R 8U1CXaBfv56bOLi005exc0ZOhCeSeJ7GrTtF/REV3nUbhmLnajCRrkFHK8Zos6wBDv 7Xy3xlz5JjB3oBI8nqC1Il9J2pOt2zBDFTCpyhOl3n0Tchdk7R3gDu3I7HBmhzMBXA oTFgpcWwP8YZHHx1MVLY+a8C1jh0XiyBnF+jkrm+Orz5d9g5YwT/u1skwrvauBZJXF eltUi5gosXtuAoalR/FVbXQ62hBpSLc3UTVvIJgXrBV2iMNiHvVYOaHCE9W0EFrDE+ BAtHWvk3R1vng== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v1 2/6] kselftest/arm64: Add FEAT_CSSC to the hwcap selftest Date: Mon, 17 Oct 2022 16:25:16 +0100 Message-Id: <20221017152520.1039165-3-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221017152520.1039165-1-broonie@kernel.org> References: <20221017152520.1039165-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1051; i=broonie@kernel.org; h=from:subject; bh=uqFGlPxL2sBgmYdEcCsoFzK5krIGZNq9NokISwORtCE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjTXPb/Rd5EqhfLM+KgtgF477vfIapDrMO1jSwnbi+ 2to9MxuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY01z2wAKCRAk1otyXVSH0NQ1B/ 0dtemDowy3YOPeLsxOu8LdltDTCDj/E/442EDhPFu3fdXOjEADS8g/LfzqrVcAVnjx+lQeTc/yYfsd fRNMvZp2PcAZNyPBRX4sn1X4ZLSzE0qh5FlZYYkAecsGZrMM3QaY8ziy+osqsfeyF4ytZKfWw6KJgN lU8lkNhZLaBZF+pPTaqhjvBFjqZc+EouP5Z9qODHDBL6pe0z1y+d5CtDUpXKKYrOV7IOWwyXji1rmq mwqnn68xQRnObIDuY3s4g740c9mhcNVFdSU1GoX5XACg+WddY/Ia5UKSa3xMdfn+i2ButHpX5UrQ94 FYenldPRX+O2OJjnSP8tT3MHsux6PC X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Add FEAT_CSSC to the set of features checked by the hwcap selftest. Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- tools/testing/selftests/arm64/abi/hwcap.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index 9f1a7b5c6193..c7a6b327a7d0 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -33,6 +33,12 @@ */ typedef void (*sigill_fn)(void); +static void cssc_sigill(void) +{ + /* CNT x0, x0 */ + asm volatile(".inst 0xdac01c00" : : : "x0"); +} + static void rng_sigill(void) { asm volatile("mrs x0, S3_3_C2_C4_0" : : : "x0"); @@ -118,6 +124,13 @@ static const struct hwcap_data { sigill_fn sigill_fn; bool sigill_reliable; } hwcaps[] = { + { + .name = "CSSC", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_CSSC, + .cpuinfo = "cssc", + .sigill_fn = cssc_sigill, + }, { .name = "RNG", .at_hwcap = AT_HWCAP2, From patchwork Mon Oct 17 15:25:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 615919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19E1BC4332F for ; Mon, 17 Oct 2022 15:26:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230251AbiJQP0t (ORCPT ); Mon, 17 Oct 2022 11:26:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbiJQP0s (ORCPT ); Mon, 17 Oct 2022 11:26:48 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C85F537191 for ; Mon, 17 Oct 2022 08:26:47 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 67CB961194 for ; Mon, 17 Oct 2022 15:26:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48988C43140; Mon, 17 Oct 2022 15:26:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666020406; bh=mmTGPzJIZgaNZHR9ynJ1gWHkWfgKy7hHPGj3lGvogQc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dhl5+9qtgWNp/Wj4FHfgT7TYb4zDStro0ZHOTKMlel8iSbcjHN4wpSjp3NlU0FM6N D0O/+UZJ/4zaC/9cMu+5fMncclMiejE3BmXrS6ir+PKirDe1No8QWEM1R3W5nndqq0 myMXnWA21WcscM9GPLJyLumEVypp9Q0D6PPmu+TzlIGjPinqOwq5rDmMIRubTKcNvi hQer5Ob5Km9p+wnngvqUo8DQ/GAzHXb7gAXm519SaBUVNiL0c/+A/LgNgwWGh26UvO mIAlGNWqv7qM3yTBAqLieyrrjIOekETXrFGrjHdQqqzxyFplH20F1Ea/xRGoqzlSVQ 4rwuu8x3ZXxuA== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v1 3/6] arm64/hwcap: Add support for FEAT_RPRFM Date: Mon, 17 Oct 2022 16:25:17 +0100 Message-Id: <20221017152520.1039165-4-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221017152520.1039165-1-broonie@kernel.org> References: <20221017152520.1039165-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4422; i=broonie@kernel.org; h=from:subject; bh=mmTGPzJIZgaNZHR9ynJ1gWHkWfgKy7hHPGj3lGvogQc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjTXPc1FV6hpuWaDY5jv0K3+xN/zh6Z/+mVfLp5aKM ve89OGOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY01z3AAKCRAk1otyXVSH0FXKB/ 9PSjosbjkUQV/WA7kcASGjS4jDtvVA5iYOZEWYLGStfiHRa3RwVDGfhBieoDSmnOUcqIf6ePXn68pM ZuwuoUboKfqWhFWFayrvDh7eFHPN/WVaRjYYp0h8HZpEjgkKN44aNo57lAX3wjVyHMMTUN7sO6U8D+ O8ta4wDtBC1NxsVfyDSG+P4+A+YujxsrwO+Ij0cfZr1tVWZsWrZ79EWadbiLSK63cBDmhlvWXtHU/6 xSqNFlIRFE2dXE/lTIV9G6Sn32PX45c5bS0iBkgT/L3oQD3TxvQmAOo2JoAZ0qZuFwjsdwlNQV5VpZ QtY2cotdeylZAZi9JFnvKtBdBcxDlC X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org FEAT_RPRFM adds a new range prefetch hint within the existing PRFM space for range prefetch hinting. Add a new hwcap to allow userspace to discover support for the new instruction. Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- Documentation/arm64/elf_hwcaps.rst | 3 +++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 2 ++ arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/tools/sysreg | 6 +++++- 6 files changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index 58197e9ccb6d..a82b2cdff680 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -278,6 +278,9 @@ HWCAP2_SVE_EBF16 HWCAP2_CSSC Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001. +HWCAP2_RPRFM + Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index a0e080df9a62..605ec55cee70 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -121,6 +121,7 @@ #define KERNEL_HWCAP_EBF16 __khwcap2_feature(EBF16) #define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16) #define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC) +#define KERNEL_HWCAP_RPRFM __khwcap2_feature(RPRFM) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index a43dddd94b4a..063cc6ea560f 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -94,5 +94,6 @@ #define HWCAP2_EBF16 (1UL << 32) #define HWCAP2_SVE_EBF16 (1UL << 33) #define HWCAP2_CSSC (1UL << 34) +#define HWCAP2_RPRFM (1UL << 35) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 130cc9127dde..01bd72ff9617 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -213,6 +213,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), @@ -2776,6 +2777,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_RPRFM_IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 3160550c0cc9..85108832d86e 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -117,6 +117,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_EBF16] = "ebf16", [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", [KERNEL_HWCAP_CSSC] = "cssc", + [KERNEL_HWCAP_RPRFM] = "rprfm", }; #ifdef CONFIG_COMPAT diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 629d119151bf..a2b2e4c1c3f2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -489,7 +489,11 @@ Enum 55:52 CSSC 0b0000 NI 0b0001 IMP EndEnum -Res0 51:28 +Enum 51:48 RPRFM + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 47:28 Enum 27:24 PAC_frac 0b0000 NI 0b0001 IMP From patchwork Mon Oct 17 15:25:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 615918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F09AC4332F for ; Mon, 17 Oct 2022 15:26:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbiJQP06 (ORCPT ); Mon, 17 Oct 2022 11:26:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbiJQP04 (ORCPT ); Mon, 17 Oct 2022 11:26:56 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 245135FF5E for ; Mon, 17 Oct 2022 08:26:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 84540CE14A0 for ; Mon, 17 Oct 2022 15:26:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49DD0C43470; Mon, 17 Oct 2022 15:26:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666020408; bh=/BpcIVyo9bzysBlJmI2fdJmkg66MdNxjcBf92h+/Hu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ip78g48reMynF7K+XwEnxkZbSeiyOFutcA25X/d4p38PqJ/LCWHrkmqGfI323EtX7 7guubtuVmUWWrglHHHICwtsvcX5jlw88dQJL7veEHndG2PQ/R4gkLru0gw3iG84wfM Kjr/ywz1/zrpN/Cny3vmsoEdc2d4nov6M/QrwddJDB/yLyixnxcz+3PT5lwdAgCbfr 6br4ZtLPTN9xWgVu2ViFukQshYWUc+JpAYuA9DCnPb/r8AEbGD5O8pybFdPaBCgYNR RdzvpHYYLKx9fUXhwnSckGY5rHKTx6RjBNfcymI7RliKbyN2Zs60np7QelBUaHWzQz G72klpHNer3CA== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v1 4/6] kselftest/arm64: Add FEAT_RPRFM to the hwcap test Date: Mon, 17 Oct 2022 16:25:18 +0100 Message-Id: <20221017152520.1039165-5-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221017152520.1039165-1-broonie@kernel.org> References: <20221017152520.1039165-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- tools/testing/selftests/arm64/abi/hwcap.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index c7a6b327a7d0..30f87dfd634e 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -138,6 +138,12 @@ static const struct hwcap_data { .cpuinfo = "rng", .sigill_fn = rng_sigill, }, + { + .name = "RPRFM", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_RPRFM, + .cpuinfo = "rprfm", + }, { .name = "SME", .at_hwcap = AT_HWCAP2, From patchwork Mon Oct 17 15:25:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 616317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA634C4332F for ; Mon, 17 Oct 2022 15:26:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230288AbiJQP0x (ORCPT ); Mon, 17 Oct 2022 11:26:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbiJQP0w (ORCPT ); Mon, 17 Oct 2022 11:26:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D52876048F for ; Mon, 17 Oct 2022 08:26:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6FFDB61196 for ; Mon, 17 Oct 2022 15:26:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D430C4347C; Mon, 17 Oct 2022 15:26:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666020410; bh=Tjv7ZeQYxBe/fAaH0j7yWZHO73Wm1EozZK4lzOQMXao=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M7l+mr5Vxap2C+2cM6q1u/6+IhyV+bvGsRsTHMIWKHEFJ3dSEH+UwWB++Xnh86s+n l5OhCF+M6GXi6U6KAuVwkbll6n2VkLLozIGuKyKnbxG3Xxn3APXZe+LkJRNsFUUIPe kWqK8/InehMh2cbfLnzpiNaTkCL6v14DU1zmaIPPSYer+xLxFaKiafsYqoO4/pn+gI 6KQm2SwM+jw980yGzUY5Gs33qE9obwHWsRlfIrKHR9Tb7cQRu1XYF73hGwIYbSsxj5 WnIWBhX3tPIZtF/gCGn+LO1dhVF5yniTSrXYiLxX5+scSShIO6h49r28Dwg6sfpceH VFYNXofNpVjaQ== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v1 5/6] arm64/hwcap: Add support for SVE 2.1 Date: Mon, 17 Oct 2022 16:25:19 +0100 Message-Id: <20221017152520.1039165-6-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221017152520.1039165-1-broonie@kernel.org> References: <20221017152520.1039165-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4260; i=broonie@kernel.org; h=from:subject; bh=Tjv7ZeQYxBe/fAaH0j7yWZHO73Wm1EozZK4lzOQMXao=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjTXPe6wTFaGbqYj0+wKgsXfSXDZxgPM+0RFN5kTNc HjU5tp2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY01z3gAKCRAk1otyXVSH0MoGB/ 9kA8MUESkZ+LHM/akdLbCuhlPLRzrYJ5bbiPsvg4s0p6uJ/ei1r2VsIrilldHcL+1vk/Dnokr3wB0h pdfjGyxwayxgUrTagM0ioafuHLfBbrwHbFGLELI8+kXabkORwY5cAhII+irduXJ79cRKWEw6FPKJJO QiBv9xwMHT+FYkvPENJOT/dKYdTmBK2KA5M6k81iCbNpfObyHKWoQjyyMR5zlG4e8OxIgSJfbSS77C 8MkfAbyogWfD08XOsheQ9c6xzjGr7mWLfPxtA3YTSwdP1brmJgWw3qX7j5isNRtRIFvPB0dPb0yRVy 3XPBqkjqn4C6kU+0GZYomtSFAu7lC4 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org FEAT_SVE2p1 introduces a number of new SVE instructions. Since there is no new architectural state added kernel support is simply a new hwcap which lets userspace know that the feature is supported. Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- Documentation/arm64/elf_hwcaps.rst | 3 +++ Documentation/arm64/sve.rst | 1 + arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 1 + arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/tools/sysreg | 1 + 7 files changed, 9 insertions(+) diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index a82b2cdff680..6fed84f935df 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -281,6 +281,9 @@ HWCAP2_CSSC HWCAP2_RPRFM Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001. +HWCAP2_SVE2P1 + Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index f338ee2df46d..c7a356bf4e8f 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -52,6 +52,7 @@ model features for SVE is included in Appendix A. HWCAP2_SVEBITPERM HWCAP2_SVESHA3 HWCAP2_SVESM4 + HWCAP2_SVE2P1 This list may be extended over time as the SVE architecture evolves. diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 605ec55cee70..06dd12c514e6 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -122,6 +122,7 @@ #define KERNEL_HWCAP_SVE_EBF16 __khwcap2_feature(SVE_EBF16) #define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC) #define KERNEL_HWCAP_RPRFM __khwcap2_feature(RPRFM) +#define KERNEL_HWCAP_SVE2P1 __khwcap2_feature(SVE2P1) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 063cc6ea560f..b713d30544f1 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -95,5 +95,6 @@ #define HWCAP2_SVE_EBF16 (1UL << 33) #define HWCAP2_CSSC (1UL << 34) #define HWCAP2_RPRFM (1UL << 35) +#define HWCAP2_SVE2P1 (1UL << 36) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 01bd72ff9617..bb1ef8cf7d04 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2750,6 +2750,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 85108832d86e..379695262b77 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -118,6 +118,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", [KERNEL_HWCAP_CSSC] = "cssc", [KERNEL_HWCAP_RPRFM] = "rprfm", + [KERNEL_HWCAP_SVE2P1] = "sve2p1", }; #ifdef CONFIG_COMPAT diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a2b2e4c1c3f2..b2782b8faa01 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -210,6 +210,7 @@ EndEnum Enum 3:0 SVEver 0b0000 IMP 0b0001 SVE2 + 0b0010 SVE2p1 EndEnum EndSysreg From patchwork Mon Oct 17 15:25:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 616316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A3E2C433FE for ; Mon, 17 Oct 2022 15:27:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230171AbiJQP07 (ORCPT ); Mon, 17 Oct 2022 11:26:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230294AbiJQP05 (ORCPT ); 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a=openpgp-sha256; l=1056; i=broonie@kernel.org; h=from:subject; bh=8V2GhJ4jVvqw3eI18z+SJ7d6N8Yl/q31zrS4myMV8vk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjTXPf6xaAYBc8ox07be/LQezNNjaZrSJSfXzeNFrs NI2S2W+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY01z3wAKCRAk1otyXVSH0DWoB/ kBvdAdNKDU24CwLcJlPAK2c/k2LbL/WWQ3tbnt0GWNWllgljr1Ds88CnR6EKIzo3hmBI8yaG6dbaAf Z4NEkr73TuOsM4pQe2WUW1ECBnYt0uBQzJY/Bnsm0qiSwY3ILC5MM8VwadT2ZeZx6Hj7UOwm2Wksxg 5F8t2RC/lvVmHTnQtoWOQZPaKUM823CCO/eeDfw1jT3AlbjUOTIhgbpVxozmuvK48s1mE787d9uFon k0LbUF+86RP14uppzmQpSv61Izyql+1vh1VD06eWWuMxVNrohnbYn15FzmPUR6mgE/jZYApnJWgK6F nTIR5TMgZUM7lQF5uGezDN7z1pzIr+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Add coverage for FEAT_SVE2p1. Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- tools/testing/selftests/arm64/abi/hwcap.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index 30f87dfd634e..9f255bc5f31c 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -62,6 +62,12 @@ static void sve2_sigill(void) asm volatile(".inst 0x4408A000" : : : "z0"); } +static void sve2p1_sigill(void) +{ + /* BFADD Z0.H, Z0.H, Z0.H */ + asm volatile(".inst 0x65000000" : : : "z0"); +} + static void sveaes_sigill(void) { /* AESD z0.b, z0.b, z0.b */ @@ -167,6 +173,13 @@ static const struct hwcap_data { .cpuinfo = "sve2", .sigill_fn = sve2_sigill, }, + { + .name = "SVE 2.1", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SVE2P1, + .cpuinfo = "sve2p1", + .sigill_fn = sve2p1_sigill, + }, { .name = "SVE AES", .at_hwcap = AT_HWCAP2,