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[23.90.200.126]) by smtp.googlemail.com with ESMTPSA id o5-20020a5d62c5000000b00228cbac7a25sm13998628wrv.64.2022.10.19.07.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 07:03:18 -0700 (PDT) From: Amjad Ouled-Ameur Date: Wed, 19 Oct 2022 16:01:03 +0200 Subject: [PATCH v3 1/2] spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v3-1-89de126fd163@baylibre.com> References: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> To: Mark Brown , Neil Armstrong , Krzysztof Kozlowski , Jerome Brunet , Martin Blumenstingl , Kevin Hilman , Rob Herring Cc: Da Xue , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, Neil Armstrong , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Amjad Ouled-Ameur X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666188196; l=2316; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=GT6aksNJPuRsH4QN0MrP1Ih2mkD83njM/kpnUgJ63XA=; b=ixcAkOk+adBdqxmgoxXlgXIVeDQnfg8RbvllBQ1SFspcrcB6O+ZI0+0K4uwlL2TcFbxZu3FcKeOF H7ly++vKDGHx+MCSN/UhYp09gxpJlU9dBFr2Z+0tt8yyV6TycVaP X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org SPI pins of the SPICC Controller in Meson-GX needs to be controlled by pin biais when idle. Therefore define three pinctrl names: - default: SPI pins are controlled by spi function. - idle-high: SCLK pin is pulled-up, but MOSI/MISO are still controlled by spi function. - idle-low: SCLK pin is pulled-down, but MOSI/MISO are still controlled by spi function. Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur --- .../bindings/spi/amlogic,meson-gx-spicc.yaml | 67 ++++++++++++++-------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 0c10f7678178..3e47fe7760a8 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -43,31 +43,48 @@ properties: minItems: 1 maxItems: 2 -if: - properties: - compatible: - contains: - enum: - - amlogic,meson-g12a-spicc - -then: - properties: - clocks: - minItems: 2 - - clock-names: - items: - - const: core - - const: pclk - -else: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: core +allOf: + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-g12a-spicc + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: pclk + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-gx-spicc + + then: + properties: + pinctrl-names: + minItems: 1 + items: + - const: default + - const: idle-high + - const: idle-low required: - compatible From patchwork Wed Oct 19 14:01:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 616696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ACCFC4332F for ; Wed, 19 Oct 2022 14:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229674AbiJSOVa (ORCPT ); Wed, 19 Oct 2022 10:21:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233072AbiJSOVM (ORCPT ); Wed, 19 Oct 2022 10:21:12 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 597AA61B24 for ; Wed, 19 Oct 2022 07:04:42 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id l16-20020a05600c4f1000b003c6c0d2a445so68089wmq.4 for ; Wed, 19 Oct 2022 07:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rZgwfLubP2W/1t0/FaJA376eh/Hnps387U4J2IjbH+Q=; b=u/rHqaVSXAtf44+agVTaE7rGMxdiAM9mO+71rH0zJ13C+ops+wfxsALrLi/qTcHLo2 Ev9tB/jp7LpRZrpDHe+l83Ad3mBJ2dKF4iB6mppCyruY6ljkZZUK6lCRy7Ing4rcvvER Zj/PzLkyiUQv6AgvOqL2zNCF9C8AoGVdGkNgWTSsWTe00yYumXkM2MceEQazBiKqE3jl KjZzDc8RXzZ4mZcyAV2kNLiHjgklBvH5uBSWHKUc3IosI9qDvLSiwftNVI92bOBCdG/0 8Urw1OrJdT28AjBHu9avIBYu4AkAcdhPIF4Udczs8XDQNxnna8i6A9pc6rQnj5gVoJ7J 5JTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rZgwfLubP2W/1t0/FaJA376eh/Hnps387U4J2IjbH+Q=; b=KYfF3cyUa+8B+iMf+BMpk2N1SrQwyjjpaeQH3PlnjYMkfXu4HZVG/gxsYCmwOn8KfG 3ukzoIY6nO2u7Ndyq5vTPo0BvW9YN2PN0FOdRCyhen3VmZ8Z94ejzTwgOGro4FRZZdcE Z61Gvi/H8jNWiAjgncJOa1zcJI7ufDxeqx8NNhnHmGPOdE/pxDOBD64XlBYbQ8vYMzGb ZAglOFwtFa8wfQMUORY584zywErNKuFAVRDG4k02ssiufXbr4SvhLZcgmoJoG9AsUpId Z7rBiZXm078vhhEGXn4yYn+WYLYHHduXQ+rstG+K7VTSFYip9/NVvpRnRoQPFoxuZGN0 slng== X-Gm-Message-State: ACrzQf16Ko1K5/xWkpsF9ILEeUfwSKd1O9yv7Vw/S8GPVOk9SzkzN8RF 5HB+iM7CXxQlv2zIvvlXqRiv5w== X-Google-Smtp-Source: AMsMyM4k2lIu5FtcD+oSZfD3YSgbmUclwlgXE3MZJDzEiIqjqYmYHAetaHQWtEDUAoC/OeKJuPuMjQ== X-Received: by 2002:a05:600c:4e47:b0:3c6:fc59:5eff with SMTP id e7-20020a05600c4e4700b003c6fc595effmr6918684wmq.18.1666188199567; Wed, 19 Oct 2022 07:03:19 -0700 (PDT) Received: from [127.0.1.1] (rtr.23.90.200.126.unyc.it. [23.90.200.126]) by smtp.googlemail.com with ESMTPSA id o5-20020a5d62c5000000b00228cbac7a25sm13998628wrv.64.2022.10.19.07.03.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 07:03:19 -0700 (PDT) From: Amjad Ouled-Ameur Date: Wed, 19 Oct 2022 16:01:04 +0200 Subject: [PATCH v3 2/2] spi: meson-spicc: Use pinctrl to drive CLK line when idle MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v3-2-89de126fd163@baylibre.com> References: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> To: Mark Brown , Neil Armstrong , Krzysztof Kozlowski , Jerome Brunet , Martin Blumenstingl , Kevin Hilman , Rob Herring Cc: Da Xue , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, Neil Armstrong , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Amjad Ouled-Ameur X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666188196; l=4316; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=dN6XmPpYO7Ty0vQSXH4eMp49Nq2iRF2CEqKZcOspWpI=; b=vviwObwJxuPYh/ZZNDCsfx7v9An1mgI8ZqaQQkOEPhpUcxtNrkB4V7dyqhh3eHnJUsX9mrUCOAxn oyRtrThBCRUCQgrksHjC40en6/dPJsjPNI8IfERp46vdxVdELtM6 X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++++++++ drivers/spi/spi-meson-spicc.c | 39 +++++++++++++++++++++++++++++- 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index c3ac531c4f84..04e9d0f1bde0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -429,6 +429,20 @@ mux { }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0"; diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index bad201510a99..ffea38e2339c 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -21,6 +21,7 @@ #include #include #include +#include /* * The Meson SPICC controller could support DMA based transfers, but is not @@ -167,6 +168,9 @@ struct meson_spicc_device { unsigned long tx_remain; unsigned long rx_remain; unsigned long xfer_remain; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_idle_high; + struct pinctrl_state *pins_idle_low; }; #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div) @@ -175,8 +179,22 @@ static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) { u32 conf; - if (!spicc->data->has_oen) + if (!spicc->data->has_oen) { + /* Try to get pinctrl states for idle high/low */ + spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl, + "idle-high"); + if (IS_ERR(spicc->pins_idle_high)) { + dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n"); + spicc->pins_idle_high = NULL; + } + spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl, + "idle-low"); + if (IS_ERR(spicc->pins_idle_low)) { + dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n"); + spicc->pins_idle_low = NULL; + } return; + } conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; @@ -441,6 +459,16 @@ static int meson_spicc_prepare_message(struct spi_master *master, else conf &= ~SPICC_POL; + if (!spicc->data->has_oen) { + if (spi->mode & SPI_CPOL) { + if (spicc->pins_idle_high) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high); + } else { + if (spicc->pins_idle_low) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low); + } + } + if (spi->mode & SPI_CPHA) conf |= SPICC_PHA; else @@ -487,6 +515,9 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master) /* Set default configuration, keeping datarate field */ writel_relaxed(conf, spicc->base + SPICC_CONREG); + if (!spicc->data->has_oen) + pinctrl_select_default_state(&spicc->pdev->dev); + return 0; } @@ -798,6 +829,12 @@ static int meson_spicc_probe(struct platform_device *pdev) goto out_core_clk; } + spicc->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(spicc->pinctrl)) { + ret = PTR_ERR(spicc->pinctrl); + goto out_clk; + } + device_reset_optional(&pdev->dev); master->num_chipselect = 4;