From patchwork Thu Oct 20 15:16:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 616912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 743CAC4332F for ; Thu, 20 Oct 2022 15:16:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229849AbiJTPQU (ORCPT ); Thu, 20 Oct 2022 11:16:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbiJTPQT (ORCPT ); Thu, 20 Oct 2022 11:16:19 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10C51147054 for ; Thu, 20 Oct 2022 08:16:18 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id bu30so35080103wrb.8 for ; Thu, 20 Oct 2022 08:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=kJeYraV+chjx4w/MZhjgD8d2xGVua4ZGuZHWlb758KSGO9ChppIikvGNbRU5JuDcMT 5q4sTiPl4qmad1XKgrkucu5HEcOejc4GFcu5wgdG9SqJ+q8uPkF7hPhQAOrjX7S6SMQq tMzzBzDxpSbVvqT3yGk4CY5K6Q4lfhQx/5JB6gQsuCpzeiXERrCjLmyreJDqzO599NZw 9DzW4wTv5O3ttQZunV8Dh3TUQta4hnsv+4LwJj96Hy9dULjjR+puxvkxBClUPcltAQhV m0sjJHT4Vqaf0GUfjhy8hFaxm4Qh3/YDjo1HIlFdeEq1YLeGuCi2ZiwFsnaGDyPsHham pjYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=FvlhUZpHsiKwIQzsibvfvYz/i+Tvwh1rDhAV6xnsQIlhy9/7uhi2xwpj0BUXrVUNI5 Zwdn3E4RQ9mOkXvdo6Yl0Xtgas+ZbPxr3sIQlZruTVbMJGXq9RrskXHgS0VYh+amqehq IBWmRmhIC72Vytji9N0e7aEoqXE+hom4DD1vXBkJgTwanfLboGl24tNEGAsdoGXCyjEu OuZrfhR0yTVdZyJoXIKab5S8cYkFtnVSxnQwAiqLFydNTLn+dW5Doat2e+uamu2OmUcC uIlNUfvTnBQprotHGwyiLZ0u7V3bgsVd/PkyNzpvwELugxn0xy8vyb8/Uu4ihjGh01zz 4Trg== X-Gm-Message-State: ACrzQf3yk74DDacSCRyz9Si2wjlw3gzSMhWyqhQyTy8PLzY5pyVpaWsL 3gCFKSypXgylnofImeii4m/CDg== X-Google-Smtp-Source: AMsMyM5qyB4bwOpUIYl9vi1zgJNgu2I+7YGLZ5w0AMEMM42WxAUOza4QELi8lmWd2SJCPtFdIwIfmg== X-Received: by 2002:a5d:494a:0:b0:235:4b14:4c7e with SMTP id r10-20020a5d494a000000b002354b144c7emr3453423wrs.174.1666278976603; Thu, 20 Oct 2022 08:16:16 -0700 (PDT) Received: from rainbowdash.guest.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id bg6-20020a05600c3c8600b003c6f3e5ba42sm41362wmb.46.2022.10.20.08.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 08:16:15 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 02/10] pwm: dwc: allow driver to be built with COMPILE_TEST Date: Thu, 20 Oct 2022 16:16:02 +0100 Message-Id: <20221020151610.59443-3-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow dwc driver to be built with COMPILE_TEST should allow better coverage when build testing. Signed-off-by: Ben Dooks --- v4: - moved to earlier in the series v3: - add HAS_IOMEM depdency for compile testing --- drivers/pwm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..3f3c53af4a56 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,7 +176,8 @@ config PWM_CROS_EC config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI + depends on PCI || COMPILE_TEST + depends on HAS_IOMEM help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. 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Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index c706ef9a7ba1..61f11e0a9319 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -196,13 +196,29 @@ static const struct pwm_ops dwc_pwm_ops = { .owner = THIS_MODULE, }; +static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev = dev; + dwc->chip.ops = &dwc_pwm_ops; + dwc->chip.npwm = DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} + static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) { struct device *dev = &pci->dev; struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + dwc = dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; @@ -226,12 +242,6 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - pci_set_drvdata(pci, dwc); - - dwc->chip.dev = dev; - dwc->chip.ops = &dwc_pwm_ops; - dwc->chip.npwm = DWC_TIMERS_TOTAL; - ret = pwmchip_add(&dwc->chip); if (ret) return ret; From patchwork Thu Oct 20 15:16:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 616910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91616C4332F for ; Thu, 20 Oct 2022 15:16:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229756AbiJTPQa (ORCPT ); Thu, 20 Oct 2022 11:16:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230098AbiJTPQ1 (ORCPT ); Thu, 20 Oct 2022 11:16:27 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9CCE14DF19 for ; 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Thu, 20 Oct 2022 08:16:21 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 07/10] pwm: dwc: make timer clock configurable Date: Thu, 20 Oct 2022 16:16:07 +0100 Message-Id: <20221020151610.59443-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks --- v6: - removed DWC_CLK_PERIOD_NS as it is now not needed v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc-pci.c | 1 + drivers/pwm/pwm-dwc.c | 10 ++++++---- drivers/pwm/pwm-dwc.h | 3 ++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c index 2213d0e7f3c8..949423e368f9 100644 --- a/drivers/pwm/pwm-dwc-pci.c +++ b/drivers/pwm/pwm-dwc-pci.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "pwm-dwc.h" diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 90a8ae1252a1..1251620ab771 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -47,13 +48,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -128,12 +129,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty += 1; - duty *= DWC_CLK_PERIOD_NS; + duty *= dwc->clk_ns; state->duty_cycle = duty; period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period += 1; - period *= DWC_CLK_PERIOD_NS; + period *= dwc->clk_ns; period += duty; state->period = period; @@ -156,6 +157,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; + dwc->clk_ns = 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 68f98eb76152..dc451cb2eff5 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -22,7 +22,6 @@ #define DWC_TIMERS_COMP_VERSION 0xac #define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 /* Timer Control Register */ #define DWC_TIM_CTRL_EN BIT(0) @@ -41,6 +40,8 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; 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Thu, 20 Oct 2022 08:16:23 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 09/10] pwm: dwc: add PWM bit unset in get_state call Date: Thu, 20 Oct 2022 16:16:09 +0100 Message-Id: <20221020151610.59443-10-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 1251620ab771..5ef0fe7ea3e9 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -121,23 +121,30 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, { struct dwc_pwm *dwc = to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; pm_runtime_get_sync(chip->dev); - state->enabled = !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty += 1; - duty *= dwc->clk_ns; - state->duty_cycle = duty; + state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); - period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period += 1; - period *= dwc->clk_ns; - period += duty; - state->period = period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty = (ld + 1) * dwc->clk_ns; + period = (ld2 + 1) * dwc->clk_ns; + period += duty; + } else { + duty = (ld + 1) * dwc->clk_ns; + period = duty * 2; + } + state->period = period; + state->duty_cycle = duty; state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev); From patchwork Thu Oct 20 15:16:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 616908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8489DC4332F for ; Thu, 20 Oct 2022 15:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230226AbiJTPQm (ORCPT ); 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Thu, 20 Oct 2022 08:16:24 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 10/10] pwm: dwc: use clock rate in hz to avoid rounding issues Date: Thu, 20 Oct 2022 16:16:10 +0100 Message-Id: <20221020151610.59443-11-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As noted, the clock-rate when not a nice multiple of ns is probably going to end up with inacurate caculations, as well as on a non pci system the rate may change (although we've not put a clock rate change notifier in this code yet) so we also add some quick checks of the rate when we do any calculations with it. Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc-of.c | 2 +- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c index c5b4351cc7b0..5f7f066859d4 100644 --- a/drivers/pwm/pwm-dwc-of.c +++ b/drivers/pwm/pwm-dwc-of.c @@ -50,7 +50,7 @@ static int dwc_pwm_plat_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(dwc->clk), "failed to get timer clock\n"); - dwc->clk_ns = NSEC_PER_SEC / clk_get_rate(dwc->clk); + dwc->clk_rate = clk_get_rate(dwc->clk); return devm_pwmchip_add(dev, &dwc->chip); } diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 5ef0fe7ea3e9..f48a6245a3b5 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -43,18 +43,22 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, u32 high; u32 low; + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); + /* * Calculate width of low and high period in terms of input clock * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp = state->duty_cycle * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; - tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp = (state->period - state->duty_cycle) * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -120,6 +124,7 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc = to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; @@ -129,22 +134,28 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); + + clk_rate = dwc->clk_rate; state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); /* If we're not in PWM, technically the output is a 50-50 * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty = (ld + 1) * dwc->clk_ns; - period = (ld2 + 1) * dwc->clk_ns; + duty = ld + 1; + period = ld2 + 1; period += duty; } else { - duty = (ld + 1) * dwc->clk_ns; + duty = ld + 1; period = duty * 2; } - state->period = period; - state->duty_cycle = duty; + duty *= NSEC_PER_SEC; + period *= NSEC_PER_SEC; + state->period = DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev); @@ -164,7 +175,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; - dwc->clk_ns = 10; + dwc->clk_rate = NSEC_PER_SEC / 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index dc451cb2eff5..19bdc2224690 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -41,7 +41,7 @@ struct dwc_pwm { struct pwm_chip chip; void __iomem *base; struct clk *clk; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))