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This controller supports the USB 3.1 specification. Signed-off-by: Wayne Chang --- .../bindings/usb/nvidia,tegra-xhci.yaml | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml new file mode 100644 index 000000000000..d261a419a04f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/nvidia,tegra-xhci.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra XUSB host controller + +description: + The Tegra XHCI controller supports both USB 2.0 HighSpeed/FullSpeed and + USB 3.1 SuperSpeed protocols. + +maintainers: + - Wayne Chang + +properties: + compatible: + items: + - enum: + - nvidia,tegra194-xusb # For Tegra194 + - nvidia,tegra234-xusb # For Tegra234 + + reg: + minItems: 2 + items: + - description: XUSB host controller registers + - description: XUSB host PCI Config registers + - description: XUSB host bar2 registers + + reg-names: + minItems: 2 + items: + - const: hcd + - const: fpci + - const: bar2 + + interrupts: + items: + - description: Must contain the XUSB host interrupt. + - description: Must contain the XUSB mbox interrupt. + + clocks: + items: + - description: Clock to enable core XUSB host clock. + - description: Clock to enable XUSB falcon clock. + - description: Clock to enable XUSB super speed clock. + - description: Clock to enable XUSB super speed dev clock. + - description: Clock to enable XUSB high speed dev clock. + - description: Clock to enable XUSB full speed dev clock. + - description: Clock to enable XUSB UTMI PLL clock. + - description: Clock to enable core XUSB dev clock. + - description: Clock to enable XUSB PLLE clock. + + clock-names: + items: + - const: xusb_host + - const: xusb_falcon_src + - const: xusb_ss + - const: xusb_ss_src + - const: xusb_hs_src + - const: xusb_fs_src + - const: pll_u_480m + - const: clk_m + - const: pll_e + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + power-domains: + items: + - description: XUSBC(host) power-domain + - description: XUSBA(superspeed) power-domain + + power-domain-names: + items: + - const: xusb_host + - const: xusb_ss + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the XUSB pad controller that is used to configure the USB pads + used by the XUDC controller. + + phys: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + + phy-names: + minItems: 1 + maxItems: 8 + items: + anyOf: + - const: usb2-0 + - const: usb2-1 + - const: usb2-2 + - const: usb2-3 + - const: usb3-0 + - const: usb3-1 + - const: usb3-2 + - const: usb3-3 + + dma-coherent: + type: boolean + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - power-domains + - power-domain-names + - nvidia,xusb-padctl + - phys + - phy-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-xusb + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + clocks: + minItems: 9 + clock-names: + minItems: 9 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-xusb + then: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + clocks: + minItems: 9 + clock-names: + minItems: 9 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + + phys = <&pad_lanes_usb2_0>; + phy-names = "usb2-0"; + + }; From patchwork Mon Oct 24 07:41:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 618096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1965CFA3743 for ; Mon, 24 Oct 2022 07:42:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230039AbiJXHmg (ORCPT ); Mon, 24 Oct 2022 03:42:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229959AbiJXHmU (ORCPT ); Mon, 24 Oct 2022 03:42:20 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2042.outbound.protection.outlook.com [40.107.243.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AB886112B; 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Replace ccgx to well-known regex "cypress". Signed-off-by: Wayne Chang --- drivers/usb/typec/ucsi/ucsi_ccg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 139707a2f3d6..5d3099e6eb77 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -1358,7 +1358,7 @@ static int ucsi_ccg_probe(struct i2c_client *client, INIT_WORK(&uc->pm_work, ccg_pm_workaround_work); /* Only fail FW flashing when FW build information is not provided */ - status = device_property_read_u16(dev, "ccgx,firmware-build", + status = device_property_read_u16(dev, "cypress,firmware-build", &uc->fw_build); if (status) dev_err(uc->dev, "failed to get FW build information\n"); From patchwork Mon Oct 24 07:41:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 618095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E27ECC38A2D for ; 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Mon, 24 Oct 2022 00:41:59 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 07/11] i2c: nvidia-gpu: Replace ccgx to well-known regex Date: Mon, 24 Oct 2022 15:41:24 +0800 Message-ID: <20221024074128.1113554-8-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT087:EE_|CH2PR12MB4199:EE_ X-MS-Office365-Filtering-Correlation-Id: 821a76a5-297f-4167-afd3-08dab593422d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: awsvsxhX3GX0baoJMZfFpPwrQe0P3DTdUEESirzhPYV8PnxkUoSIVEWT6a+3eEYXQ7YU6KpWbOAcFI/Yog0mLJ2QmulK6GFjjXRdO6/YWkABf57DlnPC4rv7h0p0dxQF20y6tU4Clvyd3BPCQXRd5Tuyei+jY6iXyZuhoswwzpkvHaYQUdfrLrT/m3OnKA05/nwU5njEErPzkRfRIJhLvZBABUutkbbcYvLzbDt5H19NhXXUp14qkuemgWo2z9gzffjekMkBTsqEGUI2jovG480Mp5cHBOxnSHolyyFA+8QOZnRv1QcOjjnQ+pAJJhsg53gbqvGQc0K0lQnlHAeRygwHTP0ydNJWPxrbHqbSm10Gj0aq6TWDy3XpB1dj/nO2qTHiDswz/dN0hFreyGojRZQ9P1ttLuFsN6YAEgraEwKHZ92RmEisI6lUqb6UM9MxDEXoyfRj9TG3SLO+tgRSkXugjKlGDasPssuuFRs04oiHLpiKCLDjWbYJkTTUy/hKi/HCEqsj/33/+nnBod5UDwR0C59rcBEXPUNCNlWeWgW5olBoqpy7rN+B4xpI8hk1Ea0GtfFQZCZ8mKNaWoir3RRLzO2SIukWzQ+OJiMq3kDAD52VcCImVwwXrXHItwKq7xTzfqAFw7Os6riEKRXIs8tRMmSEFEKqSRNhmwTaGNKLyfyJ9qNYTt+LItHm15EpUTXzfMRLUA8usR1mxdI+lxQ/fnL3IaT10nLtJzMwaObOAeqJ+b9Kqe54VFyZ8PVfALpKhPPb0yUkhoslvfn8qYoQAbChKee+n9odnx1fTok= X-Forefront-Antispam-Report: CIP:216.228.118.233; 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Replace ccgx to well-known regex "cypress". Signed-off-by: Wayne Chang --- drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 12e330cd7635..0934f8ad7f49 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -260,7 +260,7 @@ MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); static const struct property_entry ccgx_props[] = { /* Use FW built for NVIDIA (nv) only */ - PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), + PROPERTY_ENTRY_U16("cypress,firmware-build", ('n' << 8) | 'v'), { } }; From patchwork Mon Oct 24 07:41:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 618093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60ECCFA374C for ; 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Mon, 24 Oct 2022 00:42:03 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 08/11] phy: tegra: xusb: Disable trk clk when not using Date: Mon, 24 Oct 2022 15:41:25 +0800 Message-ID: <20221024074128.1113554-9-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT072:EE_|BY5PR12MB4131:EE_ X-MS-Office365-Filtering-Correlation-Id: 855dc428-fa93-43d2-dc96-08dab5934897 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ASfFp+QFYC7IKUX6CfH+Ge6bN7obcRYYg11RmgdFsOTJrtV2HjTBELvV9hKK5z1yMltFFFZkgZG9SpBAcAEIUNQlgRs/jcG3flo3Nz7ZXmQ0vYF/2ifz9WeEmv+7ubA+MXKcyDqmI1RAi7uBgxJGlBZ2Oq7lxrcb8sNgOwu9fGWorN4Gl/qKEdjhA+JMJF10zstEc13ZaoEzZAbQ22KQicOBIOUIpKirbMV1HGXWaT0Eoyzl5g+/wMKy7ps5I1x+4J1767P7YE17tUEj1Li9rfz0IKvvAADTUZoQj38Pv069+dRHnVl80X3BDOC4D0ILSZiyzBmIGIQTo7Hu7hurbQX54rNO76W8wSYDLpyWMFGWAXVvIoF0qc51ZLJg8nhTF4svUub54TAroCz7LuxYvJR3agL0DsKXKtxViVaDDoyfFIt+R4xShZ16kH7zewW/Mtuy+DLo+yzhnQQ4Rgh6Edy8j2WnKm3ipkKW9T3LZRPiC03AphRXh/Q6RlvG0R19hhRZfNb5V9T0QBK/UCdOf2isRnRxGe7n7lBmv8Ln0iB0U2TUUH3EReqbwmhUdxevk4aAXg3Nl9GSJ0do3XbBv4EE3wT6MrNn5t7GSgZzE+IMEBlGa7UbRu6p/X552I4aaMtdjs7kyplvsTt1OeOC1cEsTqbzrTdGIDxtUCBRx03i3X391gKbIqdjmVO3OMd+x4zjNtv2G0tTx/FdwaNwnDEzX3JoWxcLXIlLZvxHqWPlpb+chLMMxFno1I74j3vnkwRdEBDWz4rFwqH4UlSZmy/kURFvgyZ2GxY3Tq2Twxs= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(40480700001)(2906002)(8936002)(82740400003)(47076005)(426003)(5660300002)(6636002)(7636003)(356005)(921005)(2616005)(7416002)(41300700001)(110136005)(54906003)(26005)(316002)(6666004)(36756003)(186003)(1076003)(36860700001)(86362001)(336012)(83380400001)(7696005)(478600001)(70206006)(70586007)(8676002)(4326008)(40460700003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:20.7203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 855dc428-fa93-43d2-dc96-08dab5934897 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4131 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The change fixes an issue that the pad tracking is a one-time calibration for Tegra186 and Tegra194. We should disable the clk when it is done. The 100us delay is for HW recording the calibration value. Signed-off-by: Wayne Chang --- drivers/phy/tegra/xusb-tegra186.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 0996ede63387..f121b4ffbbfd 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -609,6 +609,10 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + udelay(100); + + clk_disable_unprepare(priv->usb2_trk_clk); + mutex_unlock(&padctl->lock); } @@ -633,8 +637,6 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - clk_disable_unprepare(priv->usb2_trk_clk); - mutex_unlock(&padctl->lock); } From patchwork Mon Oct 24 07:41:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 618094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5189AFA3748 for ; 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Mon, 24 Oct 2022 00:42:06 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 09/11] phy: tegra: xusb: Add Tegra234 support Date: Mon, 24 Oct 2022 15:41:26 +0800 Message-ID: <20221024074128.1113554-10-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT015:EE_|CH2PR12MB5020:EE_ X-MS-Office365-Filtering-Correlation-Id: bf6e61b6-4eb1-48e9-2657-08dab5934920 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NVLixrIzIppHSasxMK9iD8GLgNcrzZP7v2V/aYF9yNuYzQK5YZQsg68z7oX2XDo0nRAcPTSBlK2VOTNtAs5bXcsSVE/cQmjKo2HZM+Cr3sAkuZnRn/njipBIg+61gDSE4FixFviTnR8F4r5B1uuw1SzqRnGlj39NDNQlaV5loxTLG/SclZkPAEJgBhbeSgz7JWezvrao0MqNaTY/6/3KxkDviegF/B9X9j8hqt42mxyGpzGNPTDhkyO0cAdeROK8U4gDpVCk/Ym1SVWjJTBCFCrIUAe7hZ6yvnPgAyV5nTRBXtcqtArEFoHF0v+pOf6Wt/+WnBhC2T5xpOjaE2EoHozzcGfSjrambDVAYPWI9N8Bp3XWdnDJ03iHzH3kWgzYpRtBkoaPcLXHPzl4rMHAKSkbQOX5kylunWCh4uIDXE+EyXfUIhwRDCiyiHfnuKs39HBTTAyaWfSqBuUR/CI4ekU6kwPgEtzGOHidUKPqAlutGDGKsJu4XeYcZKZqUk6GW+qkFkbTNbK8OSUEt1972VjLtHd7JkGUYBWoGaUa1z7VFg9k6FPTvArI92zEMIpqMICmnHYB1Q7XIqQYRUXfBuf3m8dkViLKNMQK56cGyW3cslZXmVBGQRpE54GpFtzU2yzCTBN9iExMWOwzSuF5KAC1VMslZH6/1ZIRiu0+ZiiQzF0FpvyZ6YsEnVf5Nt51a3fwdsdtyNFpP8XhOLHtRTOkBlst2qerEMuB2u2C+75ByF7kkoAIWB1ldOyB4m+npjtneH1rQwuFzEcqxNXUlxZzZOtN8pxeBNQflO++5EA= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(47076005)(426003)(186003)(1076003)(336012)(40480700001)(6666004)(2906002)(86362001)(356005)(921005)(7636003)(36756003)(40460700003)(82740400003)(82310400005)(83380400001)(7696005)(26005)(4326008)(36860700001)(2616005)(316002)(8676002)(478600001)(6636002)(41300700001)(110136005)(70586007)(5660300002)(7416002)(8936002)(54906003)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:21.6604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf6e61b6-4eb1-48e9-2657-08dab5934920 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5020 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sing-Han Chen Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 65 +++++++++++++++++++++++++++++-- drivers/phy/tegra/xusb.c | 6 +++ drivers/phy/tegra/xusb.h | 23 +++++++++++ 4 files changed, 92 insertions(+), 3 deletions(-) diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index 89b84067cb4c..eeeea72de117 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -7,4 +7,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index f121b4ffbbfd..cc02cea65a21 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -89,6 +89,11 @@ #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19) #define USB2_PD_TRK BIT(26) +#define USB2_TRK_COMPLETED BIT(31) + +#define XUSB_PADCTL_USB2_BIAS_PAD_CTL2 0x28c +#define USB2_TRK_HW_MODE BIT(0) +#define CYA_TRK_CODE_UPDATE_ON_IDLE BIT(31) #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) #define HSIC_PD_TX_DATA0 BIT(1) @@ -609,9 +614,32 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - udelay(100); + if (padctl->soc->poll_trk_completed) { + err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, + USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100); + if (err) { + /* The failure with polling on trk complete will not + * cause the failure of powering on the bias pad. + */ + dev_warn(dev, "failed to poll USB2 trk completed: %d\n", + err); + } - clk_disable_unprepare(priv->usb2_trk_clk); + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value |= USB2_TRK_COMPLETED; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + } else { + udelay(100); + } + + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value |= USB2_TRK_HW_MODE; + value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + } else { + clk_disable_unprepare(priv->usb2_trk_clk); + } mutex_unlock(&padctl->lock); } @@ -637,6 +665,13 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value &= ~USB2_TRK_HW_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + clk_disable_unprepare(priv->usb2_trk_clk); + } + mutex_unlock(&padctl->lock); } @@ -1560,7 +1595,8 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); #endif -#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) +#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ + IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) static const char * const tegra194_xusb_padctl_supply_names[] = { "avdd-usb", "vclamp-usb", @@ -1616,8 +1652,31 @@ const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = { .supply_names = tegra194_xusb_padctl_supply_names, .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), .supports_gen2 = true, + .poll_trk_completed = true, }; EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc); + +const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = { + .num_pads = ARRAY_SIZE(tegra194_pads), + .pads = tegra194_pads, + .ports = { + .usb2 = { + .ops = &tegra186_usb2_port_ops, + .count = 4, + }, + .usb3 = { + .ops = &tegra186_usb3_port_ops, + .count = 4, + }, + }, + .ops = &tegra186_xusb_padctl_ops, + .supply_names = tegra194_xusb_padctl_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), + .supports_gen2 = true, + .poll_trk_completed = true, + .trk_hw_mode = true, +}; +EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); #endif MODULE_AUTHOR("JC Kuo "); diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 95091876c422..23d179b1a5b5 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -71,6 +71,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra194-xusb-padctl", .data = &tegra194_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) + { + .compatible = "nvidia,tegra234-xusb-padctl", + .data = &tegra234_xusb_padctl_soc, + }, #endif { } }; diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 8cfbbdbd6e0c..ec0b5b023ad1 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -8,6 +8,7 @@ #define __PHY_TEGRA_XUSB_H #include +#include #include #include @@ -433,6 +434,8 @@ struct tegra_xusb_padctl_soc { unsigned int num_supplies; bool supports_gen2; bool need_fake_usb3_port; + bool poll_trk_completed; + bool trk_hw_mode; }; struct tegra_xusb_padctl { @@ -475,6 +478,23 @@ static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, return value; } +static inline u32 padctl_readl_poll(struct tegra_xusb_padctl *padctl, + unsigned long offset, u32 val, u32 mask, int us) +{ + u32 regval; + int err; + + err = readl_poll_timeout_atomic(padctl->regs + offset, regval, + (regval & mask) == val, 1, us); + dev_dbg(padctl->dev, "%08lx poll > %08x\n", offset, regval); + if (err) { + dev_err(padctl->dev, "%08lx poll timeout > %08x\n", offset, + regval); + } + + return err; +} + struct tegra_xusb_lane *tegra_xusb_find_lane(struct tegra_xusb_padctl *padctl, const char *name, unsigned int index); @@ -491,5 +511,8 @@ extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc; #if defined(CONFIG_ARCH_TEGRA_194_SOC) extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) +extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */