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[209.51.188.17]) by mx.google.com with ESMTPS id ez3-20020a05622a4c8300b003a4fe528be9si1174998qtb.296.2022.10.27.13.48.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Oct 2022 13:48:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RdoIvhfZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oo9nH-0003a1-4V; Thu, 27 Oct 2022 16:48:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oo9n1-0003Hc-PR for qemu-devel@nongnu.org; Thu, 27 Oct 2022 16:47:55 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oo9mn-0007R6-Vy for qemu-devel@nongnu.org; Thu, 27 Oct 2022 16:47:47 -0400 Received: by mail-wm1-x332.google.com with SMTP id l14-20020a05600c1d0e00b003c6ecc94285so4505401wms.1 for ; Thu, 27 Oct 2022 13:47:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=74DDUYUGfeWypaCG02ItfjGfd6cxkR71vlmSf2VE7U4=; b=RdoIvhfZgRp3UAcV+aox7MMhJbRRupi7JKOxd7ft8hIQ6BtZ09acHmEQros/q8Xofm orpACplii7yxdXSqO5mZWa/9yR/JtyuRKMDYl/kkfzGcPi+JU2BlNmejT9lGt26xPi6k WDyEN8ZY2MxkyoTq2IXp5glTbyRCJ6ikVu1gpquyl1PgzP2COKbPQyE3HAVbwi9WPFkJ LPSfFtS8vtM7+ItyaYB8fpGKsNqXzYDSjEXZBApzypWq+kl+Al9Z7dL2Fgd6DO2fhn3t dBXVPsS4wll04aE+tMmZPZEPmeudYM4fkE6ZUlTjDyHMGQjgwwdYgupeINE9oCatuDOo sJHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=74DDUYUGfeWypaCG02ItfjGfd6cxkR71vlmSf2VE7U4=; b=OJGXLdM6nYEn5+gDX8+QNTy+9xo6T/cqx74S9BXxh1JMyqnkG7hFfgPiIjOjHPtPZc WgeWqWOBJISan+zfijLDS60BWoL/VoluenqIiau1w0owtk7/DQ60cGw9/Ed32H0wLV7r pveam/L6j5uHVnsinZ7JHMf9x15JZyYMFN5QgD5j5aLZt7th01BQ/cUTqb96tQCKC3Zn Xzl+iqeR6reorHQJOmYPKZbSso10o/s4p0CHdul28kCtPGzYZewks2MkWdRloWnbnQs9 vHrX23FArnb0u9kCJAbmbtMO16cjp6Lcx0RoBSDmXY1PBSsbx7sDCAUZJVLIW1fEzyRV SJGg== X-Gm-Message-State: ACrzQf03+rNL0mcNbuXpqJ4tmimfKpLofxebqUIWbEPD4gEs7AfAz3+n 2bHFu2TidL6YRwSWKXXDmKjcTGQ+UOGVT7xW X-Received: by 2002:a7b:c048:0:b0:3b4:fb26:f0f3 with SMTP id u8-20020a7bc048000000b003b4fb26f0f3mr7482015wmc.115.1666903652295; Thu, 27 Oct 2022 13:47:32 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id r9-20020a05600c458900b003b4ac05a8a4sm7361417wmo.27.2022.10.27.13.47.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 27 Oct 2022 13:47:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: Jiaxun Yang , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= Subject: [PATCH v2 1/3] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Date: Thu, 27 Oct 2022 22:47:18 +0200 Message-Id: <20221027204720.33611-2-philmd@linaro.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221027204720.33611-1-philmd@linaro.org> References: <20221027204720.33611-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bernhard Beschow --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 272d93eea7..df0f448b67 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -72,6 +72,8 @@ #define MAX_IDE_BUS 2 +#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) + typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ @@ -1377,7 +1379,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, + piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true, TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(piix4); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); From patchwork Thu Oct 27 20:47:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 619228 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp555112pvb; Thu, 27 Oct 2022 13:48:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6RHXtptcTljv710XPTUSlGTbctvRnXWqScKOOOIzaxDSE1SF5ZB5JXs1jq3e1gRQ6TPXEc X-Received: by 2002:a05:622a:134f:b0:39d:18f5:b2be with SMTP id w15-20020a05622a134f00b0039d18f5b2bemr31476316qtk.199.1666903684709; Thu, 27 Oct 2022 13:48:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666903684; cv=none; d=google.com; s=arc-20160816; b=NrIYAfeZ2ryJMoXAh2tc8lP//tCqNqL1rzr/v1G369UL091ExwLU2R6Xo/cWFNSD3h zHMV2L8TYB/n032lRffZm5crbc4SeWyB1rgB2bh0evBVmm09wjpuQpODFfbNLj/wfp5k kWa4PGboJKbnLUjDA1WoGIgBbHpJOK8AG8ytfAYdJYV9GabTcM2DtmAIWSQZAXYuEGom 4+2WyIY//kEzXp9Ps0ZIaBcEN/iU28W1YQZ9yWxGLnJQrCYfptlsRuVbh41zDNPuoHvW 54LEyjzUSRR50zzxUjXd7IWU6cKKExADzYEUApN/GXs//PRc6aNkiLp3ncZaeEXVZx3h x7zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0gABDM3SAd3eC6ZX61AV1tyP17xHBzgjqBVHS8eXGXg=; b=kCMA5MjjqKu+exzfdLrTxYnSSoAg449vOUpgAw/VfcP370wExHybQMyF4RyKKhqUVT 2DLoD8s0Gxfi9rTs6CUAg1Ia01TwoXJHoeISqc0X0UzYLTxg0xD4AyX9yN0J7YYW3zVP xLB2FPRf8O/kToSRwby7tyXAwB/gQR8eP08zj5Hp3/jrJgjF4STPywi9BdY5NhCM7Z1u 9xH3fP4JHur4TvbwX4t3M2MoURjK4sjv1bAy+Lb7KaiTmxfWInLR2ryj2au52MIsn/5d Srww295uWOQbD+JS5gsPNYJdkuV5fkvGbk15c+xDVP9lUgrlCal/jazcmJxqwLJy5qhX dZ5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cAi+oU2Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daudé --- FIXME: Missing the nanoMIPS counter-part! --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index df0f448b67..4403028778 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); stw_p(p++, NM_HI2(kernel_entry)); @@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] = { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; /* Small bootloader */ @@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, #undef cpu_to_gt32 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /* From patchwork Thu Oct 27 20:47:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 619231 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp555841pvb; Thu, 27 Oct 2022 13:49:42 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Phhmxpysht8/BrE+aK/wqEwVabR6cBFs8J2X8dJbt5bC5yymAg0XT5VNbx19Pgy8xMTFP X-Received: by 2002:a05:622a:1313:b0:39c:ff31:21e0 with SMTP id v19-20020a05622a131300b0039cff3121e0mr10499815qtk.274.1666903782393; Thu, 27 Oct 2022 13:49:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666903782; cv=none; d=google.com; s=arc-20160816; b=zIJBKJkBz0cbxXToQU4nc0Kz8PQoLMr/qJS8kuUSQmfbuskOIyWLLdJ53CDJbfqfIN wrw1DugrgucVQbDTVAUmVBcCr03+ST6HcVVXYFx5St2rqqiL4e0qFal/3FS+uO+SudJj w6JDUmvl7ZKiQE1tAbEuWB2vGfn+qUg9IRQ+CXQJtz/Y+OMG6HIssXNsmkZLsSmdk5F+ j10n+OgpK2KCRsGUBYsk1Et0w/C7EIjSzXkSVqeMOt4OnnsrJYjQ2Yf6yYuRs0X0Kw/X ddnyHlDZenX5HfDSj4wPRTGi9xyfskIN/6brZtzfKxL1AX6U0FyBXhwOFJ6oMqYu8fZJ KwLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FideTTwLBlaM3Uj+ggSbpikD+Db2qX3oNiUh+CsQYlw=; b=s/YH+v9oj0oWATnq07Z18P7WZvXjjHK7PliV+MbzfJoeLno6JcZao3wUfxFjErXqKj W23dBzTMh4tXoCLIU73MNps2Zvm0JpE5K+TZ64PLiY6Q9cu2JC5d2hEbU52QjV4TDj3s iXqvGsX9DBCIox5bptrwF2fPptWuIR5/8zB1fFDcgtnqZTJM6pkYeqIfsbBoyEwqA9cW 8og4s9LszO6gynAED5MZsf6ZB7UwcYs6TlnQJGend5Kl1Wg9PfjgvQ7MQsMYqqqBpLmU Vuqokd1kAu4RtkDK1mimeuonERRQneYnGNRJFGWhtdkI3gPvDXm/KlWdVt7LUJOQaM7x FMAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y0anLze3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 190-20020a3705c7000000b006eb472451fcsi1511523qkf.113.2022.10.27.13.49.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Oct 2022 13:49:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y0anLze3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oo9nE-0003RU-KX; Thu, 27 Oct 2022 16:48:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oo9n1-0003He-Sx for qemu-devel@nongnu.org; Thu, 27 Oct 2022 16:47:55 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oo9my-0007VO-P2 for qemu-devel@nongnu.org; Thu, 27 Oct 2022 16:47:47 -0400 Received: by mail-wr1-x42b.google.com with SMTP id w14so4168089wru.8 for ; Thu, 27 Oct 2022 13:47:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FideTTwLBlaM3Uj+ggSbpikD+Db2qX3oNiUh+CsQYlw=; b=y0anLze37SuyGnx2X0R5zVokWIq4ZWzf/8hDyAr9+NGCdErnT7jiShtfbi7ZwT3Ray vMbSh5FaNi0txW1TTMkpEPqP1Lh0Jd5N7QDCRWzbLrWeVQLdNGcuphBYrW5EuePdbdXQ qoA0d44I1mkXqHe7mXBChByiZIUD/Wckigrnbw2ICVWPEN3bJ0/dbAkJKJDVNxwXKNPb Ilzv6PKu9saey7uxWIpeb6gKSGGD+Yqvq4k1wKb+V0EaSbcRfOz57YvVaofQsUYBH1gr JrgeiyFS3Vku+FUZFlNnbcRzE6d5aQYsnqh0cuR/o7RlWwGlR4kJqZJWVpjEVBhVWAZS C3eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FideTTwLBlaM3Uj+ggSbpikD+Db2qX3oNiUh+CsQYlw=; b=JLgy73sI7XtkVTutIJCswZIfbWhBGZXmZre76z1jFNEkABgQ1+tT9gNNJaimOEcfvj Hr/UOAHFHol8lApPrFy85QC+//E2J+Z1tGP1KnXQQE+aSe53bicHpbFUEUsh8Og4CQm3 RIQ6/TK81GLdSjA1Bv6SL+oRx5+fS06Ih8lt40ydfUGgGbCtNaZM8xR8uEJmTYSmlyT+ uPIepkYLtrvrEYSNr4VWhbjYtiRpOwIB4t9fKq5ayPLYa3oMmMBsI2rS38ziWTDfQHYM nDQa0PDPL3su+Id/0zBImPVYW12THJCylQ4/25Q9OXExoM1t6y6+JizJ6aQkCf8DNsr2 lWcA== X-Gm-Message-State: ACrzQf2xk2O7x4ZHBaech2LqRoQBulUB0e/gbMjHt1ACY3vtSbp/jOhR z8h19RlMOhFM1aH+3f4eKf0ktjmZ3az4Ew1X X-Received: by 2002:a5d:69c2:0:b0:236:86fc:4400 with SMTP id s2-20020a5d69c2000000b0023686fc4400mr8513748wrw.69.1666903663218; Thu, 27 Oct 2022 13:47:43 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id w7-20020adfd4c7000000b002362f6fcaf5sm1948159wrk.48.2022.10.27.13.47.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 27 Oct 2022 13:47:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: Jiaxun Yang , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= Subject: [PATCH v2 3/3] hw/isa/piix4: Correct IRQRC[A:D] reset values Date: Thu, 27 Oct 2022 22:47:20 +0200 Message-Id: <20221027204720.33611-4-philmd@linaro.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221027204720.33611-1-philmd@linaro.org> References: <20221027204720.33611-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bernhard Beschow Reviewed-by: Igor Mammedov --- hw/isa/piix4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 15f344dbb7..a2165c6a49 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -115,10 +115,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 + pci_conf[0x60] = 0x80; + pci_conf[0x61] = 0x80; + pci_conf[0x62] = 0x80; + pci_conf[0x63] = 0x80; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c;