From patchwork Mon Oct 24 17:54:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 619420 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6D8DC38A2D for ; Mon, 24 Oct 2022 19:23:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232305AbiJXTXA (ORCPT ); Mon, 24 Oct 2022 15:23:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232014AbiJXTVv (ORCPT ); Mon, 24 Oct 2022 15:21:51 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E889E140BA for ; Mon, 24 Oct 2022 10:57:18 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id s196so9308267pgs.3 for ; Mon, 24 Oct 2022 10:57:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kj33p7JdC03bi8muflplwrkkTeKEhU1qK5ms8K2qnYw=; b=nzykeBNFH40raHYAmGXOty01g/6nzbiDvq+zDWKIdNwOAPn5f8q4jxQnDVsAG1oDcC AhM8H5Av+nJ9E6ng/FNVrDq75WbJDwmUEvLj2Kg814cjo2iUn/ASUE04gAbuSFX1lRDy BCKNYIqneKZWIYFdZOXNRu+y0xg7hgX7j7WGY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kj33p7JdC03bi8muflplwrkkTeKEhU1qK5ms8K2qnYw=; b=whiJCk23YfDImqR77bXllAmR20brFxlWlgnxrpx2FN0CWmHJaX7dMdhpnjuORrB/5V +I4D6iY7cLY/14bfV0/RhINCdFsUbz/TfOVohIDpx3h+SssTG70kDYbf8raaSJbSfRhV Xef6uHMociE1fXR9iG63P6qTBQCvcBf9oHJ3Hg/0AscODYNFUwNcGRt1P+LSLMb5O/8L NeLMKNL88tvc6agfl6z06edeY9zbzKpZWyriKnXKgPq5HQ3swqu7hMNPqNuHaQgeDevn g7dzTyk8NgzD0MQ3+Y7woIqz+kl3cIn7uUGG2lmkUOLY16QVYY9QaVseOole9kzeIi+q WtQQ== X-Gm-Message-State: ACrzQf1ZsOriqaZKShyP+WKE6T/ZRkDtshHSi7YhgnCEhcAIE69fBm56 h607m+BFod0dp6I/jKzhJ2P/zg== X-Google-Smtp-Source: AMsMyM5BdgZEyjt56UqLJ4vmOVqtMG2g5CTexuitasuGfHwHzRTZ7b/Y++JkhG9PKeh5Y7FxoCAnow== X-Received: by 2002:a05:6a00:e1b:b0:537:7c74:c405 with SMTP id bq27-20020a056a000e1b00b005377c74c405mr34703121pfb.43.1666634176496; Mon, 24 Oct 2022 10:56:16 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:808b:e2f6:edcf:ccb0]) by smtp.gmail.com with UTF8SMTPSA id a1-20020a170902ecc100b0016cf3f124e1sm30195plh.234.2022.10.24.10.56.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Oct 2022 10:56:15 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , linux-mmc@vger.kernel.org, Al Cooper , Bjorn Andersson , Sowjanya Komatineni , Broadcom internal kernel review list , Sascha Hauer , Konrad Dybcio , Florian Fainelli , NXP Linux Team , Thierry Reding , Fabio Estevam , Michal Simek , linux-kernel@vger.kernel.org, Shawn Guo , Adrian Hunter , Pengutronix Kernel Team , linux-arm-msm@vger.kernel.org, Haibo Chen , Andy Gross , linux-arm-kernel@lists.infradead.org, Faiz Abbas , Jonathan Hunter , Brian Norris , stable@vger.kernel.org, Guenter Roeck Subject: [PATCH v3 2/7] mmc: sdhci-of-arasan: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 24 Oct 2022 10:54:56 -0700 Message-Id: <20221024105229.v3.2.I29f6a2189e84e35ad89c1833793dca9e36c64297@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221024175501.2265400-1-briannorris@chromium.org> References: <20221024175501.2265400-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but one particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). Typically we will eventually deactivate CQE (cqhci_suspend() -> cqhci_deactivate()), but that's not guaranteed -- in particular, if we perform a partial (e.g., interrupted) system suspend. The same bug was already found and fixed for two other drivers, in v5.7 and v5.9: 5cf583f1fb9c mmc: sdhci-msm: Deactivate CQE during SDHC reset df57d73276b8 mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers The latter is especially prescient, saying "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." So like these other patches, deactivate CQHCI when resetting the controller. Do this via the new sdhci_and_cqhci_reset() helper. Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: Signed-off-by: Brian Norris Reviewed-by: Guenter Roeck --- Changes in v3: - Refactor to a "SDHCI and CQHCI" helper -- sdhci_and_cqhci_reset() Changes in v2: - Rely on cqhci_deactivate() to safely handle (ignore) not-yet-initialized CQE support drivers/mmc/host/sdhci-of-arasan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 3997cad1f793..cfb891430174 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -25,6 +25,7 @@ #include #include "cqhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 @@ -366,7 +367,7 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); From patchwork Mon Oct 24 17:54:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 619422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B7D9FA3741 for ; Mon, 24 Oct 2022 19:22:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230433AbiJXTV6 (ORCPT ); Mon, 24 Oct 2022 15:21:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232082AbiJXTVN (ORCPT ); Mon, 24 Oct 2022 15:21:13 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE51415A8FC for ; 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Mon, 24 Oct 2022 10:56:20 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:808b:e2f6:edcf:ccb0]) by smtp.gmail.com with UTF8SMTPSA id w20-20020a170902ca1400b001714e7608fdsm26385pld.256.2022.10.24.10.56.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Oct 2022 10:56:20 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , linux-mmc@vger.kernel.org, Al Cooper , Bjorn Andersson , Sowjanya Komatineni , Broadcom internal kernel review list , Sascha Hauer , Konrad Dybcio , Florian Fainelli , NXP Linux Team , Thierry Reding , Fabio Estevam , Michal Simek , linux-kernel@vger.kernel.org, Shawn Guo , Adrian Hunter , Pengutronix Kernel Team , linux-arm-msm@vger.kernel.org, Haibo Chen , Andy Gross , linux-arm-kernel@lists.infradead.org, Faiz Abbas , Jonathan Hunter , Brian Norris Subject: [PATCH v3 3/7] mmc: sdhci-brcmstb: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 24 Oct 2022 10:54:57 -0700 Message-Id: <20221024105229.v3.3.I6a715feab6d01f760455865e968ecf0d85036018@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221024175501.2265400-1-briannorris@chromium.org> References: <20221024175501.2265400-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. Fixes: d46ba2d17f90 ("mmc: sdhci-brcmstb: Add support for Command Queuing (CQE)") Signed-off-by: Brian Norris --- Changes in v3: - Use new SDHCI+CQHCI helper Changes in v2: - Rely on cqhci_deactivate() to handle NULL cqe_private, instead of moving around CQE capability flags drivers/mmc/host/sdhci-brcmstb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index aff36a933ebe..55d8bd232695 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -12,6 +12,7 @@ #include #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -55,7 +56,7 @@ static void brcmstb_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); /* Reset will clear this, so re-enable it */ if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) From patchwork Mon Oct 24 17:54:59 2022 Content-Type: text/plain; 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Mon, 24 Oct 2022 10:56:26 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:808b:e2f6:edcf:ccb0]) by smtp.gmail.com with UTF8SMTPSA id g29-20020aa79ddd000000b0056bdb5197f4sm103804pfq.35.2022.10.24.10.56.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Oct 2022 10:56:25 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , linux-mmc@vger.kernel.org, Al Cooper , Bjorn Andersson , Sowjanya Komatineni , Broadcom internal kernel review list , Sascha Hauer , Konrad Dybcio , Florian Fainelli , NXP Linux Team , Thierry Reding , Fabio Estevam , Michal Simek , linux-kernel@vger.kernel.org, Shawn Guo , Adrian Hunter , Pengutronix Kernel Team , linux-arm-msm@vger.kernel.org, Haibo Chen , Andy Gross , linux-arm-kernel@lists.infradead.org, Faiz Abbas , Jonathan Hunter , Brian Norris Subject: [PATCH v3 5/7] mmc: sdhci-tegra: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 24 Oct 2022 10:54:59 -0700 Message-Id: <20221024105229.v3.5.I418c9eaaf754880fcd2698113e8c3ef821a944d7@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221024175501.2265400-1-briannorris@chromium.org> References: <20221024175501.2265400-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Include this fix by way of the new sdhci_and_cqhci_reset() helper. Fixes: 3c4019f97978 ("mmc: tegra: HW Command Queue Support for Tegra SDMMC") Signed-off-by: Brian Norris --- Changes in v3: - Use new SDHCI+CQHCI helper Changes in v2: - Drop unnecessary 'enable_hwcq' check drivers/mmc/host/sdhci-tegra.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 413925bce0ca..c71000a07656 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -28,6 +28,7 @@ #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -367,7 +368,7 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; u32 misc_ctrl, clk_ctrl, pad_ctrl; - sdhci_reset(host, mask); + sdhci_and_cqhci_reset(host, mask); if (!(mask & SDHCI_RESET_ALL)) return; From patchwork Mon Oct 24 17:55:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 619419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F8C1FA3740 for ; Mon, 24 Oct 2022 19:23:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232515AbiJXTXK (ORCPT ); Mon, 24 Oct 2022 15:23:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231697AbiJXTWC (ORCPT ); Mon, 24 Oct 2022 15:22:02 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DE12615B for ; Mon, 24 Oct 2022 10:57:25 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id f140so9633443pfa.1 for ; Mon, 24 Oct 2022 10:57:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kBU82kTAb6ejCzCPdRzJommk6OJkr5XyNm4aFLMb1Lo=; b=RnX9z/EyXFWaUQ4+NHwDXdpAWxW+FR9R8nm39w0AaYU9kdznNu4IHmM6GSKF4cRcV4 aRfuhZxa9CM2GIlk54VdFm5ss32J0pIw9JiN4zYfVZ12g2Llv4W2LoC94v4PMZ40bAzx 3kA73t9lBnjmWm9QMfq36+K1fqNixXiAfEkTE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kBU82kTAb6ejCzCPdRzJommk6OJkr5XyNm4aFLMb1Lo=; b=ZmxNAABXLqKFucCf/2kw/I2TmX8fzyGN+Vhrw8SPGtzp6Ibmte0nMvqYxzkgAXZzMp 1kSteIP4JvnO/QH6qlL1lPW4Egta6Fmqe2ltGbKZYp4eOEzSx2nEGoQXyr2tiAp1rzzP Ush5g9rmzP6kH/ud2OY9TW2DUWJaSPpyCP64Sn8Z9GKR15EvumrLJJJ1aapxXeOR4nfU PFkYSELaZ9WR23tyIWogseblu0+ra2vhUIVlvwkPbN54xu/oZviNMeOxWsGwug+j5b8R iqe2p4n8vedl4Xva9RUyCshX7X/VOKe2P73PHDsb6lGrElslDk2/Qj/qH2CKU7WSVnJP Xx8g== X-Gm-Message-State: ACrzQf0k+LDjM3F36snTgiFlvbBKVzrSGpuzuSmFRumNdOagBwUXRESk tQ1cqZegKmahGSjv+tLi6w/IQA== X-Google-Smtp-Source: AMsMyM6Hp0vgunlSJu4/TCH07DNhzYhxDd1XyT5BfXLbDyfeI3MU6gI+gnXmu+1SQyl1XKUTxmYmYQ== X-Received: by 2002:a62:1a97:0:b0:562:5587:12d6 with SMTP id a145-20020a621a97000000b00562558712d6mr34124134pfa.37.1666634192416; Mon, 24 Oct 2022 10:56:32 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:808b:e2f6:edcf:ccb0]) by smtp.gmail.com with UTF8SMTPSA id b1-20020a1709027e0100b00176a6ba5969sm39531plm.98.2022.10.24.10.56.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Oct 2022 10:56:32 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , linux-mmc@vger.kernel.org, Al Cooper , Bjorn Andersson , Sowjanya Komatineni , Broadcom internal kernel review list , Sascha Hauer , Konrad Dybcio , Florian Fainelli , NXP Linux Team , Thierry Reding , Fabio Estevam , Michal Simek , linux-kernel@vger.kernel.org, Shawn Guo , Adrian Hunter , Pengutronix Kernel Team , linux-arm-msm@vger.kernel.org, Haibo Chen , Andy Gross , linux-arm-kernel@lists.infradead.org, Faiz Abbas , Jonathan Hunter , Brian Norris Subject: [PATCH v3 7/7] mmc: sdhci-*: Convert drivers to new sdhci_and_cqhci_reset() Date: Mon, 24 Oct 2022 10:55:01 -0700 Message-Id: <20221024105229.v3.7.Ia91f031f5f770af7bd2ff3e28b398f277606d970@changeid> X-Mailer: git-send-email 2.38.0.135.g90850a2211-goog In-Reply-To: <20221024175501.2265400-1-briannorris@chromium.org> References: <20221024175501.2265400-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org An earlier patch ("mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI") does these operations for us. I keep these as a separate patch, since the earlier patch is a prerequisite to some important bugfixes that need to be backported via linux-stable. Signed-off-by: Brian Norris --- Changes in v3: - Rewrite to new helper, patch sdhci-msm too Changes in v2: - Factor out ->cqe_private helpers drivers/mmc/host/sdhci-msm.c | 10 ++-------- drivers/mmc/host/sdhci-pci-core.c | 11 ++--------- drivers/mmc/host/sdhci-pci-gli.c | 11 ++--------- 3 files changed, 6 insertions(+), 26 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 3a091a387ecb..03f76384ab3f 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -19,6 +19,7 @@ #include #include +#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" @@ -2304,13 +2305,6 @@ static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host) pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); } -static void sdhci_msm_reset(struct sdhci_host *host, u8 mask) -{ - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) - cqhci_deactivate(host->mmc); - sdhci_reset(host, mask); -} - static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host) { int ret; @@ -2450,7 +2444,7 @@ static const struct of_device_id sdhci_msm_dt_match[] = { MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); static const struct sdhci_ops sdhci_msm_ops = { - .reset = sdhci_msm_reset, + .reset = sdhci_and_cqhci_reset, .set_clock = sdhci_msm_set_clock, .get_min_clock = sdhci_msm_get_min_clock, .get_max_clock = sdhci_msm_get_max_clock, diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 169b84761041..cc039155b5c7 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -38,6 +38,7 @@ #include "cqhci.h" #include "sdhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pci.h" static void sdhci_pci_hw_reset(struct sdhci_host *host); @@ -234,14 +235,6 @@ static void sdhci_pci_dumpregs(struct mmc_host *mmc) sdhci_dumpregs(mmc_priv(mmc)); } -static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask) -{ - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && - host->mmc->cqe_private) - cqhci_deactivate(host->mmc); - sdhci_reset(host, mask); -} - /*****************************************************************************\ * * * Hardware specific quirk handling * @@ -703,7 +696,7 @@ static const struct sdhci_ops sdhci_intel_glk_ops = { .set_power = sdhci_intel_set_power, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_cqhci_reset, + .reset = sdhci_and_cqhci_reset, .set_uhs_signaling = sdhci_intel_set_uhs_signaling, .hw_reset = sdhci_pci_hw_reset, .irq = sdhci_cqhci_irq, diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 4d509f656188..633a8ee8f8c5 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -15,6 +15,7 @@ #include #include #include "sdhci.h" +#include "sdhci-cqhci.h" #include "sdhci-pci.h" #include "cqhci.h" @@ -922,14 +923,6 @@ static int gl9763e_add_host(struct sdhci_pci_slot *slot) return ret; } -static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask) -{ - if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && - host->mmc->cqe_private) - cqhci_deactivate(host->mmc); - sdhci_reset(host, mask); -} - static void gli_set_gl9763e(struct sdhci_pci_slot *slot) { struct pci_dev *pdev = slot->chip->pdev; @@ -1136,7 +1129,7 @@ static const struct sdhci_ops sdhci_gl9763e_ops = { .set_clock = sdhci_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_gl9763e_reset, + .reset = sdhci_and_cqhci_reset, .set_uhs_signaling = sdhci_set_gl9763e_signaling, .voltage_switch = sdhci_gli_voltage_switch, .irq = sdhci_gl9763e_cqhci_irq,