From patchwork Mon Oct 31 17:27:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 620285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB7DAFA3741 for ; Mon, 31 Oct 2022 17:27:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231580AbiJaR1v (ORCPT ); Mon, 31 Oct 2022 13:27:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231423AbiJaR1r (ORCPT ); Mon, 31 Oct 2022 13:27:47 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20F4F13CDE; Mon, 31 Oct 2022 10:27:45 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 29VHO0lt008142; Mon, 31 Oct 2022 17:27:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=O+w9lGOhPyqCtjmnPAnAruDm3ryHtBkHMrAOy4NESwE=; b=ep2OIW84mP46Qf/oW+dXBwS32b1/ACYjxEKnqx9gY3UKrrvXYWEiBelMUgLvdgNKl6fq WEmt0tZCYqoCcKzcIxUsmYiqykYYIPeK4+8P9bUoNITjzYD9gV1AVP3SIvjGjGAK73cv 1Xejpz6cHOI7kDkdEKYeB6IABkde0srF91iJll9foGAsz1+eOAs9P7Fh5B8nO32zTAan BMuutYlBwkMOc6l45QMEQNw+f7bEzwj9CzeZD96ttBNmGFNmMdPpDD915AWoQcG5Qyqg U4iLRBDYBBhOwaOS1bSt78Dbb/Qlp/clWoOofPhioW6/i3XigVmvHpvDns/3s5jYHa7z Tg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kjjqb00hr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Oct 2022 17:27:33 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29VHRWZh017547 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Oct 2022 17:27:32 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 31 Oct 2022 10:27:32 -0700 From: Kuogee Hsieh To: , , , , , , , , , CC: , , , , , , Subject: [PATCH] drm/msm/dp: remove limitation of link rate at 5.4G to support HBR3 Date: Mon, 31 Oct 2022 10:27:25 -0700 Message-ID: <1667237245-24988-1-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: B3uYstytrGzf9Q_1GyZqjspKPjlymOPk X-Proofpoint-GUID: B3uYstytrGzf9Q_1GyZqjspKPjlymOPk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-31_19,2022-10-31_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 bulkscore=0 mlxscore=0 mlxlogscore=632 priorityscore=1501 spamscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210310108 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org An HBR3-capable device shall also support TPS4. Since TPS4 feature had been implemented already, it is not necessary to limit link rate at HBR2 (5.4G). This patch remove this limitation to support HBR3 (8.1G) link rate. Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/dp/dp_panel.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 5149ceb..3344f5a 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -78,10 +78,6 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) if (link_info->num_lanes > dp_panel->max_dp_lanes) link_info->num_lanes = dp_panel->max_dp_lanes; - /* Limit support upto HBR2 until HBR3 support is added */ - if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4))) - link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4); - drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes);