From patchwork Tue Nov 1 15:56:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 620715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7475C38A2B for ; Tue, 1 Nov 2022 15:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229462AbiKAP4c (ORCPT ); Tue, 1 Nov 2022 11:56:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229981AbiKAP4a (ORCPT ); Tue, 1 Nov 2022 11:56:30 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F8FC381; Tue, 1 Nov 2022 08:56:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667318189; x=1698854189; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=32rEyVNWT8FR+vish5GvE6UoII8LYbwmJ5c2195UtCk=; b=bdpLUrip82BJsF3anrXGwC8D1ZBmXmi7RpvMpHv89WkaopcdjBnnPppH MfqzuLKD8f2lSvHY2zAE454XvJgQ6zLNUNQQ5pXd4DCM6Q14vgmpISCEz gMwhyGAWYTJAFxyoz5+Hb4ema0EicsvyTMfFyntGQl9WAFBx1qbRn1s79 5SLeNZMQzu/mtplADnNLBuk03+P3mg5CjQskeHbZTWJQ4A7SA2Dq9/oSi n9OnqaEFqD4Q6NUYuOWbQDNGbqWelPQF5uhLhvZ3LaSGFcMrR7q9+APqB 4XC+SVtDszCmXYRW/VyQHO59s33qaCXX3zezvkOUHMxRmGwy/NaBTKcUE w==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="292474808" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="292474808" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 08:56:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="776537915" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="776537915" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 01 Nov 2022 08:56:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 6A44BD0; Tue, 1 Nov 2022 17:56:47 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v1 1/6] pwm: Add a stub for devm_pwmchip_add() Date: Tue, 1 Nov 2022 17:56:37 +0200 Message-Id: <20221101155642.52575-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> References: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org devm_pwmchip_add() can be called by a module that optionally instantiates PWM chip. In case of CONFIG_PWM=n, the compilation can't be performed. Hence, add a necessary stub. Signed-off-by: Andy Shevchenko --- include/linux/pwm.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/pwm.h b/include/linux/pwm.h index d70c6e5a839d..bba492eea96c 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -478,6 +478,11 @@ static inline int pwmchip_remove(struct pwm_chip *chip) return -EINVAL; } +static inline int devm_pwmchip_add(struct device *dev, struct pwm_chip *chip) +{ + return -EINVAL; +} + static inline struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, unsigned int index, const char *label) From patchwork Tue Nov 1 15:56:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 621186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AB6DC4321E for ; Tue, 1 Nov 2022 15:56:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230037AbiKAP4b (ORCPT ); Tue, 1 Nov 2022 11:56:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229827AbiKAP43 (ORCPT ); Tue, 1 Nov 2022 11:56:29 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BBBF65AC; Tue, 1 Nov 2022 08:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667318188; x=1698854188; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NI154NeC1RWG4hSdSSq9uISzU3eVykdnlrIdlNSvC4A=; b=KkXarmWr/Efn/RiHllZ6FOxL4J4zLyJxG7rAdBs3f6Hn513mEUpjTm8H fyfa/3KqBnIskWPCOXYoJvTlkCXFhbl6GyybEo06AuBESG9dNIMP2zueI TThVK7v8VzU+YY/0iqMqSBquVv5BowV5kBBJN+VpnYFsiMyDxn7ktXmYy 76iBf44lfehHNVDii4hhhTFj5iNgWqYbVwySY8YvYKUpZ2YydgvM9Htkt tygQoDQ7SAYGjCX7FK8sEE3KCvqve/9dwzu5H2bR/IhhbI9X3+pXBVBVk qTSgHNAUqzU0XKTHNehSuHE77rL4X9W1B40Y4KkUjODYoidMEqbx0QWia A==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="292474806" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="292474806" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 08:56:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="776537916" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="776537916" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 01 Nov 2022 08:56:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 7271215C; Tue, 1 Nov 2022 17:56:47 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v1 2/6] pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS Date: Tue, 1 Nov 2022 17:56:38 +0200 Message-Id: <20221101155642.52575-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> References: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The MAX_PWMS definition is already being used by PWM core. Using the same name in the certain driver confuses people and potentially can clash with it. Hence, rename it by adding LPSS prefix. Reported-by: Uwe Kleine-König Signed-off-by: Andy Shevchenko --- drivers/pwm/pwm-lpss.c | 2 +- drivers/pwm/pwm-lpss.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index accdef5dd58e..b8739cd2c235 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -252,7 +252,7 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, int i, ret; u32 ctrl; - if (WARN_ON(info->npwm > MAX_PWMS)) + if (WARN_ON(info->npwm > LPSS_MAX_PWMS)) return ERR_PTR(-ENODEV); lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index 8e82eb5a7e00..2c746c51b883 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -13,7 +13,7 @@ #include #include -#define MAX_PWMS 4 +#define LPSS_MAX_PWMS 4 struct pwm_lpss_chip { struct pwm_chip chip; From patchwork Tue Nov 1 15:56:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 621185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20735C4167E for ; Tue, 1 Nov 2022 15:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbiKAP4c (ORCPT ); Tue, 1 Nov 2022 11:56:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229920AbiKAP43 (ORCPT ); Tue, 1 Nov 2022 11:56:29 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D48BDEE4; Tue, 1 Nov 2022 08:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667318188; x=1698854188; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3EvRlLYJGkNaFR0CEneATqIgsr+cfpB23wrxayXUipM=; b=Mr5I/Z7vshj0P/SIWBRS89+qJNXwYLFoSBuSsNbSmOALgQ2OKSibe2NV ZKz8ny+X8aJPokYZ5hFC6HVi+OXeTUC2AwdrXbRH36CtU/Aefb5QqH476 JK8ORLGBKflPS5HUhyJ02xKIPVkLF9+MbafuNaea9sNOj8TxA0hci7xXo gHkFD6IyLyM95afq928YbSXzKdvjVvWSKQZ77y2eHGyCEJCZ2XXQejdQP PEdfZzrDR4Zoz9N/4n2PZVCQXmMsv4dSSQuAy9EjTpu/JDxb505cwK/yX 3/gWPma1mOh5dbHlO9H7z7gbWKvYNx0Cgw33iiYTdpGKaJr49GJZZ7sF0 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="335838671" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="335838671" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 08:56:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="628614197" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="628614197" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 01 Nov 2022 08:56:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 79F9B1E5; Tue, 1 Nov 2022 17:56:47 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v1 3/6] pwm: lpss: Include headers we are direct user of Date: Tue, 1 Nov 2022 17:56:39 +0200 Message-Id: <20221101155642.52575-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> References: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org For the sake of integrity, include headers we are direct user of. While at it, move the struct pwm_lpss_chip to be after the struct pwm_lpss_boardinfo as the former uses pointer to the latter. Replace device.h with a forward declaration in order to improve the compilation time due to reducing overhead of device.h parsing with entire train of dependencies. Signed-off-by: Andy Shevchenko Reviewed-by: Hans de Goede --- drivers/pwm/pwm-lpss.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index 2c746c51b883..4561d229b27d 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -10,16 +10,12 @@ #ifndef __PWM_LPSS_H #define __PWM_LPSS_H -#include #include +#include -#define LPSS_MAX_PWMS 4 +struct device; -struct pwm_lpss_chip { - struct pwm_chip chip; - void __iomem *regs; - const struct pwm_lpss_boardinfo *info; -}; +#define LPSS_MAX_PWMS 4 struct pwm_lpss_boardinfo { unsigned long clk_rate; @@ -43,6 +39,12 @@ extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info; +struct pwm_lpss_chip { + struct pwm_chip chip; + void __iomem *regs; + const struct pwm_lpss_boardinfo *info; +}; + struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, const struct pwm_lpss_boardinfo *info); From patchwork Tue Nov 1 15:56:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 620716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA904C43217 for ; Tue, 1 Nov 2022 15:56:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229971AbiKAP4a (ORCPT ); Tue, 1 Nov 2022 11:56:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229475AbiKAP42 (ORCPT ); Tue, 1 Nov 2022 11:56:28 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0D606460; Tue, 1 Nov 2022 08:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667318187; x=1698854187; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XBafnubMqFq/SZkOKUaP3VSykoY0r8hf6OiR8NcEyP8=; b=lGqFiRte+bUByNzGAgCAbpAFBp7T9zMJ7upGCEs5KXpKWKcXyeWiGzib PhhoIjJW+beYKuECqBUdOG3dTS83w3tz9qNPITTRyY8tG9++zXh0ccz3m /j8ZGnoey+VPHdoCNWYAm2/4SYhcGoy3dcioxGyhu1rfcyrOYfC452fFu XTycDwBw6a0WcP9UHpOrPM21qKwG3d+JOPlsFXct/lTcdvZEVful1RmOS 3mqQkRShsgotf0fJLD0Sb+eyPJwy5MjMu9ECNU4QGjmdv9RiIZi4NQmhO oRFg1mnzxZ7so4N28F//sJXRtPqYwDRr/n12IJqP8M5+b2QSYSPOErqn6 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="335838670" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="335838670" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 08:56:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="628614198" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="628614198" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 01 Nov 2022 08:56:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 8154029D; Tue, 1 Nov 2022 17:56:47 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v1 4/6] pwm: lpss: Allow other drivers to enable PWM LPSS Date: Tue, 1 Nov 2022 17:56:40 +0200 Message-Id: <20221101155642.52575-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> References: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The PWM LPSS device can be embedded in another device. In order to enable it, allow that drivers to probe a corresponding device. Signed-off-by: Andy Shevchenko Reviewed-by: Hans de Goede --- drivers/pwm/pwm-lpss.h | 22 +-------------- .../linux/platform_data/x86}/pwm-lpss.h | 28 ++++--------------- 2 files changed, 6 insertions(+), 44 deletions(-) copy {drivers/pwm => include/linux/platform_data/x86}/pwm-lpss.h (53%) diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index 4561d229b27d..b721532c6c3c 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -13,27 +13,10 @@ #include #include -struct device; +#include #define LPSS_MAX_PWMS 4 -struct pwm_lpss_boardinfo { - unsigned long clk_rate; - unsigned int npwm; - unsigned long base_unit_bits; - /* - * Some versions of the IP may stuck in the state machine if enable - * bit is not set, and hence update bit will show busy status till - * the reset. For the rest it may be otherwise. - */ - bool bypass; - /* - * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device - * messes with the PWM0 controllers state, - */ - bool other_devices_aml_touches_pwm_regs; -}; - extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; @@ -45,7 +28,4 @@ struct pwm_lpss_chip { const struct pwm_lpss_boardinfo *info; }; -struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, - const struct pwm_lpss_boardinfo *info); - #endif /* __PWM_LPSS_H */ diff --git a/drivers/pwm/pwm-lpss.h b/include/linux/platform_data/x86/pwm-lpss.h similarity index 53% copy from drivers/pwm/pwm-lpss.h copy to include/linux/platform_data/x86/pwm-lpss.h index 4561d229b27d..296bd837ddbb 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/include/linux/platform_data/x86/pwm-lpss.h @@ -1,21 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Intel Low Power Subsystem PWM controller driver - * - * Copyright (C) 2014, Intel Corporation - * - * Derived from the original pwm-lpss.c - */ +/* Intel Low Power Subsystem PWM controller driver */ -#ifndef __PWM_LPSS_H -#define __PWM_LPSS_H +#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H +#define __PLATFORM_DATA_X86_PWM_LPSS_H -#include #include struct device; -#define LPSS_MAX_PWMS 4 +struct pwm_lpss_chip; struct pwm_lpss_boardinfo { unsigned long clk_rate; @@ -34,18 +27,7 @@ struct pwm_lpss_boardinfo { bool other_devices_aml_touches_pwm_regs; }; -extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info; -extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; -extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; -extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info; - -struct pwm_lpss_chip { - struct pwm_chip chip; - void __iomem *regs; - const struct pwm_lpss_boardinfo *info; -}; - struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, const struct pwm_lpss_boardinfo *info); -#endif /* __PWM_LPSS_H */ +#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */ From patchwork Tue Nov 1 15:56:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 621184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 438E5C3A59F for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="335838675" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="335838675" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 08:56:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="628614205" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="628614205" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 01 Nov 2022 08:56:28 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 88BDD2B7; Tue, 1 Nov 2022 17:56:47 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v1 5/6] pwm: lpss: Add pwm_lpss_probe() stub Date: Tue, 1 Nov 2022 17:56:41 +0200 Message-Id: <20221101155642.52575-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> References: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In case the PWM LPSS module is not provided, allow users to be compiled with a help of a pwm_lpss_probe() stub. Signed-off-by: Andy Shevchenko --- include/linux/platform_data/x86/pwm-lpss.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/linux/platform_data/x86/pwm-lpss.h b/include/linux/platform_data/x86/pwm-lpss.h index 296bd837ddbb..c868b396ed2c 100644 --- a/include/linux/platform_data/x86/pwm-lpss.h +++ b/include/linux/platform_data/x86/pwm-lpss.h @@ -4,6 +4,8 @@ #ifndef __PLATFORM_DATA_X86_PWM_LPSS_H #define __PLATFORM_DATA_X86_PWM_LPSS_H +#include +#include #include struct device; @@ -27,7 +29,16 @@ struct pwm_lpss_boardinfo { bool other_devices_aml_touches_pwm_regs; }; +#if IS_REACHABLE(CONFIG_PWM_LPSS) struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, const struct pwm_lpss_boardinfo *info); +#else +static inline +struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, + const struct pwm_lpss_boardinfo *info) +{ + return ERR_PTR(-ENODEV); +} +#endif /* CONFIG_PWM_LPSS */ #endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */ From patchwork Tue Nov 1 15:56:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 620714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D640C41535 for ; Tue, 1 Nov 2022 15:56:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230348AbiKAP4d (ORCPT ); Tue, 1 Nov 2022 11:56:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230100AbiKAP4b (ORCPT ); Tue, 1 Nov 2022 11:56:31 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FC32167E8; Tue, 1 Nov 2022 08:56:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667318191; x=1698854191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9EMEBtyd+ncSOy04taxX8rD97/YD448iR78mVb4VTLI=; b=Amc1/UUZbZYYXCeYtWD7C+H1E+Dkd5JxPxMR007CkP4uPucKxkzSc1vB nsUJyvY1/61kXXdo01XGdUzEl+qA+Q9YgVMFBj5NKrNZs5rVO54B71wJh 50CmP/33NsoS9XFMkAAd/5gwxqTFjXxnV6mygEwk9BCCKgQ9VGJ0dsqQ/ XBte+/lC9xUgEgJqhL8M/qV8ywX22ddQpF1RFm/UvqE0HWlCipFS1o+aG 5F6JNUy/jv6h/XO8LAo4V6E5whsQmatlLY+yo7/g2H1PIqSwNOquA5+Hx c0M4nSMqbcpJY4++s7+VUUYf60rqY8hwSZadtnCS5jh0wHpFoJ54Mz9cZ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="292474815" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="292474815" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 08:56:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="776537934" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="776537934" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 01 Nov 2022 08:56:28 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 903364B5; Tue, 1 Nov 2022 17:56:47 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v1 6/6] pinctrl: intel: Enumerate PWM device when community has a capabilitty Date: Tue, 1 Nov 2022 17:56:42 +0200 Message-Id: <20221101155642.52575-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> References: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Some of the Communities may have PWM capability. In such cases, enumerate PWM device via respective driver. User is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index e17d1318b913..fe5bf2184cbf 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -24,6 +24,8 @@ #include #include +#include + #include "../core.h" #include "pinctrl-intel.h" @@ -49,6 +51,8 @@ #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) #define PADOWN_GPP(p) ((p) / 8) +#define PWMC 0x204 + /* Offset from pad_regs */ #define PADCFG0 0x000 #define PADCFG0_RXEVCFG_SHIFT 25 @@ -1494,6 +1498,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) return 0; } +static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, + struct intel_community *community) +{ + static const struct pwm_lpss_boardinfo info = { + .clk_rate = 19200000, + .npwm = 1, + .base_unit_bits = 22, + .bypass = true, + }; + struct pwm_lpss_chip *pwm; + + if (!(community->features & PINCTRL_FEATURE_PWM)) + return 0; + + pwm = pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); + if (IS_ERR(pwm) && PTR_ERR(pwm) != -ENODEV) + return PTR_ERR(pwm); + + return 0; +} + int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data) { @@ -1592,6 +1617,10 @@ int intel_pinctrl_probe(struct platform_device *pdev, ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); if (ret) return ret; + + ret = intel_pinctrl_probe_pwm(pctrl, community); + if (ret) + return ret; } irq = platform_get_irq(pdev, 0);