From patchwork Thu Nov 3 07:40:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: guanjun X-Patchwork-Id: 621137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F9A9C4332F for ; Thu, 3 Nov 2022 07:40:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230435AbiKCHkw (ORCPT ); Thu, 3 Nov 2022 03:40:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230376AbiKCHkv (ORCPT ); Thu, 3 Nov 2022 03:40:51 -0400 Received: from out30-133.freemail.mail.aliyun.com (out30-133.freemail.mail.aliyun.com [115.124.30.133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A7362ADC; Thu, 3 Nov 2022 00:40:48 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R111e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046060; MF=guanjun@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VTrRND8_1667461245; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VTrRND8_1667461245) by smtp.aliyun-inc.com; Thu, 03 Nov 2022 15:40:46 +0800 From: 'Guanjun' To: herbert@gondor.apana.org.au, elliott@hpe.com Cc: zelin.deng@linux.alibaba.com, artie.ding@linux.alibaba.com, guanjun@linux.alibaba.com, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, xuchun.shang@linux.alibaba.com Subject: [PATCH v3 RESEND 1/9] crypto/ycc: Add YCC (Yitian Cryptography Complex) accelerator driver Date: Thu, 3 Nov 2022 15:40:35 +0800 Message-Id: <1667461243-48652-2-git-send-email-guanjun@linux.alibaba.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> References: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Zelin Deng YCC (Yitian Cryptography Complex) is designed to accelerate the process of encryption and decryption. Yitian is the name of Alibaba SoCs which is based on ARMv9 architecture. This patch aims to add driver with basic pci settings and irq requests. Signed-off-by: Zelin Deng Co-developed-by: Jiankang Chen Signed-off-by: Jiankang Chen Signed-off-by: Guanjun --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1 + drivers/crypto/ycc/Kconfig | 8 + drivers/crypto/ycc/Makefile | 3 + drivers/crypto/ycc/ycc_dev.h | 148 +++++++++++++++ drivers/crypto/ycc/ycc_drv.c | 444 +++++++++++++++++++++++++++++++++++++++++++ drivers/crypto/ycc/ycc_isr.c | 117 ++++++++++++ drivers/crypto/ycc/ycc_isr.h | 12 ++ 8 files changed, 735 insertions(+) create mode 100644 drivers/crypto/ycc/Kconfig create mode 100644 drivers/crypto/ycc/Makefile create mode 100644 drivers/crypto/ycc/ycc_dev.h create mode 100644 drivers/crypto/ycc/ycc_drv.c create mode 100644 drivers/crypto/ycc/ycc_isr.c create mode 100644 drivers/crypto/ycc/ycc_isr.h diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 55e75fb..f0c4aee 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -818,4 +818,6 @@ config CRYPTO_DEV_SA2UL source "drivers/crypto/keembay/Kconfig" source "drivers/crypto/aspeed/Kconfig" +source "drivers/crypto/ycc/Kconfig" + endif # CRYPTO_HW diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 116de17..a667775 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -52,4 +52,5 @@ obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/ obj-y += xilinx/ obj-y += hisilicon/ obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/ +obj-$(CONFIG_CRYPTO_DEV_YCC) += ycc/ obj-y += keembay/ diff --git a/drivers/crypto/ycc/Kconfig b/drivers/crypto/ycc/Kconfig new file mode 100644 index 00000000..6e88ecb --- /dev/null +++ b/drivers/crypto/ycc/Kconfig @@ -0,0 +1,8 @@ +config CRYPTO_DEV_YCC + tristate "Support for Alibaba YCC cryptographic accelerator" + depends on CRYPTO && CRYPTO_HW && PCI + default n + help + Enables the driver for the on-chip cryptographic accelerator of + Alibaba Yitian SoCs which is based on ARMv9 architecture. + If unsure say N. diff --git a/drivers/crypto/ycc/Makefile b/drivers/crypto/ycc/Makefile new file mode 100644 index 00000000..ef28b7c --- /dev/null +++ b/drivers/crypto/ycc/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CRYPTO_DEV_YCC) += ycc.o +ycc-objs := ycc_drv.o ycc_isr.o diff --git a/drivers/crypto/ycc/ycc_dev.h b/drivers/crypto/ycc/ycc_dev.h new file mode 100644 index 00000000..427046e --- /dev/null +++ b/drivers/crypto/ycc/ycc_dev.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __YCC_DEV_H +#define __YCC_DEV_H +#include +#include + +#define YCC_MAX_DEBUGFS_NAME 20 + +#define PCI_VENDOR_ID_YCC 0x1DED +#define PCI_DEVICE_ID_RCEC 0x8003 +#define PCI_DEVICE_ID_RCIEP 0x8001 + +#define YCC_RINGPAIR_NUM 48 +#define YCC_IRQS (YCC_RINGPAIR_NUM + 1) + +#define RING_STOP_BIT BIT(15) +#define RING_CFG_RING_SZ GENMASK(2, 0) +#define RING_CFG_INT_TH GENMASK(15, 8) +#define RING_ERR_AXI BIT(0) +#define RING_PENDING_CNT GENMASK(9, 0) + +#define YCC_SEC_CFG_BAR 0 +#define YCC_NSEC_CFG_BAR 1 +#define YCC_SEC_Q_BAR 2 +#define YCC_NSEC_Q_BAR 3 + +/* YCC secure configuration register offset */ +#define REG_YCC_CTL 0x18 +#define REG_YCC_GO 0x50 +#define REG_YCC_HCLK_INT_STATUS 0x54 +#define REG_YCC_XCLK_INT_STATUS 0x58 +#define REG_YCC_XCLK_MEM_ECC_EN_0 0x5c +#define REG_YCC_XCLK_MEM_ECC_EN_1 0x60 +#define REG_YCC_XCLK_MEM_ECC_COR_0 0x74 +#define REG_YCC_XCLK_MEM_ECC_COR_1 0x78 +#define REG_YCC_XCLK_MEM_ECC_UNCOR_0 0x80 +#define REG_YCC_XCLK_MEM_ECC_UNCOR_1 0x84 +#define REG_YCC_HCLK_MEM_ECC_EN 0x88 +#define REG_YCC_HCLK_MEM_ECC_COR 0x94 +#define REG_YCC_HCLK_MEM_ECC_UNCOR 0x98 + +#define REG_YCC_DEV_INT_MASK 0xA4 +#define REG_YCC_HCLK_INT_MASK 0xE4 +#define REG_YCC_XCLK_INT_MASK 0xE8 + +/* ring register offset */ +#define REG_RING_CMD_BASE_ADDR_LO 0x00 +#define REG_RING_CMD_BASE_ADDR_HI 0x04 +#define REG_RING_CMD_WR_PTR 0x08 +#define REG_RING_CMD_RD_PTR 0x0C +#define REG_RING_RSP_BASE_ADDR_LO 0x10 +#define REG_RING_RSP_BASE_ADDR_HI 0x14 +#define REG_RING_RSP_WR_PTR 0x18 +#define REG_RING_RSP_RD_PTR 0x1C +#define REG_RING_CFG 0x20 +#define REG_RING_TO_TH 0x24 +#define REG_RING_STATUS 0x28 +#define REG_RING_PENDING_CMD 0x2C +#define REG_RING_RSP_WR_SHADOWN_PTR 0x30 +#define REG_RING_RSP_AFULL_TH 0x34 + +#define YCC_HCLK_AHB_ERR BIT(0) +#define YCC_HCLK_SHIELD_ERR BIT(1) +#define YCC_HCLK_TRNG_ERR BIT(2) +#define YCC_HCLK_EFUSE_ERR BIT(3) +#define YCC_HCLK_INIT_ERR GENMASK(30, 16) +#define YCC_HCLK_CB_TRNG_ERR BIT(31) + +#define YCC_CTRL_IRAM_EN BIT(1) +#define YCC_CTRL_SEC_EN BIT(3) + +#define YCC_GO_PWRON BIT(0) +#define YCC_GO_ENABLED BIT(1) + +#define PCI_EXR_DEVCTL_TRP BIT(21) +#define PCI_EXP_DEVCTL_FLREN BIT(15) + +#define YDEV_STATUS_BIND 0 +#define YDEV_STATUS_INIT 1 +#define YDEV_STATUS_RESET 2 +#define YDEV_STATUS_READY 3 +#define YDEV_STATUS_ERR 4 +#define YDEV_STATUS_SRIOV 5 + +struct ycc_bar { + void __iomem *vaddr; + resource_size_t paddr; + resource_size_t size; +}; + +enum ycc_dev_type { + YCC_RCIEP, + YCC_RCEC, +}; + +struct ycc_dev { + struct list_head list; + struct pci_dev *pdev; + + u32 type; + int id; + int node; + const char *dev_name; + struct ycc_bar ycc_bars[4]; + struct ycc_dev *assoc_dev; + + bool is_polling; + unsigned long status; + struct workqueue_struct *dev_err_q; + char err_irq_name[32]; + struct work_struct work; + char *msi_name[48]; + struct dentry *debug_dir; + atomic_t refcnt; + + bool sec; + bool is_vf; + bool enable_vf; +}; + +#define YCC_CSR_WR(csr_base, csr_offset, val) \ + __raw_writel(val, csr_base + csr_offset) +#define YCC_CSR_RD(csr_base, csr_offset) \ + __raw_readl(csr_base + csr_offset) + +static inline void ycc_dev_get(struct ycc_dev *ydev) +{ + atomic_inc(&ydev->refcnt); +} + +static inline void ycc_dev_put(struct ycc_dev *ydev) +{ + atomic_dec(&ydev->refcnt); +} + +static inline void ycc_g_err_mask(void __iomem *vaddr) +{ + /* This will mask all error interrupt */ + YCC_CSR_WR(vaddr, REG_YCC_DEV_INT_MASK, (u32)~0); +} + +static inline void ycc_g_err_unmask(void __iomem *vaddr) +{ + /* This will unmask all error interrupt */ + YCC_CSR_WR(vaddr, REG_YCC_DEV_INT_MASK, 0); +} + +#endif diff --git a/drivers/crypto/ycc/ycc_drv.c b/drivers/crypto/ycc/ycc_drv.c new file mode 100644 index 00000000..4467dcd --- /dev/null +++ b/drivers/crypto/ycc/ycc_drv.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * YCC: Drivers for Alibaba YCC (Yitian Cryptography Complex) cryptographic + * accelerator. Enables the on-chip cryptographic accelerator of Alibaba + * Yitian SoCs which is based on ARMv9 architecture. + * + * Copyright (C) 2020-2022 Alibaba Corporation. All rights reserved. + * Author: Zelin Deng + * Author: Guanjun + */ + +#define pr_fmt(fmt) "YCC: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ycc_isr.h" + +static const char ycc_name[] = "ycc"; + +static bool is_polling = true; +module_param(is_polling, bool, 0644); + +LIST_HEAD(ycc_table); +static DEFINE_MUTEX(ycc_mutex); + +/* + * Each ycc device (RCIEP or RCEC) supports upto 48 VFs + * when enables SR-IOV. So each socket has 98 devices, + * includes 2 PFs and 96 VFs. + */ +#define YCC_MAX_DEVICES (98 * 4) /* Assume 4 sockets */ +static DEFINE_IDR(ycc_idr); + +static int ycc_device_flr(struct pci_dev *pdev, struct pci_dev *rcec_pdev) +{ + int ret; + + /* + * NOTE: When rciep gets FLR, its associated rcec gets reset as well. + * It does not make sense that individual pcie device should impact + * others. Before it has been fixed on silicon side, add a workaround to + * do FLR properly -- save both pci states and restore them latter. + */ + ret = pci_save_state(pdev); + if (ret) { + pr_err("Failed to save pci state\n"); + return ret; + } + + ret = pci_save_state(rcec_pdev); + if (ret) { + pr_err("Failed to save RCEC pci state\n"); + return ret; + } + + pcie_reset_flr(pdev, 0); + pcie_reset_flr(rcec_pdev, 0); + + pci_restore_state(pdev); + pci_restore_state(rcec_pdev); + + return 0; +} + +static int ycc_resource_setup(struct ycc_dev *ydev) +{ + struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev; + struct pci_dev *pdev = ydev->pdev; + struct ycc_bar *abar, *cfg_bar; + u32 hclk_status; + int ret; + + ret = ycc_device_flr(pdev, rcec_pdev); + if (ret) + return ret; + + ret = pci_request_regions(pdev, ydev->dev_name); + if (ret) { + pr_err("Failed to request RCIEP mem regions\n"); + return ret; + } + + ret = -EIO; + cfg_bar = &ydev->ycc_bars[YCC_SEC_CFG_BAR]; + cfg_bar->paddr = pci_resource_start(pdev, YCC_SEC_CFG_BAR); + cfg_bar->size = pci_resource_len(pdev, YCC_SEC_CFG_BAR); + cfg_bar->vaddr = ioremap(cfg_bar->paddr, cfg_bar->size); + if (!cfg_bar->vaddr) { + pr_err("Failed to ioremap RCIEP cfg bar\n"); + goto release_mem_regions; + } + + ycc_g_err_mask(cfg_bar->vaddr); + + YCC_CSR_WR(cfg_bar->vaddr, REG_YCC_CTL, 0|YCC_CTRL_IRAM_EN); + YCC_CSR_WR(cfg_bar->vaddr, REG_YCC_GO, 0|YCC_GO_PWRON); + + /* Waiting for ycc firmware ready, 1000ms is recommended by the HW designers */ + mdelay(1000); + if (!(YCC_CSR_RD(cfg_bar->vaddr, REG_YCC_GO) & YCC_GO_ENABLED)) { + pr_err("Failed to set ycc enabled\n"); + goto iounmap_cfg_bar; + } + + /* Check HCLK status register, some error may happen at PWRON stage */ + hclk_status = YCC_CSR_RD(cfg_bar->vaddr, REG_YCC_HCLK_INT_STATUS); + if (hclk_status & YCC_HCLK_INIT_ERR) { + pr_err("Error happened when ycc was initializing\n"); + goto iounmap_cfg_bar; + } + + abar = &ydev->ycc_bars[YCC_NSEC_Q_BAR]; + abar->paddr = pci_resource_start(pdev, YCC_NSEC_Q_BAR); + abar->size = pci_resource_len(pdev, YCC_NSEC_Q_BAR); + abar->vaddr = pci_iomap(pdev, YCC_NSEC_Q_BAR, abar->size); + if (!abar->vaddr) { + pr_err("Failed to ioremap RCIEP queue bar\n"); + goto iounmap_cfg_bar; + } + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (ret < 0) { + pr_info("Failed to set DMA bit mask 64, try 32\n"); + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret < 0) + goto iounmap_queue_bar; + } + + ret = ycc_enable_msix(ydev); + if (ret <= 0) { + pr_err("Failed to enable msix, ret: %d\n", ret); + ret = (ret == 0) ? -EINVAL : ret; + goto iounmap_queue_bar; + } + + ret = ycc_init_global_err(ydev); + if (ret) { + pr_err("Failed to enable global err\n"); + goto disable_msix; + } + + ret = ycc_alloc_irqs(ydev); + if (ret) { + pr_err("Failed to alloc irqs\n"); + goto deinit_g_err; + } + + YCC_CSR_WR(cfg_bar->vaddr, REG_YCC_HCLK_INT_STATUS, ~0); + ycc_g_err_unmask(cfg_bar->vaddr); + return 0; + +deinit_g_err: + ycc_deinit_global_err(ydev); +disable_msix: + ycc_disable_msix(ydev); +iounmap_queue_bar: + iounmap(abar->vaddr); +iounmap_cfg_bar: + iounmap(cfg_bar->vaddr); +release_mem_regions: + pci_release_regions(pdev); + return ret; +} + +static void ycc_resource_free(struct ycc_dev *ydev) +{ + ycc_deinit_global_err(ydev); + ycc_free_irqs(ydev); + ycc_disable_msix(ydev); + iounmap(ydev->ycc_bars[YCC_SEC_CFG_BAR].vaddr); + iounmap(ydev->ycc_bars[YCC_NSEC_Q_BAR].vaddr); + pci_release_regions(ydev->pdev); +} + +static inline bool ycc_rcec_match(struct pci_dev *pdev0, struct pci_dev *pdev1) +{ + return pdev0->bus->number == pdev1->bus->number; +} + +static int ycc_rcec_bind(struct ycc_dev *ydev) +{ + struct ycc_dev *assoc_dev, *rciep, *rcec; + struct list_head *itr; + int ret = 0; + + if (list_empty(&ycc_table)) + return ret; + + list_for_each(itr, &ycc_table) { + assoc_dev = list_entry(itr, struct ycc_dev, list); + /* not in the same pci bus */ + if (!ycc_rcec_match(ydev->pdev, assoc_dev->pdev)) + continue; + + /* if sriov is enabled, it could be the same */ + if (ydev == assoc_dev) + continue; + + /* if sriov is enabled, found other VFs */ + if (ydev->type == assoc_dev->type) + continue; + + /* have been bound */ + if (test_bit(YDEV_STATUS_BIND, &assoc_dev->status)) + continue; + + /* assocated device has been enabled sriov */ + if (test_bit(YDEV_STATUS_SRIOV, &assoc_dev->status)) + break; + + ydev->assoc_dev = assoc_dev; + assoc_dev->assoc_dev = ydev; + rciep = (ydev->type == YCC_RCIEP) ? ydev : ydev->assoc_dev; + rcec = rciep->assoc_dev; + + ret = sysfs_create_link(&rcec->pdev->dev.kobj, + &rciep->pdev->dev.kobj, "ycc_rciep"); + if (ret) + goto out; + + ret = sysfs_create_link(&rciep->pdev->dev.kobj, + &rcec->pdev->dev.kobj, "ycc_rcec"); + if (ret) + goto remove_rciep_link; + + ret = ycc_resource_setup(rciep); + if (ret) + goto remove_rcec_link; + + set_bit(YDEV_STATUS_READY, &rciep->status); + set_bit(YDEV_STATUS_BIND, &rciep->status); + set_bit(YDEV_STATUS_READY, &rcec->status); + set_bit(YDEV_STATUS_BIND, &rcec->status); + break; + } + + return ret; + +remove_rcec_link: + sysfs_remove_link(&rciep->pdev->dev.kobj, "ycc_rcec"); +remove_rciep_link: + sysfs_remove_link(&rcec->pdev->dev.kobj, "ycc_rciep"); +out: + return ret; +} + +static void ycc_rcec_unbind(struct ycc_dev *ydev) +{ + struct ycc_dev *rciep, *rcec; + + if (!test_bit(YDEV_STATUS_BIND, &ydev->status)) + return; + + rciep = (ydev->type == YCC_RCIEP) ? ydev : ydev->assoc_dev; + rcec = rciep->assoc_dev; + + clear_bit(YDEV_STATUS_READY, &rciep->status); + clear_bit(YDEV_STATUS_READY, &rcec->status); + clear_bit(YDEV_STATUS_BIND, &rciep->status); + clear_bit(YDEV_STATUS_BIND, &rcec->status); + sysfs_remove_link(&rcec->pdev->dev.kobj, "ycc_rciep"); + sysfs_remove_link(&rciep->pdev->dev.kobj, "ycc_rcec"); + ycc_resource_free(rciep); + rciep->assoc_dev = NULL; + rcec->assoc_dev = NULL; +} + +static int ycc_dev_add(struct ycc_dev *ydev) +{ + int ret; + + mutex_lock(&ycc_mutex); + ret = ycc_rcec_bind(ydev); + if (ret) + goto out; + list_add_tail(&ydev->list, &ycc_table); + +out: + mutex_unlock(&ycc_mutex); + return ret; +} + +static void ycc_dev_del(struct ycc_dev *ydev) +{ + mutex_lock(&ycc_mutex); + ycc_rcec_unbind(ydev); + list_del(&ydev->list); + mutex_unlock(&ycc_mutex); +} + +static inline int ycc_rciep_init(struct ycc_dev *ydev) +{ + struct pci_dev *pdev = ydev->pdev; + char name[YCC_MAX_DEBUGFS_NAME + 1]; + int idr; + + ydev->sec = false; + ydev->dev_name = ycc_name; + ydev->is_polling = is_polling; + + idr = idr_alloc(&ycc_idr, ydev, 0, YCC_MAX_DEVICES, GFP_KERNEL); + if (idr < 0) { + pr_err("Failed to allocate idr for RCIEP device\n"); + return idr; + } + + ydev->id = idr; + + snprintf(name, YCC_MAX_DEBUGFS_NAME, "ycc_%02x:%02d.%02d", + pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + ydev->debug_dir = debugfs_create_dir(name, NULL); + /* If failed to create debugfs, driver can still work */ + if (IS_ERR_OR_NULL(ydev->debug_dir)) { + pr_warn("Failed to create debugfs for RCIEP device\n"); + ydev->debug_dir = NULL; + } + + return 0; +} + +static int ycc_drv_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct ycc_dev *ydev; + struct device *dev = &pdev->dev; + int node = dev_to_node(dev); + int ret = -ENOMEM; + + ydev = kzalloc_node(sizeof(struct ycc_dev), GFP_KERNEL, node); + if (!ydev) + return ret; + + ret = pci_enable_device(pdev); + if (ret) { + pr_err("Failed to enable pci device\n"); + goto free_ydev; + } + pci_set_master(pdev); + pci_set_drvdata(pdev, ydev); + + ydev->pdev = pdev; + ydev->is_vf = false; + ydev->enable_vf = false; + ydev->node = node; + if (id->device == PCI_DEVICE_ID_RCIEP) { + ydev->type = YCC_RCIEP; + ret = ycc_rciep_init(ydev); + if (ret) + goto disable_ydev; + } else { + ydev->type = YCC_RCEC; + } + + ret = ycc_dev_add(ydev); + if (ret) + goto remove_debugfs; + + return ret; + +remove_debugfs: + if (ydev->type == YCC_RCIEP) { + debugfs_remove_recursive(ydev->debug_dir); + idr_remove(&ycc_idr, ydev->id); + } +disable_ydev: + pci_disable_device(pdev); +free_ydev: + pr_err("Failed to probe %s\n", ydev->type == YCC_RCIEP ? "RCIEP" : "RCEC"); + kfree(ydev); + return ret; +} + +static void ycc_drv_remove(struct pci_dev *pdev) +{ + struct ycc_dev *ydev = pci_get_drvdata(pdev); + + ycc_dev_del(ydev); + if (ydev->type == YCC_RCIEP) { + debugfs_remove_recursive(ydev->debug_dir); + idr_remove(&ycc_idr, ydev->id); + } + + pci_disable_sriov(pdev); + pci_disable_device(pdev); + kfree(ydev); +} + +/* + * SRIOV is not supported now. + */ +static int ycc_drv_sriov_configure(struct pci_dev *pdev, int numvfs) +{ + return -EFAULT; +} + +static const struct pci_device_id ycc_id_table[] = { + { PCI_DEVICE(PCI_VENDOR_ID_YCC, PCI_DEVICE_ID_RCIEP) }, + { PCI_DEVICE(PCI_VENDOR_ID_YCC, PCI_DEVICE_ID_RCEC) }, + { 0, } +}; +MODULE_DEVICE_TABLE(pci, ycc_id_table); + +static struct pci_driver ycc_driver = { + .name = "ycc", + .id_table = ycc_id_table, + .probe = ycc_drv_probe, + .remove = ycc_drv_remove, + .sriov_configure = ycc_drv_sriov_configure, +}; + +static int __init ycc_drv_init(void) +{ + int ret; + + ret = pci_register_driver(&ycc_driver); + if (ret) + goto out; + + return 0; + +out: + return ret; +} + +static void __exit ycc_drv_exit(void) +{ + pci_unregister_driver(&ycc_driver); +} + +module_init(ycc_drv_init); +module_exit(ycc_drv_exit); +MODULE_AUTHOR("Zelin Deng "); +MODULE_AUTHOR("Guanjun "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Driver for Alibaba YCC cryptographic accelerator"); diff --git a/drivers/crypto/ycc/ycc_isr.c b/drivers/crypto/ycc/ycc_isr.c new file mode 100644 index 00000000..f2f751c --- /dev/null +++ b/drivers/crypto/ycc/ycc_isr.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) "YCC: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ycc_isr.h" + +/* + * TODO: will implement when ycc ring actually work. + */ +static void ycc_process_global_err(struct work_struct *work) +{ +} + +static irqreturn_t ycc_g_err_isr(int irq, void *data) +{ + struct ycc_dev *ydev = (struct ycc_dev *)data; + struct ycc_bar *cfg_bar; + + if (test_and_set_bit(YDEV_STATUS_ERR, &ydev->status)) + return IRQ_HANDLED; + + /* Mask global errors until it has been processed */ + cfg_bar = &ydev->ycc_bars[YCC_SEC_CFG_BAR]; + ycc_g_err_mask(cfg_bar->vaddr); + + clear_bit(YDEV_STATUS_READY, &ydev->status); + + schedule_work(&ydev->work); + return IRQ_HANDLED; +} + +int ycc_enable_msix(struct ycc_dev *ydev) +{ + struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev; + + /* Disable intx explicitly */ + return pci_alloc_irq_vectors(rcec_pdev, YCC_IRQS, YCC_IRQS, PCI_IRQ_MSIX); +} + +void ycc_disable_msix(struct ycc_dev *ydev) +{ + struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev; + + pci_free_irq_vectors(rcec_pdev); +} + +static int ycc_setup_global_err_workqueue(struct ycc_dev *ydev) +{ + char name[32] = {0}; + + sprintf(name, "ycc_dev_%d_g_errd", ydev->id); + INIT_WORK(&ydev->work, ycc_process_global_err); + + /* Allocated, but not used temporarily */ + ydev->dev_err_q = alloc_workqueue(name, WQ_UNBOUND, 0); + if (!ydev->dev_err_q) { + pr_err("Failed to alloc workqueue for dev: %d\n", ydev->id); + return -ENOMEM; + } + + return 0; +} + +static void ycc_cleanup_global_err_workqueue(struct ycc_dev *ydev) +{ + if (ydev->dev_err_q) + destroy_workqueue(ydev->dev_err_q); +} + +/* + * TODO: Just request irq for global err. Irq for each ring + * will be requested when ring actually work. + */ +int ycc_alloc_irqs(struct ycc_dev *ydev) +{ + struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev; + int num = ydev->is_vf ? 1 : YCC_RINGPAIR_NUM; + int ret; + + sprintf(ydev->err_irq_name, "ycc_dev_%d_global_err", ydev->id); + ret = request_irq(pci_irq_vector(rcec_pdev, num), + ycc_g_err_isr, 0, ydev->err_irq_name, ydev); + if (ret) + pr_err("Failed to alloc global irq interrupt for dev: %d\n", ydev->id); + + return ret; +} + +/* + * TODO: Same as the allocate action. + */ +void ycc_free_irqs(struct ycc_dev *ydev) +{ + struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev; + int num = ydev->is_vf ? 1 : YCC_RINGPAIR_NUM; + + free_irq(pci_irq_vector(rcec_pdev, num), ydev); +} + +int ycc_init_global_err(struct ycc_dev *ydev) +{ + return ycc_setup_global_err_workqueue(ydev); +} + +void ycc_deinit_global_err(struct ycc_dev *ydev) +{ + ycc_cleanup_global_err_workqueue(ydev); +} diff --git a/drivers/crypto/ycc/ycc_isr.h b/drivers/crypto/ycc/ycc_isr.h new file mode 100644 index 00000000..8318a6f --- /dev/null +++ b/drivers/crypto/ycc/ycc_isr.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __YCC_ISR_H + +#include "ycc_dev.h" + +int ycc_enable_msix(struct ycc_dev *ydev); +void ycc_disable_msix(struct ycc_dev *ydev); +int ycc_alloc_irqs(struct ycc_dev *ydev); +void ycc_free_irqs(struct ycc_dev *ydev); +int ycc_init_global_err(struct ycc_dev *ydev); +void ycc_deinit_global_err(struct ycc_dev *ydev); +#endif From patchwork Thu Nov 3 07:40:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: guanjun X-Patchwork-Id: 621136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFC42C4332F for ; Thu, 3 Nov 2022 07:41:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231130AbiKCHlI (ORCPT ); Thu, 3 Nov 2022 03:41:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230527AbiKCHky (ORCPT ); Thu, 3 Nov 2022 03:40:54 -0400 Received: from out199-9.us.a.mail.aliyun.com (out199-9.us.a.mail.aliyun.com [47.90.199.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2218210A2; Thu, 3 Nov 2022 00:40:51 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R181e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046051; MF=guanjun@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VTrRlYo_1667461246; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VTrRlYo_1667461246) by smtp.aliyun-inc.com; Thu, 03 Nov 2022 15:40:48 +0800 From: 'Guanjun' To: herbert@gondor.apana.org.au, elliott@hpe.com Cc: zelin.deng@linux.alibaba.com, artie.ding@linux.alibaba.com, guanjun@linux.alibaba.com, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, xuchun.shang@linux.alibaba.com Subject: [PATCH v3 RESEND 2/9] crypto/ycc: Add ycc ring configuration Date: Thu, 3 Nov 2022 15:40:36 +0800 Message-Id: <1667461243-48652-3-git-send-email-guanjun@linux.alibaba.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> References: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Zelin Deng There're 2 types of functional rings, kernel ring and user ring. All kernel rings must be initialized in kernel driver while user rings are not supported now. Signed-off-by: Zelin Deng --- drivers/crypto/ycc/Makefile | 2 +- drivers/crypto/ycc/ycc_dev.h | 6 + drivers/crypto/ycc/ycc_drv.c | 59 ++++- drivers/crypto/ycc/ycc_isr.c | 7 + drivers/crypto/ycc/ycc_isr.h | 1 + drivers/crypto/ycc/ycc_ring.c | 559 ++++++++++++++++++++++++++++++++++++++++++ drivers/crypto/ycc/ycc_ring.h | 111 +++++++++ 7 files changed, 743 insertions(+), 2 deletions(-) create mode 100644 drivers/crypto/ycc/ycc_ring.c create mode 100644 drivers/crypto/ycc/ycc_ring.h diff --git a/drivers/crypto/ycc/Makefile b/drivers/crypto/ycc/Makefile index ef28b7c..31aae9c 100644 --- a/drivers/crypto/ycc/Makefile +++ b/drivers/crypto/ycc/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CRYPTO_DEV_YCC) += ycc.o -ycc-objs := ycc_drv.o ycc_isr.o +ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o diff --git a/drivers/crypto/ycc/ycc_dev.h b/drivers/crypto/ycc/ycc_dev.h index 427046e..456a53922 100644 --- a/drivers/crypto/ycc/ycc_dev.h +++ b/drivers/crypto/ycc/ycc_dev.h @@ -104,10 +104,16 @@ struct ycc_dev { struct ycc_bar ycc_bars[4]; struct ycc_dev *assoc_dev; + int max_desc; + int user_rings; bool is_polling; unsigned long status; struct workqueue_struct *dev_err_q; char err_irq_name[32]; + + struct ycc_ring *rings; + unsigned long ring_bitmap; + struct work_struct work; char *msi_name[48]; struct dentry *debug_dir; diff --git a/drivers/crypto/ycc/ycc_drv.c b/drivers/crypto/ycc/ycc_drv.c index 4467dcd..4eccd1f3 100644 --- a/drivers/crypto/ycc/ycc_drv.c +++ b/drivers/crypto/ycc/ycc_drv.c @@ -24,11 +24,16 @@ #include #include "ycc_isr.h" +#include "ycc_ring.h" static const char ycc_name[] = "ycc"; +static int max_desc = 256; +static int user_rings; static bool is_polling = true; +module_param(max_desc, int, 0644); module_param(is_polling, bool, 0644); +module_param(user_rings, int, 0644); LIST_HEAD(ycc_table); static DEFINE_MUTEX(ycc_mutex); @@ -41,6 +46,35 @@ #define YCC_MAX_DEVICES (98 * 4) /* Assume 4 sockets */ static DEFINE_IDR(ycc_idr); +static int ycc_dev_debugfs_statistics_show(struct seq_file *s, void *p) +{ + struct ycc_dev *ydev = (struct ycc_dev *)s->private; + struct ycc_ring *ring; + int i; + + seq_printf(s, "name, type, nr_binds, nr_cmds, nr_resps\n"); + for (i = 0; i < YCC_RINGPAIR_NUM; i++) { + ring = ydev->rings + i; + seq_printf(s, "Ring%02d, %d, %llu, %llu, %llu\n", ring->ring_id, + ring->type, ring->nr_binds, ring->nr_cmds, ring->nr_resps); + } + + return 0; +} + +static int ycc_dev_debugfs_statistics_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, ycc_dev_debugfs_statistics_show, inode->i_private); +} + +static const struct file_operations ycc_dev_statistics_fops = { + .open = ycc_dev_debugfs_statistics_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .owner = THIS_MODULE, +}; + static int ycc_device_flr(struct pci_dev *pdev, struct pci_dev *rcec_pdev) { int ret; @@ -136,11 +170,21 @@ static int ycc_resource_setup(struct ycc_dev *ydev) goto iounmap_queue_bar; } + /* User ring is not supported temporarily */ + ydev->user_rings = 0; + user_rings = 0; + + ret = ycc_dev_rings_init(ydev, max_desc, user_rings); + if (ret) { + pr_err("Failed to init ycc rings\n"); + goto iounmap_queue_bar; + } + ret = ycc_enable_msix(ydev); if (ret <= 0) { pr_err("Failed to enable msix, ret: %d\n", ret); ret = (ret == 0) ? -EINVAL : ret; - goto iounmap_queue_bar; + goto release_rings; } ret = ycc_init_global_err(ydev); @@ -163,12 +207,15 @@ static int ycc_resource_setup(struct ycc_dev *ydev) ycc_deinit_global_err(ydev); disable_msix: ycc_disable_msix(ydev); +release_rings: + ycc_dev_rings_release(ydev, user_rings); iounmap_queue_bar: iounmap(abar->vaddr); iounmap_cfg_bar: iounmap(cfg_bar->vaddr); release_mem_regions: pci_release_regions(pdev); + return ret; } @@ -177,6 +224,7 @@ static void ycc_resource_free(struct ycc_dev *ydev) ycc_deinit_global_err(ydev); ycc_free_irqs(ydev); ycc_disable_msix(ydev); + ycc_dev_rings_release(ydev, ydev->user_rings); iounmap(ydev->ycc_bars[YCC_SEC_CFG_BAR].vaddr); iounmap(ydev->ycc_bars[YCC_NSEC_Q_BAR].vaddr); pci_release_regions(ydev->pdev); @@ -301,12 +349,15 @@ static void ycc_dev_del(struct ycc_dev *ydev) static inline int ycc_rciep_init(struct ycc_dev *ydev) { struct pci_dev *pdev = ydev->pdev; + struct dentry *debugfs; char name[YCC_MAX_DEBUGFS_NAME + 1]; int idr; ydev->sec = false; ydev->dev_name = ycc_name; ydev->is_polling = is_polling; + ydev->user_rings = user_rings; + ydev->max_desc = max_desc; idr = idr_alloc(&ycc_idr, ydev, 0, YCC_MAX_DEVICES, GFP_KERNEL); if (idr < 0) { @@ -323,6 +374,11 @@ static inline int ycc_rciep_init(struct ycc_dev *ydev) if (IS_ERR_OR_NULL(ydev->debug_dir)) { pr_warn("Failed to create debugfs for RCIEP device\n"); ydev->debug_dir = NULL; + } else { + debugfs = debugfs_create_file("statistics", 0400, ydev->debug_dir, + (void *)ydev, &ycc_dev_statistics_fops); + if (IS_ERR_OR_NULL(debugfs)) + pr_warn("Failed to create statistics entry for RCIEP device\n"); } return 0; @@ -351,6 +407,7 @@ static int ycc_drv_probe(struct pci_dev *pdev, const struct pci_device_id *id) ydev->is_vf = false; ydev->enable_vf = false; ydev->node = node; + ydev->ring_bitmap = 0; if (id->device == PCI_DEVICE_ID_RCIEP) { ydev->type = YCC_RCIEP; ret = ycc_rciep_init(ydev); diff --git a/drivers/crypto/ycc/ycc_isr.c b/drivers/crypto/ycc/ycc_isr.c index f2f751c..cd2a2d7 100644 --- a/drivers/crypto/ycc/ycc_isr.c +++ b/drivers/crypto/ycc/ycc_isr.c @@ -38,6 +38,13 @@ static irqreturn_t ycc_g_err_isr(int irq, void *data) return IRQ_HANDLED; } +/* + * TODO: will implement when ycc ring actually work. + */ +void ycc_resp_process(uintptr_t ring_addr) +{ +} + int ycc_enable_msix(struct ycc_dev *ydev) { struct pci_dev *rcec_pdev = ydev->assoc_dev->pdev; diff --git a/drivers/crypto/ycc/ycc_isr.h b/drivers/crypto/ycc/ycc_isr.h index 8318a6f..5a25ac7 100644 --- a/drivers/crypto/ycc/ycc_isr.h +++ b/drivers/crypto/ycc/ycc_isr.h @@ -3,6 +3,7 @@ #include "ycc_dev.h" +void ycc_resp_process(uintptr_t ring_addr); int ycc_enable_msix(struct ycc_dev *ydev); void ycc_disable_msix(struct ycc_dev *ydev); int ycc_alloc_irqs(struct ycc_dev *ydev); diff --git a/drivers/crypto/ycc/ycc_ring.c b/drivers/crypto/ycc/ycc_ring.c new file mode 100644 index 00000000..ea6877e --- /dev/null +++ b/drivers/crypto/ycc/ycc_ring.c @@ -0,0 +1,559 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) "YCC: Ring: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ycc_dev.h" +#include "ycc_ring.h" +#include "ycc_isr.h" + +#define YCC_CMD_DESC_SIZE 64 +#define YCC_RESP_DESC_SIZE 16 +#define YCC_RING_CSR_STRIDE 0x1000 + +extern struct list_head ycc_table; + +static struct rb_root ring_rbtree = RB_ROOT; +static DEFINE_SPINLOCK(ring_rbtree_lock); + +/* + * Show the status of specified ring's command queue and + * response queue. + */ +static int ycc_ring_debugfs_status_show(struct seq_file *s, void *p) +{ + struct ycc_ring *ring = (struct ycc_ring *)s->private; + + seq_printf(s, "Ring ID: %d\n", ring->ring_id); + seq_printf(s, "Desscriptor Entry Size: %d, CMD Descriptor Size: %d, RESP Descriptor Size :%d\n", + ring->max_desc, YCC_CMD_DESC_SIZE, YCC_RESP_DESC_SIZE); + seq_printf(s, "CMD base addr:%llx, RESP base addr:%llx\n", + ring->cmd_base_paddr, ring->resp_base_paddr); + seq_printf(s, "CMD wr ptr:%d, CMD rd ptr: %d\n", + YCC_CSR_RD(ring->csr_vaddr, REG_RING_CMD_WR_PTR), + YCC_CSR_RD(ring->csr_vaddr, REG_RING_CMD_RD_PTR)); + seq_printf(s, "RESP rd ptr:%d, RESP wr ptr: %d\n", + YCC_CSR_RD(ring->csr_vaddr, REG_RING_RSP_RD_PTR), + YCC_CSR_RD(ring->csr_vaddr, REG_RING_RSP_WR_PTR)); + + return 0; +} + +static int ycc_ring_debugfs_status_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, ycc_ring_debugfs_status_show, inode->i_private); +} + +static const struct file_operations ycc_ring_status_fops = { + .open = ycc_ring_debugfs_status_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .owner = THIS_MODULE, +}; + +/* + * Dump the raw content of specified ring's command queue and + * response queue. + */ +static int ycc_ring_debugfs_dump_show(struct seq_file *s, void *p) +{ + struct ycc_ring *ring = (struct ycc_ring *)s->private; + + seq_printf(s, "Ring ID: %d\n", ring->ring_id); + seq_puts(s, "-------- Ring CMD Descriptors --------\n"); + seq_hex_dump(s, "", DUMP_PREFIX_ADDRESS, 32, 4, ring->cmd_base_vaddr, + YCC_CMD_DESC_SIZE * ring->max_desc, false); + seq_puts(s, "-------- Ring RESP Descriptors --------\n"); + seq_hex_dump(s, "", DUMP_PREFIX_ADDRESS, 32, 4, ring->resp_base_vaddr, + YCC_RESP_DESC_SIZE * ring->max_desc, false); + + return 0; +} + +static int ycc_ring_debugfs_dump_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, ycc_ring_debugfs_dump_show, inode->i_private); +} + +static const struct file_operations ycc_ring_dump_fops = { + .open = ycc_ring_debugfs_dump_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .owner = THIS_MODULE, +}; + +/* + * Create debugfs for rings, only for KERN_RING + * "/sys/kernel/debugfs/ycc_b:d.f/ring${x}" + */ +static int ycc_create_ring_debugfs(struct ycc_ring *ring) +{ + struct dentry *debugfs; + char name[8]; + + if (!ring || !ring->ydev || !ring->ydev->debug_dir) + return -EINVAL; + + snprintf(name, sizeof(name), "ring%02d", ring->ring_id); + debugfs = debugfs_create_dir(name, ring->ydev->debug_dir); + if (IS_ERR_OR_NULL(debugfs)) + goto out; + + ring->debug_dir = debugfs; + + debugfs = debugfs_create_file("status", 0400, ring->debug_dir, + (void *)ring, &ycc_ring_status_fops); + if (IS_ERR_OR_NULL(debugfs)) + goto remove_debugfs; + + debugfs = debugfs_create_file("dump", 0400, ring->debug_dir, + (void *)ring, &ycc_ring_dump_fops); + if (IS_ERR_OR_NULL(debugfs)) + goto remove_debugfs; + + return 0; + +remove_debugfs: + debugfs_remove_recursive(ring->debug_dir); +out: + ring->debug_dir = NULL; + return PTR_ERR(debugfs); +} + +static void ycc_remove_ring_debugfs(struct ycc_ring *ring) +{ + debugfs_remove_recursive(ring->debug_dir); +} + +/* + * Allocate memory for rings and initiate basic fields + */ +static int ycc_alloc_rings(struct ycc_dev *ydev) +{ + int num = YCC_RINGPAIR_NUM; + struct ycc_bar *abar; + u32 i; + + if (ydev->rings) + return 0; + + if (ydev->is_vf) { + num = 1; + abar = &ydev->ycc_bars[0]; + } else if (ydev->sec) { + abar = &ydev->ycc_bars[YCC_SEC_Q_BAR]; + } else { + abar = &ydev->ycc_bars[YCC_NSEC_Q_BAR]; + } + + ydev->rings = kzalloc_node(num * sizeof(struct ycc_ring), + GFP_KERNEL, ydev->node); + if (!ydev->rings) + return -ENOMEM; + + for (i = 0; i < num; i++) { + ydev->rings[i].ring_id = i; + ydev->rings[i].ydev = ydev; + ydev->rings[i].csr_vaddr = abar->vaddr + i * YCC_RING_CSR_STRIDE; + ydev->rings[i].csr_paddr = abar->paddr + i * YCC_RING_CSR_STRIDE; + } + + return 0; +} + +/* + * Free memory for rings + */ +static void ycc_free_rings(struct ycc_dev *ydev) +{ + kfree(ydev->rings); + ydev->rings = NULL; +} + +/* + * Initiate ring and create command queue and response queue. + */ +static int ycc_init_ring(struct ycc_ring *ring, u32 max_desc) +{ + struct ycc_dev *ydev = ring->ydev; + u32 cmd_ring_size, resp_ring_size; + + ring->type = KERN_RING; + ring->max_desc = max_desc; + + cmd_ring_size = ring->max_desc * YCC_CMD_DESC_SIZE; + resp_ring_size = ring->max_desc * YCC_RESP_DESC_SIZE; + + ring->cmd_base_vaddr = dma_alloc_coherent(&ydev->pdev->dev, + cmd_ring_size, + &ring->cmd_base_paddr, + GFP_KERNEL); + if (!ring->cmd_base_vaddr) { + pr_err("Failed to alloc cmd dma memory\n"); + return -ENOMEM; + } + memset(ring->cmd_base_vaddr, CMD_INVALID_CONTENT_U8, cmd_ring_size); + + ring->resp_base_vaddr = dma_alloc_coherent(&ydev->pdev->dev, + resp_ring_size, + &ring->resp_base_paddr, + GFP_KERNEL); + if (!ring->resp_base_vaddr) { + pr_err("Failed to alloc resp dma memory\n"); + dma_free_coherent(&ydev->pdev->dev, cmd_ring_size, + ring->cmd_base_vaddr, ring->cmd_base_paddr); + return -ENOMEM; + } + memset(ring->resp_base_vaddr, CMD_INVALID_CONTENT_U8, resp_ring_size); + + YCC_CSR_WR(ring->csr_vaddr, REG_RING_RSP_AFULL_TH, 0); + YCC_CSR_WR(ring->csr_vaddr, REG_RING_CMD_BASE_ADDR_LO, + (u32)ring->cmd_base_paddr & 0xffffffff); + YCC_CSR_WR(ring->csr_vaddr, REG_RING_CMD_BASE_ADDR_HI, + ((u64)ring->cmd_base_paddr >> 32) & 0xffffffff); + YCC_CSR_WR(ring->csr_vaddr, REG_RING_RSP_BASE_ADDR_LO, + (u32)ring->resp_base_paddr & 0xffffffff); + YCC_CSR_WR(ring->csr_vaddr, REG_RING_RSP_BASE_ADDR_HI, + ((u64)ring->resp_base_paddr >> 32) & 0xffffffff); + + if (ycc_create_ring_debugfs(ring)) + pr_warn("Failed to create debugfs entry for ring: %d\n", ring->ring_id); + + atomic_set(&ring->ref_cnt, 0); + spin_lock_init(&ring->lock); + return 0; +} + +/* + * Release dma memory for command queue and response queue. + */ +static void ycc_release_ring(struct ycc_ring *ring) +{ + u32 ring_size; + + /* This ring should not be in use here */ + WARN_ON(atomic_read(&ring->ref_cnt)); + + if (ring->cmd_base_vaddr) { + ring_size = ring->max_desc * YCC_CMD_DESC_SIZE; + dma_free_coherent(&ring->ydev->pdev->dev, ring_size, + ring->cmd_base_vaddr, + ring->cmd_base_paddr); + ring->cmd_base_vaddr = NULL; + } + if (ring->resp_base_vaddr) { + ring_size = ring->max_desc * YCC_RESP_DESC_SIZE; + dma_free_coherent(&ring->ydev->pdev->dev, ring_size, + ring->resp_base_vaddr, + ring->resp_base_paddr); + ring->resp_base_vaddr = NULL; + } + + ycc_remove_ring_debugfs(ring); + ring->type = FREE_RING; +} + +int ycc_dev_rings_init(struct ycc_dev *ydev, u32 max_desc, int user_rings) +{ + int kern_rings = YCC_RINGPAIR_NUM - user_rings; + struct ycc_ring *ring; + int ret, i; + + ret = ycc_alloc_rings(ydev); + if (ret) { + pr_err("Failed to allocate memory for rings\n"); + return ret; + } + + for (i = 0; i < kern_rings; i++) { + ring = &ydev->rings[i]; + ret = ycc_init_ring(ring, max_desc); + if (ret) + goto free_kern_rings; + + tasklet_init(&ring->resp_handler, ycc_resp_process, (uintptr_t)ring); + } + + return 0; + +free_kern_rings: + while (i--) { + ring = &ydev->rings[i]; + ycc_release_ring(ring); + } + + ycc_free_rings(ydev); + return ret; +} + +void ycc_dev_rings_release(struct ycc_dev *ydev, int user_rings) +{ + int kern_rings = YCC_RINGPAIR_NUM - user_rings; + struct ycc_ring *ring; + int i; + + for (i = 0; i < kern_rings; i++) { + ring = &ydev->rings[i]; + + tasklet_kill(&ring->resp_handler); + ycc_release_ring(ring); + } + + ycc_free_rings(ydev); +} + +/* + * Check if the command queue is full. + */ +static inline bool ycc_ring_full(struct ycc_ring *ring) +{ + return ring->cmd_rd_ptr == (ring->cmd_wr_ptr + 1) % ring->max_desc; +} + +/* + * Check if the response queue is empty + */ +static inline bool ycc_ring_empty(struct ycc_ring *ring) +{ + return ring->resp_rd_ptr == ring->resp_wr_ptr; +} + +#define __rb_node_to_type(a) rb_entry(a, struct ycc_ring, node) + +static inline bool ycc_ring_less(struct rb_node *a, const struct rb_node *b) +{ + return (atomic_read(&__rb_node_to_type(a)->ref_cnt) + < atomic_read(&__rb_node_to_type(b)->ref_cnt)); +} + +static struct ycc_ring *ycc_select_ring(void) +{ + struct ycc_ring *found = NULL; + struct rb_node *rnode; + struct list_head *itr; + struct ycc_dev *ydev; + int idx; + + if (list_empty(&ycc_table)) + return NULL; + + /* + * No need to protect the list through lock here. The external + * ycc_table list only insert/remove entry when probing/removing + * the driver. + */ + list_for_each(itr, &ycc_table) { + ydev = list_entry(itr, struct ycc_dev, list); + + /* RCEC has no rings */ + if (ydev->type != YCC_RCIEP) + continue; + + /* RCIEP is not ready */ + if (!test_bit(YDEV_STATUS_READY, &ydev->status)) + continue; + + do { + idx = find_first_zero_bit(&ydev->ring_bitmap, YCC_RINGPAIR_NUM); + if (idx == YCC_RINGPAIR_NUM) + break; + + found = ydev->rings + idx; + if (found->type != KERN_RING) { + /* Found ring is not for kernel, mark it and continue */ + set_bit(idx, &ydev->ring_bitmap); + continue; + } + } while (test_and_set_bit(idx, &ydev->ring_bitmap)); + + if (idx < YCC_RINGPAIR_NUM && found) + goto out; + } + + /* + * We didn't find the exact ring which means each ring + * has been occupied. Fallback to slow path. + */ + spin_lock(&ring_rbtree_lock); + rnode = rb_first(&ring_rbtree); + rb_erase(rnode, &ring_rbtree); + spin_unlock(&ring_rbtree_lock); + + found = __rb_node_to_type(rnode); + +out: + ycc_ring_get(found); + spin_lock(&ring_rbtree_lock); + rb_add(&found->node, &ring_rbtree, ycc_ring_less); + spin_unlock(&ring_rbtree_lock); + return found; +} + +/* + * Bind the ring to crypto + */ +struct ycc_ring *ycc_crypto_get_ring(void) +{ + struct ycc_ring *ring; + + ring = ycc_select_ring(); + if (ring) { + ycc_dev_get(ring->ydev); + ring->nr_binds++; + if (ring->ydev->is_polling && atomic_read(&ring->ref_cnt) == 1) + tasklet_hi_schedule(&ring->resp_handler); + } + + return ring; +} + +void ycc_crypto_free_ring(struct ycc_ring *ring) +{ + struct rb_node *rnode = &ring->node; + + spin_lock(&ring_rbtree_lock); + rb_erase(rnode, &ring_rbtree); + if (atomic_dec_and_test(&ring->ref_cnt)) { + clear_bit(ring->ring_id, &ring->ydev->ring_bitmap); + tasklet_kill(&ring->resp_handler); + } else { + rb_add(rnode, &ring_rbtree, ycc_ring_less); + } + + spin_unlock(&ring_rbtree_lock); + + ycc_dev_put(ring->ydev); +} + +/* + * Submit command to ring's command queue. + */ +int ycc_enqueue(struct ycc_ring *ring, void *cmd) +{ + int ret = 0; + + if (!ring || !ring->ydev || !cmd) + return -EINVAL; + + spin_lock_bh(&ring->lock); + if (!test_bit(YDEV_STATUS_READY, &ring->ydev->status) || ycc_ring_stopped(ring)) { + pr_debug("Enqueue error, device status: %ld, ring stopped: %d\n", + ring->ydev->status, ycc_ring_stopped(ring)); + + /* Fallback to software */ + ret = -EAGAIN; + goto out; + } + + ring->cmd_rd_ptr = YCC_CSR_RD(ring->csr_vaddr, REG_RING_CMD_RD_PTR); + if (ycc_ring_full(ring)) { + pr_debug("Enqueue error, ring %d is full\n", ring->ring_id); + ret = -EAGAIN; + goto out; + } + + memcpy(ring->cmd_base_vaddr + ring->cmd_wr_ptr * YCC_CMD_DESC_SIZE, cmd, + YCC_CMD_DESC_SIZE); + + /* Ensure that cmd_wr_ptr update after memcpy */ + dma_wmb(); + if (++ring->cmd_wr_ptr == ring->max_desc) + ring->cmd_wr_ptr = 0; + + ring->nr_cmds++; + YCC_CSR_WR(ring->csr_vaddr, REG_RING_CMD_WR_PTR, ring->cmd_wr_ptr); + +out: + spin_unlock_bh(&ring->lock); + return ret; +} + +static inline void ycc_check_cmd_state(u16 state) +{ + switch (state) { + case CMD_SUCCESS: + break; + case CMD_ILLEGAL: + pr_debug("Illegal command\n"); + break; + case CMD_UNDERATTACK: + pr_debug("Attack is detected\n"); + break; + case CMD_INVALID: + pr_debug("Invalid command\n"); + break; + case CMD_ERROR: + pr_debug("Command error\n"); + break; + case CMD_EXCESS: + pr_debug("Excess permission\n"); + break; + case CMD_KEY_ERROR: + pr_debug("Invalid internal key\n"); + break; + case CMD_VERIFY_ERROR: + pr_debug("Mac/tag verify failed\n"); + break; + default: + pr_debug("Unknown error\n"); + break; + } +} + +static void ycc_handle_resp(struct ycc_ring *ring, struct ycc_resp_desc *desc) +{ + struct ycc_flags *aflag; + + dma_rmb(); + + aflag = (struct ycc_flags *)desc->private_ptr; + if (!aflag || (u64)aflag == CMD_INVALID_CONTENT_U64) { + pr_debug("Invalid command aflag\n"); + return; + } + + ycc_check_cmd_state(desc->state); + aflag->ycc_done_callback(aflag->ptr, desc->state); + + memset(desc, CMD_INVALID_CONTENT_U8, sizeof(*desc)); + kfree(aflag); +} + +/* + * dequeue, read response descriptor + */ +void ycc_dequeue(struct ycc_ring *ring) +{ + struct ycc_resp_desc *resp; + int cnt = 0; + + if (!test_bit(YDEV_STATUS_READY, &ring->ydev->status) || ycc_ring_stopped(ring)) + return; + + ring->resp_wr_ptr = YCC_CSR_RD(ring->csr_vaddr, REG_RING_RSP_WR_PTR); + while (!ycc_ring_empty(ring)) { + resp = (struct ycc_resp_desc *)ring->resp_base_vaddr + + ring->resp_rd_ptr; + ycc_handle_resp(ring, resp); + + cnt++; + ring->nr_resps++; + if (++ring->resp_rd_ptr == ring->max_desc) + ring->resp_rd_ptr = 0; + } + + if (cnt) + YCC_CSR_WR(ring->csr_vaddr, REG_RING_RSP_RD_PTR, ring->resp_rd_ptr); +} diff --git a/drivers/crypto/ycc/ycc_ring.h b/drivers/crypto/ycc/ycc_ring.h new file mode 100644 index 00000000..eb3e6f9 --- /dev/null +++ b/drivers/crypto/ycc/ycc_ring.h @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +#ifndef __YCC_RING_H +#define __YCC_RING_H + +#include +#include + +#include "ycc_dev.h" + +#define CMD_ILLEGAL 0x15 +#define CMD_UNDERATTACK 0x25 +#define CMD_INVALID 0x35 +#define CMD_ERROR 0x45 +#define CMD_EXCESS 0x55 +#define CMD_KEY_ERROR 0x65 +#define CMD_VERIFY_ERROR 0x85 +#define CMD_SUCCESS 0xa5 +#define CMD_CANCELLED 0xff + +#define CMD_INVALID_CONTENT_U8 0x7f +#define CMD_INVALID_CONTENT_U64 0x7f7f7f7f7f7f7f7fULL + +enum ring_type { + FREE_RING, + USER_RING, + KERN_RING, + INVAL_RING, +}; + +struct ycc_ring { + u16 ring_id; + u32 status; + + struct rb_node node; + atomic_t ref_cnt; + + void __iomem *csr_vaddr; /* config register address */ + resource_size_t csr_paddr; + struct ycc_dev *ydev; /* belongs to which ydev */ + struct dentry *debug_dir; + + u32 max_desc; /* max desc entry numbers */ + u32 irq_th; + spinlock_t lock; /* used to send cmd, protect write ptr */ + enum ring_type type; + + void *cmd_base_vaddr; /* base addr of cmd ring */ + dma_addr_t cmd_base_paddr; + u16 cmd_wr_ptr; /* current cmd write pointer */ + u16 cmd_rd_ptr; /* current cmd read pointer */ + void *resp_base_vaddr; /* base addr of resp ring */ + dma_addr_t resp_base_paddr; + u16 resp_wr_ptr; /* current resp write pointer */ + u16 resp_rd_ptr; /* current resp read pointer */ + + struct tasklet_struct resp_handler; + + /* for statistics */ + u64 nr_binds; + u64 nr_cmds; + u64 nr_resps; +}; + +struct ycc_flags { + void *ptr; + int (*ycc_done_callback)(void *ptr, u16 state); +}; + +struct ycc_resp_desc { + u64 private_ptr; + u16 state; + u8 reserved[6]; +}; + +union ycc_real_cmd { + /* + * TODO: Real command will implement when + * corresponding algorithm is ready + */ + u8 padding[32]; +}; + +struct ycc_cmd_desc { + union ycc_real_cmd cmd; + u64 private_ptr; + u8 reserved0[16]; + u8 reserved1[8]; +} __packed; + +static inline void ycc_ring_get(struct ycc_ring *ring) +{ + atomic_inc(&ring->ref_cnt); +} + +static inline void ycc_ring_put(struct ycc_ring *ring) +{ + atomic_dec(&ring->ref_cnt); +} + +static inline bool ycc_ring_stopped(struct ycc_ring *ring) +{ + return !!(YCC_CSR_RD(ring->csr_vaddr, REG_RING_CFG) & RING_STOP_BIT); +} + +int ycc_enqueue(struct ycc_ring *ring, void *cmd); +void ycc_dequeue(struct ycc_ring *ring); +struct ycc_ring *ycc_crypto_get_ring(void); +void ycc_crypto_free_ring(struct ycc_ring *ring); +int ycc_dev_rings_init(struct ycc_dev *ydev, u32 max_desc, int user_rings); +void ycc_dev_rings_release(struct ycc_dev *ydev, int user_rings); +#endif From patchwork Thu Nov 3 07:40:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: guanjun X-Patchwork-Id: 621135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DFD9C4321E for ; Thu, 3 Nov 2022 07:41:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231388AbiKCHl3 (ORCPT ); Thu, 3 Nov 2022 03:41:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231295AbiKCHlI (ORCPT ); Thu, 3 Nov 2022 03:41:08 -0400 Received: from out30-42.freemail.mail.aliyun.com (out30-42.freemail.mail.aliyun.com [115.124.30.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5507F5F4F; Thu, 3 Nov 2022 00:40:55 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R751e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=guanjun@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VTrZFAS_1667461251; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VTrZFAS_1667461251) by smtp.aliyun-inc.com; Thu, 03 Nov 2022 15:40:52 +0800 From: 'Guanjun' To: herbert@gondor.apana.org.au, elliott@hpe.com Cc: zelin.deng@linux.alibaba.com, artie.ding@linux.alibaba.com, guanjun@linux.alibaba.com, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, xuchun.shang@linux.alibaba.com Subject: [PATCH v3 RESEND 5/9] crypto/ycc: Add skcipher algorithm support Date: Thu, 3 Nov 2022 15:40:39 +0800 Message-Id: <1667461243-48652-6-git-send-email-guanjun@linux.alibaba.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> References: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Guanjun Support skcipher algorithm. Signed-off-by: Guanjun --- drivers/crypto/ycc/Kconfig | 9 + drivers/crypto/ycc/Makefile | 2 +- drivers/crypto/ycc/ycc_algs.h | 114 ++++++ drivers/crypto/ycc/ycc_dev.h | 3 + drivers/crypto/ycc/ycc_drv.c | 52 +++ drivers/crypto/ycc/ycc_ring.h | 17 +- drivers/crypto/ycc/ycc_ske.c | 925 ++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 1117 insertions(+), 5 deletions(-) create mode 100644 drivers/crypto/ycc/ycc_algs.h create mode 100644 drivers/crypto/ycc/ycc_ske.c diff --git a/drivers/crypto/ycc/Kconfig b/drivers/crypto/ycc/Kconfig index 6e88ecb..8dae75e 100644 --- a/drivers/crypto/ycc/Kconfig +++ b/drivers/crypto/ycc/Kconfig @@ -2,6 +2,15 @@ config CRYPTO_DEV_YCC tristate "Support for Alibaba YCC cryptographic accelerator" depends on CRYPTO && CRYPTO_HW && PCI default n + select CRYPTO_SKCIPHER + select CRYPTO_LIB_DES + select CRYPTO_SM3_GENERIC + select CRYPTO_AES + select CRYPTO_CBC + select CRYPTO_ECB + select CRYPTO_CTR + select CRYPTO_XTS + select CRYPTO_SM4 help Enables the driver for the on-chip cryptographic accelerator of Alibaba Yitian SoCs which is based on ARMv9 architecture. diff --git a/drivers/crypto/ycc/Makefile b/drivers/crypto/ycc/Makefile index 31aae9c..eedc1c8 100644 --- a/drivers/crypto/ycc/Makefile +++ b/drivers/crypto/ycc/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CRYPTO_DEV_YCC) += ycc.o -ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o +ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o diff --git a/drivers/crypto/ycc/ycc_algs.h b/drivers/crypto/ycc/ycc_algs.h new file mode 100644 index 00000000..6c7b0dc --- /dev/null +++ b/drivers/crypto/ycc/ycc_algs.h @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +#ifndef __YCC_ALG_H +#define __YCC_ALG_H + +#include + +#include "ycc_ring.h" +#include "ycc_dev.h" + +enum ycc_gcm_mode { + YCC_AES_128_GCM = 0, + YCC_AES_192_GCM, + YCC_AES_256_GCM, + YCC_SM4_GCM, +}; + +enum ycc_ccm_mode { + YCC_AES_128_CCM = 0, + YCC_AES_192_CCM, + YCC_AES_256_CCM, + YCC_SM4_CCM, +}; + +enum ycc_ske_alg_mode { + YCC_DES_ECB = 26, + YCC_DES_CBC, + YCC_DES_CFB, + YCC_DES_OFB, + YCC_DES_CTR, /* 30 */ + + YCC_TDES_128_ECB = 31, + YCC_TDES_128_CBC, + YCC_TDES_128_CFB, + YCC_TDES_128_OFB, + YCC_TDES_128_CTR, + YCC_TDES_192_ECB, + YCC_TDES_192_CBC, + YCC_TDES_192_CFB, + YCC_TDES_192_OFB, + YCC_TDES_192_CTR, /* 40 */ + + YCC_AES_128_ECB = 41, + YCC_AES_128_CBC, + YCC_AES_128_CFB, + YCC_AES_128_OFB, + YCC_AES_128_CTR, + YCC_AES_128_XTS, /* 46 */ + + YCC_AES_192_ECB = 48, + YCC_AES_192_CBC, + YCC_AES_192_CFB, + YCC_AES_192_OFB, + YCC_AES_192_CTR, /* 52 */ + + YCC_AES_256_ECB = 55, + YCC_AES_256_CBC, + YCC_AES_256_CFB, + YCC_AES_256_OFB, + YCC_AES_256_CTR, + YCC_AES_256_XTS, /* 60 */ + + YCC_SM4_ECB = 62, + YCC_SM4_CBC, + YCC_SM4_CFB, + YCC_SM4_OFB, + YCC_SM4_CTR, + YCC_SM4_XTS, /* 67 */ +}; + +enum ycc_cmd_id { + YCC_CMD_SKE_ENC = 0x23, + YCC_CMD_SKE_DEC, +}; + +struct ycc_crypto_ctx { + struct ycc_ring *ring; + void *soft_tfm; + + u32 keysize; + u32 key_dma_size; /* dma memory size for key/key+iv */ + + u8 mode; + u8 *cipher_key; + u8 reserved[4]; +}; + +struct ycc_crypto_req { + int mapped_src_nents; + int mapped_dst_nents; + + void *key_vaddr; + dma_addr_t key_paddr; + + struct ycc_cmd_desc desc; + struct skcipher_request *ske_req; + struct skcipher_request ske_subreq; + + void *src_vaddr; + dma_addr_t src_paddr; + void *dst_vaddr; + dma_addr_t dst_paddr; + + int in_len; + int out_len; + int aad_offset; + struct ycc_crypto_ctx *ctx; + u8 last_block[16]; /* used to store iv out when decrypt */ +}; + +#define YCC_DEV(ctx) (&(ctx)->ring->ydev->pdev->dev) + +int ycc_sym_register(void); +void ycc_sym_unregister(void); +#endif diff --git a/drivers/crypto/ycc/ycc_dev.h b/drivers/crypto/ycc/ycc_dev.h index 456a53922..a758f0d 100644 --- a/drivers/crypto/ycc/ycc_dev.h +++ b/drivers/crypto/ycc/ycc_dev.h @@ -151,4 +151,7 @@ static inline void ycc_g_err_unmask(void __iomem *vaddr) YCC_CSR_WR(vaddr, REG_YCC_DEV_INT_MASK, 0); } +int ycc_algorithm_register(void); +void ycc_algorithm_unregister(void); + #endif diff --git a/drivers/crypto/ycc/ycc_drv.c b/drivers/crypto/ycc/ycc_drv.c index 4eccd1f3..f4928a9 100644 --- a/drivers/crypto/ycc/ycc_drv.c +++ b/drivers/crypto/ycc/ycc_drv.c @@ -25,6 +25,7 @@ #include "ycc_isr.h" #include "ycc_ring.h" +#include "ycc_algs.h" static const char ycc_name[] = "ycc"; @@ -35,6 +36,8 @@ module_param(is_polling, bool, 0644); module_param(user_rings, int, 0644); +static atomic_t ycc_algs_refcnt; + LIST_HEAD(ycc_table); static DEFINE_MUTEX(ycc_mutex); @@ -75,6 +78,40 @@ static int ycc_dev_debugfs_statistics_open(struct inode *inode, struct file *fil .owner = THIS_MODULE, }; +int ycc_algorithm_register(void) +{ + int ret = 0; + + /* No kernel rings */ + if (user_rings == YCC_RINGPAIR_NUM) + return ret; + + /* Only register once */ + if (atomic_inc_return(&ycc_algs_refcnt) > 1) + return ret; + + ret = ycc_sym_register(); + if (ret) + goto err; + + return 0; + +err: + atomic_dec(&ycc_algs_refcnt); + return ret; +} + +void ycc_algorithm_unregister(void) +{ + if (user_rings == YCC_RINGPAIR_NUM) + return; + + if (atomic_dec_return(&ycc_algs_refcnt)) + return; + + ycc_sym_unregister(); +} + static int ycc_device_flr(struct pci_dev *pdev, struct pci_dev *rcec_pdev) { int ret; @@ -321,6 +358,7 @@ static void ycc_rcec_unbind(struct ycc_dev *ydev) ycc_resource_free(rciep); rciep->assoc_dev = NULL; rcec->assoc_dev = NULL; + ycc_algorithm_unregister(); } static int ycc_dev_add(struct ycc_dev *ydev) @@ -421,8 +459,20 @@ static int ycc_drv_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (ret) goto remove_debugfs; + if (test_bit(YDEV_STATUS_READY, &ydev->status)) { + ret = ycc_algorithm_register(); + if (ret) { + pr_err("Failed to register algorithm\n"); + clear_bit(YDEV_STATUS_READY, &ydev->status); + clear_bit(YDEV_STATUS_READY, &ydev->assoc_dev->status); + goto dev_del; + } + } + return ret; +dev_del: + ycc_dev_del(ydev); remove_debugfs: if (ydev->type == YCC_RCIEP) { debugfs_remove_recursive(ydev->debug_dir); @@ -478,6 +528,8 @@ static int __init ycc_drv_init(void) { int ret; + atomic_set(&ycc_algs_refcnt, 0); + ret = pci_register_driver(&ycc_driver); if (ret) goto out; diff --git a/drivers/crypto/ycc/ycc_ring.h b/drivers/crypto/ycc/ycc_ring.h index 52b0fe8..6a26fd8 100644 --- a/drivers/crypto/ycc/ycc_ring.h +++ b/drivers/crypto/ycc/ycc_ring.h @@ -75,11 +75,20 @@ struct ycc_resp_desc { u8 reserved[6]; }; +struct ycc_skcipher_cmd { + u8 cmd_id; + u8 mode; + u64 sptr:48; + u64 dptr:48; + u32 dlen; + u16 key_idx; /* key used to decrypt kek */ + u8 reserved[2]; + u64 keyptr:48; + u8 padding; +} __packed; + union ycc_real_cmd { - /* - * TODO: Real command will implement when - * corresponding algorithm is ready - */ + struct ycc_skcipher_cmd ske_cmd; u8 padding[32]; }; diff --git a/drivers/crypto/ycc/ycc_ske.c b/drivers/crypto/ycc/ycc_ske.c new file mode 100644 index 00000000..9facae7 --- /dev/null +++ b/drivers/crypto/ycc/ycc_ske.c @@ -0,0 +1,925 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) "YCC: Crypto: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ycc_algs.h" + +static int ycc_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key, + unsigned int key_size, int mode, + unsigned int key_dma_size) +{ + struct ycc_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (ctx->cipher_key) { + memset(ctx->cipher_key, 0, ctx->keysize); + } else { + ctx->cipher_key = kzalloc(key_size, GFP_KERNEL); + if (!ctx->cipher_key) + return -ENOMEM; + } + memcpy(ctx->cipher_key, key, key_size); + ctx->mode = mode; + ctx->keysize = key_size; + ctx->key_dma_size = key_dma_size; + + if (ctx->soft_tfm && crypto_skcipher_setkey(ctx->soft_tfm, key, key_size)) + pr_warn("Failed to setkey for soft skcipher tfm\n"); + + return 0; +} + +#define DEFINE_YCC_SKE_AES_SETKEY(name, mode, size) \ +static int ycc_skcipher_aes_##name##_setkey(struct crypto_skcipher *tfm,\ + const u8 *key, \ + unsigned int key_size) \ +{ \ + int alg_mode; \ + switch (key_size) { \ + case AES_KEYSIZE_128: \ + alg_mode = YCC_AES_128_##mode; \ + break; \ + case AES_KEYSIZE_192: \ + alg_mode = YCC_AES_192_##mode; \ + break; \ + case AES_KEYSIZE_256: \ + alg_mode = YCC_AES_256_##mode; \ + break; \ + default: \ + return -EINVAL; \ + } \ + return ycc_skcipher_setkey(tfm, key, key_size, alg_mode, size); \ +} + +#define DEFINE_YCC_SKE_SM4_SETKEY(name, mode, size) \ +static int ycc_skcipher_sm4_##name##_setkey(struct crypto_skcipher *tfm,\ + const u8 *key, \ + unsigned int key_size) \ +{ \ + int alg_mode = YCC_SM4_##mode; \ + if (key_size != SM4_KEY_SIZE) \ + return -EINVAL; \ + return ycc_skcipher_setkey(tfm, key, key_size, alg_mode, size); \ +} + +#define DEFINE_YCC_SKE_DES_SETKEY(name, mode, size) \ +static int ycc_skcipher_des_##name##_setkey(struct crypto_skcipher *tfm,\ + const u8 *key, \ + unsigned int key_size) \ +{ \ + int alg_mode = YCC_DES_##mode; \ + int ret; \ + if (key_size != DES_KEY_SIZE) \ + return -EINVAL; \ + ret = verify_skcipher_des_key(tfm, key); \ + if (ret) \ + return ret; \ + return ycc_skcipher_setkey(tfm, key, key_size, alg_mode, size); \ +} + +#define DEFINE_YCC_SKE_3DES_SETKEY(name, mode, size) \ +static int ycc_skcipher_3des_##name##_setkey(struct crypto_skcipher *tfm,\ + const u8 *key, \ + unsigned int key_size) \ +{ \ + int alg_mode = YCC_TDES_192_##mode; \ + int ret; \ + if (key_size != DES3_EDE_KEY_SIZE) \ + return -EINVAL; \ + ret = verify_skcipher_des3_key(tfm, key); \ + if (ret) \ + return ret; \ + return ycc_skcipher_setkey(tfm, key, key_size, alg_mode, size); \ +} + +/* + * ECB: Only has 1 key, without IV, at least 32 bytes. + * Others except XTS: |key|iv|, at least 48 bytes. + */ +DEFINE_YCC_SKE_AES_SETKEY(ecb, ECB, 32); +DEFINE_YCC_SKE_AES_SETKEY(cbc, CBC, 48); +DEFINE_YCC_SKE_AES_SETKEY(ctr, CTR, 48); +DEFINE_YCC_SKE_AES_SETKEY(cfb, CFB, 48); +DEFINE_YCC_SKE_AES_SETKEY(ofb, OFB, 48); + +DEFINE_YCC_SKE_SM4_SETKEY(ecb, ECB, 32); +DEFINE_YCC_SKE_SM4_SETKEY(cbc, CBC, 48); +DEFINE_YCC_SKE_SM4_SETKEY(ctr, CTR, 48); +DEFINE_YCC_SKE_SM4_SETKEY(cfb, CFB, 48); +DEFINE_YCC_SKE_SM4_SETKEY(ofb, OFB, 48); + +DEFINE_YCC_SKE_DES_SETKEY(ecb, ECB, 32); +DEFINE_YCC_SKE_DES_SETKEY(cbc, CBC, 48); +DEFINE_YCC_SKE_DES_SETKEY(ctr, CTR, 48); +DEFINE_YCC_SKE_DES_SETKEY(cfb, CFB, 48); +DEFINE_YCC_SKE_DES_SETKEY(ofb, OFB, 48); + +DEFINE_YCC_SKE_3DES_SETKEY(ecb, ECB, 32); +DEFINE_YCC_SKE_3DES_SETKEY(cbc, CBC, 48); +DEFINE_YCC_SKE_3DES_SETKEY(ctr, CTR, 48); +DEFINE_YCC_SKE_3DES_SETKEY(cfb, CFB, 48); +DEFINE_YCC_SKE_3DES_SETKEY(ofb, OFB, 48); + +static int ycc_skcipher_aes_xts_setkey(struct crypto_skcipher *tfm, + const u8 *key, + unsigned int key_size) +{ + int alg_mode; + int ret; + + ret = xts_verify_key(tfm, key, key_size); + if (ret) + return ret; + + switch (key_size) { + case AES_KEYSIZE_128 * 2: + alg_mode = YCC_AES_128_XTS; + break; + case AES_KEYSIZE_256 * 2: + alg_mode = YCC_AES_256_XTS; + break; + default: + return -EINVAL; + } + + /* XTS: |key1|key2|iv|, at least 32 + 32 + 16 bytes */ + return ycc_skcipher_setkey(tfm, key, key_size, alg_mode, 80); +} + +static int ycc_skcipher_sm4_xts_setkey(struct crypto_skcipher *tfm, + const u8 *key, + unsigned int key_size) +{ + int alg_mode; + int ret; + + ret = xts_verify_key(tfm, key, key_size); + if (ret) + return ret; + + if (key_size != SM4_KEY_SIZE * 2) + return -EINVAL; + + alg_mode = YCC_SM4_XTS; + return ycc_skcipher_setkey(tfm, key, key_size, alg_mode, 80); +} + +static int ycc_skcipher_fill_key(struct ycc_crypto_req *req) +{ + struct ycc_crypto_ctx *ctx = req->ctx; + struct device *dev = YCC_DEV(ctx); + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req->ske_req); + u32 ivsize = crypto_skcipher_ivsize(tfm); + + if (!req->key_vaddr) { + req->key_vaddr = dma_alloc_coherent(dev, ALIGN(ctx->key_dma_size, 64), + &req->key_paddr, GFP_ATOMIC); + if (!req->key_vaddr) + return -ENOMEM; + } + + memset(req->key_vaddr, 0, ALIGN(ctx->key_dma_size, 64)); + /* XTS Mode has 2 keys & 1 iv */ + if (ctx->key_dma_size == 80) { + memcpy(req->key_vaddr + (32 - ctx->keysize / 2), + ctx->cipher_key, ctx->keysize / 2); + memcpy(req->key_vaddr + (64 - ctx->keysize / 2), + ctx->cipher_key + ctx->keysize / 2, ctx->keysize / 2); + } else { + memcpy(req->key_vaddr + (32 - ctx->keysize), ctx->cipher_key, + ctx->keysize); + } + + if (ivsize) { + if (ctx->mode == YCC_DES_ECB || + ctx->mode == YCC_TDES_128_ECB || + ctx->mode == YCC_TDES_192_ECB || + ctx->mode == YCC_AES_128_ECB || + ctx->mode == YCC_AES_192_ECB || + ctx->mode == YCC_AES_256_ECB || + ctx->mode == YCC_SM4_ECB) { + pr_err("Illegal ivsize for ECB mode, should be zero"); + goto clear_key; + } + + /* DES or 3DES */ + if (ctx->mode >= YCC_DES_ECB && ctx->mode <= YCC_TDES_192_CTR) { + if (ivsize > 8) + goto clear_key; + memcpy(req->key_vaddr + ctx->key_dma_size - 8, + req->ske_req->iv, ivsize); + } else { + memcpy(req->key_vaddr + ctx->key_dma_size - 16, + req->ske_req->iv, ivsize); + } + } + + return 0; +clear_key: + memset(req->key_vaddr, 0, ALIGN(ctx->key_dma_size, 64)); + dma_free_coherent(dev, ctx->key_dma_size, req->key_vaddr, req->key_paddr); + req->key_vaddr = NULL; + return -EINVAL; +} + +static int ycc_skcipher_sg_map(struct ycc_crypto_req *req) +{ + struct device *dev = YCC_DEV(req->ctx); + struct skcipher_request *ske_req = req->ske_req; + int src_nents; + + src_nents = sg_nents_for_len(ske_req->src, ske_req->cryptlen); + if (unlikely(src_nents <= 0)) { + pr_err("Failed to get src sg len\n"); + return -EINVAL; + } + + req->src_vaddr = dma_alloc_coherent(dev, ALIGN(req->in_len, 64), + &req->src_paddr, GFP_ATOMIC); + if (!req->src_vaddr) + return -ENOMEM; + + req->dst_vaddr = dma_alloc_coherent(dev, ALIGN(req->in_len, 64), + &req->dst_paddr, GFP_ATOMIC); + if (!req->dst_vaddr) { + dma_free_coherent(dev, ALIGN(req->in_len, 64), + req->src_vaddr, req->src_paddr); + return -ENOMEM; + } + + sg_copy_to_buffer(ske_req->src, src_nents, req->src_vaddr, ske_req->cryptlen); + return 0; +} + +static inline void ycc_skcipher_sg_unmap(struct ycc_crypto_req *req) +{ + struct device *dev = YCC_DEV(req->ctx); + + dma_free_coherent(dev, ALIGN(req->in_len, 64), req->src_vaddr, req->src_paddr); + dma_free_coherent(dev, ALIGN(req->in_len, 64), req->dst_vaddr, req->dst_paddr); +} + +/* + * For CBC & CTR + */ +static void ycc_skcipher_iv_out(struct ycc_crypto_req *req, void *dst) +{ + struct skcipher_request *ske_req = req->ske_req; + struct crypto_skcipher *stfm = crypto_skcipher_reqtfm(ske_req); + u8 bs = crypto_skcipher_blocksize(stfm); + u8 mode = req->ctx->mode; + u8 cmd = req->desc.cmd.ske_cmd.cmd_id; + u32 nb = (ske_req->cryptlen + bs - 1) / bs; + + switch (mode) { + case YCC_DES_CBC: + case YCC_TDES_128_CBC: + case YCC_TDES_192_CBC: + case YCC_AES_128_CBC: + case YCC_AES_192_CBC: + case YCC_AES_256_CBC: + case YCC_SM4_CBC: + if (cmd == YCC_CMD_SKE_DEC) + memcpy(ske_req->iv, req->last_block, bs); + else + memcpy(ske_req->iv, + (u8 *)dst + ALIGN(ske_req->cryptlen, bs) - bs, + bs); + break; + case YCC_DES_CTR: + case YCC_TDES_128_CTR: + case YCC_TDES_192_CTR: + case YCC_AES_128_CTR: + case YCC_AES_192_CTR: + case YCC_AES_256_CTR: + case YCC_SM4_CTR: + for ( ; nb-- ; ) + crypto_inc(ske_req->iv, bs); + break; + default: + return; + } +} + +static int ycc_skcipher_callback(void *ptr, u16 state) +{ + struct ycc_crypto_req *req = (struct ycc_crypto_req *)ptr; + struct skcipher_request *ske_req = req->ske_req; + struct ycc_crypto_ctx *ctx = req->ctx; + struct device *dev = YCC_DEV(ctx); + + sg_copy_from_buffer(ske_req->dst, + sg_nents_for_len(ske_req->dst, ske_req->cryptlen), + req->dst_vaddr, ske_req->cryptlen); + + if (state == CMD_SUCCESS) + ycc_skcipher_iv_out(req, req->dst_vaddr); + + ycc_skcipher_sg_unmap(req); + + if (req->key_vaddr) { + memset(req->key_vaddr, 0, ALIGN(ctx->key_dma_size, 64)); + dma_free_coherent(dev, ALIGN(ctx->key_dma_size, 64), + req->key_vaddr, req->key_paddr); + req->key_vaddr = NULL; + } + if (ske_req->base.complete) + ske_req->base.complete(&ske_req->base, + state == CMD_SUCCESS ? 0 : -EBADMSG); + + return 0; +} + +static inline bool ycc_skcipher_do_soft(struct ycc_dev *ydev) +{ + return !test_bit(YDEV_STATUS_READY, &ydev->status); +} + +static int ycc_skcipher_submit_desc(struct skcipher_request *ske_req, u8 cmd) +{ + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(ske_req); + struct ycc_crypto_req *req = skcipher_request_ctx(ske_req); + struct ycc_skcipher_cmd *ske_cmd = &req->desc.cmd.ske_cmd; + struct ycc_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + struct ycc_flags *aflags; + u8 bs = crypto_skcipher_blocksize(tfm); + int ret; + + memset(req, 0, sizeof(*req)); + req->ctx = ctx; + req->ske_req = ske_req; + req->in_len = ALIGN(ske_req->cryptlen, bs); + + /* + * The length of request, 64n + bs, may lead the device hung. + * So append one bs here. This is a workaround for hardware issue. + */ + if (req->in_len % 64 == bs) + req->in_len += bs; + + ret = ycc_skcipher_fill_key(req); + if (ret) + return ret; + + ret = ycc_skcipher_sg_map(req); + if (ret) + goto free_key; + + ret = -ENOMEM; + aflags = kzalloc(sizeof(struct ycc_flags), GFP_ATOMIC); + if (!aflags) + goto sg_unmap; + + aflags->ptr = (void *)req; + aflags->ycc_done_callback = ycc_skcipher_callback; + + req->desc.private_ptr = (u64)aflags; + ske_cmd->cmd_id = cmd; + ske_cmd->mode = ctx->mode; + ske_cmd->sptr = req->src_paddr; + ske_cmd->dptr = req->dst_paddr; + ske_cmd->dlen = req->in_len; + ske_cmd->keyptr = req->key_paddr; + ske_cmd->padding = 0; + + /* LKCF will check iv output, for decryption, the iv is its last block */ + if (cmd == YCC_CMD_SKE_DEC) + memcpy(req->last_block, + req->src_vaddr + ALIGN(ske_req->cryptlen, bs) - bs, bs); + + ret = ycc_enqueue(ctx->ring, &req->desc); + if (!ret) + return -EINPROGRESS; + + pr_debug("Failed to submit desc to ring\n"); + kfree(aflags); + +sg_unmap: + ycc_skcipher_sg_unmap(req); +free_key: + memset(req->key_vaddr, 0, ALIGN(ctx->key_dma_size, 64)); + dma_free_coherent(YCC_DEV(ctx), + ALIGN(ctx->key_dma_size, 64), + req->key_vaddr, req->key_paddr); + req->key_vaddr = NULL; + return ret; +} + +static int ycc_skcipher_encrypt(struct skcipher_request *req) +{ + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct ycc_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_request *subreq = + &((struct ycc_crypto_req *)skcipher_request_ctx(req))->ske_subreq; + + if (ycc_skcipher_do_soft(ctx->ring->ydev)) { + skcipher_request_set_tfm(subreq, ctx->soft_tfm); + skcipher_request_set_callback(subreq, req->base.flags, + req->base.complete, req->base.data); + skcipher_request_set_crypt(subreq, req->src, req->dst, + req->cryptlen, req->iv); + return crypto_skcipher_encrypt(subreq); + } + + return ycc_skcipher_submit_desc(req, YCC_CMD_SKE_ENC); +} + +static int ycc_skcipher_decrypt(struct skcipher_request *req) +{ + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); + struct ycc_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + struct skcipher_request *subreq = + &((struct ycc_crypto_req *)skcipher_request_ctx(req))->ske_subreq; + + if (ycc_skcipher_do_soft(ctx->ring->ydev)) { + skcipher_request_set_tfm(subreq, ctx->soft_tfm); + skcipher_request_set_callback(subreq, req->base.flags, + req->base.complete, req->base.data); + skcipher_request_set_crypt(subreq, req->src, req->dst, + req->cryptlen, req->iv); + return crypto_skcipher_encrypt(subreq); + } + + return ycc_skcipher_submit_desc(req, YCC_CMD_SKE_DEC); +} + +static int ycc_skcipher_init(struct crypto_skcipher *tfm) +{ + struct ycc_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + struct ycc_ring *ring; + + ctx->soft_tfm = crypto_alloc_skcipher(crypto_tfm_alg_name(crypto_skcipher_tfm(tfm)), 0, + CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_ASYNC); + if (IS_ERR(ctx->soft_tfm)) { + pr_warn("Failed to allocate soft tfm for:%s, software fallback is limited\n", + crypto_tfm_alg_name(crypto_skcipher_tfm(tfm))); + ctx->soft_tfm = NULL; + crypto_skcipher_set_reqsize(tfm, sizeof(struct ycc_crypto_req)); + } else { + /* + * If it's software fallback, store meta data of soft request. + */ + crypto_skcipher_set_reqsize(tfm, sizeof(struct ycc_crypto_req) + + crypto_skcipher_reqsize(ctx->soft_tfm)); + } + + ring = ycc_crypto_get_ring(); + if (!ring) + return -ENOMEM; + + ctx->ring = ring; + return 0; +} + +static void ycc_skcipher_exit(struct crypto_skcipher *tfm) +{ + struct ycc_crypto_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (ctx->ring) + ycc_crypto_free_ring(ctx->ring); + + kfree(ctx->cipher_key); + + if (ctx->soft_tfm) + crypto_free_skcipher((struct crypto_skcipher *)ctx->soft_tfm); +} + + +static struct skcipher_alg ycc_skciphers[] = { + { + .base = { + .cra_name = "cbc(aes)", + .cra_driver_name = "cbc-aes-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_aes_cbc_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ecb(aes)", + .cra_driver_name = "ecb-aes-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_aes_ecb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = 0, + }, + { + .base = { + .cra_name = "ctr(aes)", + .cra_driver_name = "ctr-aes-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_aes_ctr_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "cfb(aes)", + .cra_driver_name = "cfb-aes-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_aes_cfb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ofb(aes)", + .cra_driver_name = "ofb-aes-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_aes_ofb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "xts(aes)", + .cra_driver_name = "xts-aes-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_aes_xts_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE * 2, + .max_keysize = AES_MAX_KEY_SIZE * 2, + .ivsize = AES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "cbc(sm4)", + .cra_driver_name = "cbc-sm4-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = SM4_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_sm4_cbc_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = SM4_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ecb(sm4)", + .cra_driver_name = "ecb-sm4-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = SM4_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_sm4_ecb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = 0, + }, + { + .base = { + .cra_name = "ctr(sm4)", + .cra_driver_name = "ctr-sm4-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = SM4_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_sm4_ctr_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = SM4_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "cfb(sm4)", + .cra_driver_name = "cfb-sm4-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = SM4_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_sm4_cfb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = SM4_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ofb(sm4)", + .cra_driver_name = "ofb-sm4-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = SM4_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_sm4_ofb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = SM4_KEY_SIZE, + .max_keysize = SM4_KEY_SIZE, + .ivsize = SM4_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "xts(sm4)", + .cra_driver_name = "xts-sm4-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = SM4_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_sm4_xts_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = SM4_KEY_SIZE * 2, + .max_keysize = SM4_KEY_SIZE * 2, + .ivsize = SM4_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "cbc(des)", + .cra_driver_name = "cbc-des-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_des_cbc_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ecb(des)", + .cra_driver_name = "ecb-des-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_des_ecb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = 0, + }, + { + .base = { + .cra_name = "ctr(des)", + .cra_driver_name = "ctr-des-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_des_ctr_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "cfb(des)", + .cra_driver_name = "cfb-des-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_des_cfb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ofb(des)", + .cra_driver_name = "ofb-des-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_des_ofb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "cbc(des3_ede)", + .cra_driver_name = "cbc-des3_ede-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_3des_cbc_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ecb(des3_ede)", + .cra_driver_name = "ecb-des3_ede-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_3des_ecb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = 0, + }, + { + .base = { + .cra_name = "ctr(des3_ede)", + .cra_driver_name = "ctr-des3_ede-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_3des_ctr_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "cfb(des3_ede)", + .cra_driver_name = "cfb-des3_ede-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_3des_cfb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + }, + { + .base = { + .cra_name = "ofb(des3_ede)", + .cra_driver_name = "ofb-des3_ede-ycc", + .cra_priority = 4001, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct ycc_crypto_ctx), + .cra_module = THIS_MODULE, + }, + .init = ycc_skcipher_init, + .exit = ycc_skcipher_exit, + .setkey = ycc_skcipher_3des_ofb_setkey, + .encrypt = ycc_skcipher_encrypt, + .decrypt = ycc_skcipher_decrypt, + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + }, +}; + +int ycc_sym_register(void) +{ + return crypto_register_skciphers(ycc_skciphers, ARRAY_SIZE(ycc_skciphers)); +} + +void ycc_sym_unregister(void) +{ + crypto_unregister_skciphers(ycc_skciphers, ARRAY_SIZE(ycc_skciphers)); +} From patchwork Thu Nov 3 07:40:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: guanjun X-Patchwork-Id: 621134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70C06C4332F for ; Thu, 3 Nov 2022 07:42:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231244AbiKCHmL (ORCPT ); Thu, 3 Nov 2022 03:42:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231368AbiKCHl2 (ORCPT ); Thu, 3 Nov 2022 03:41:28 -0400 Received: from out30-45.freemail.mail.aliyun.com (out30-45.freemail.mail.aliyun.com [115.124.30.45]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDFA96333; Thu, 3 Nov 2022 00:40:58 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R551e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046050; MF=guanjun@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VTrTeZS_1667461254; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VTrTeZS_1667461254) by smtp.aliyun-inc.com; Thu, 03 Nov 2022 15:40:56 +0800 From: 'Guanjun' To: herbert@gondor.apana.org.au, elliott@hpe.com Cc: zelin.deng@linux.alibaba.com, artie.ding@linux.alibaba.com, guanjun@linux.alibaba.com, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, xuchun.shang@linux.alibaba.com Subject: [PATCH v3 RESEND 7/9] crypto/ycc: Add rsa algorithm support Date: Thu, 3 Nov 2022 15:40:41 +0800 Message-Id: <1667461243-48652-8-git-send-email-guanjun@linux.alibaba.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> References: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Guanjun Support rsa algorithm for ycc. That includes encryption\decryption and verification\signature Signed-off-by: Guanjun --- drivers/crypto/ycc/Makefile | 2 +- drivers/crypto/ycc/ycc_algs.h | 44 +++ drivers/crypto/ycc/ycc_drv.c | 7 + drivers/crypto/ycc/ycc_pke.c | 696 ++++++++++++++++++++++++++++++++++++++++++ drivers/crypto/ycc/ycc_ring.h | 23 ++ 5 files changed, 771 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/ycc/ycc_pke.c diff --git a/drivers/crypto/ycc/Makefile b/drivers/crypto/ycc/Makefile index d629dd5..d1f22a9 100644 --- a/drivers/crypto/ycc/Makefile +++ b/drivers/crypto/ycc/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CRYPTO_DEV_YCC) += ycc.o -ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o ycc_aead.o +ycc-objs := ycc_drv.o ycc_isr.o ycc_ring.o ycc_ske.o ycc_aead.o ycc_pke.o diff --git a/drivers/crypto/ycc/ycc_algs.h b/drivers/crypto/ycc/ycc_algs.h index e3be83ec..6a13230a 100644 --- a/drivers/crypto/ycc/ycc_algs.h +++ b/drivers/crypto/ycc/ycc_algs.h @@ -76,6 +76,13 @@ enum ycc_cmd_id { YCC_CMD_GCM_DEC, YCC_CMD_CCM_ENC, YCC_CMD_CCM_DEC, /* 0x28 */ + + YCC_CMD_RSA_ENC = 0x83, + YCC_CMD_RSA_DEC, + YCC_CMD_RSA_CRT_DEC, + YCC_CMD_RSA_CRT_SIGN, + YCC_CMD_RSA_SIGN, + YCC_CMD_RSA_VERIFY, /* 0x88 */ }; struct ycc_crypto_ctx { @@ -121,10 +128,47 @@ struct ycc_crypto_req { }; }; +#define YCC_RSA_KEY_SZ_512 64 +#define YCC_RSA_KEY_SZ_1536 192 +#define YCC_RSA_CRT_PARAMS 5 +#define YCC_RSA_E_SZ_MAX 8 +#define YCC_CMD_DATA_ALIGN_SZ 64 +#define YCC_PIN_SZ 16 + +struct ycc_pke_ctx { + struct rsa_key *rsa_key; + + void *priv_key_vaddr; + dma_addr_t priv_key_paddr; + void *pub_key_vaddr; + dma_addr_t pub_key_paddr; + + unsigned int key_len; + unsigned int e_len; + bool crt_mode; + struct ycc_ring *ring; + struct crypto_akcipher *soft_tfm; +}; + +struct ycc_pke_req { + void *src_vaddr; + dma_addr_t src_paddr; + void *dst_vaddr; + dma_addr_t dst_paddr; + + struct ycc_cmd_desc desc; + union { + struct ycc_pke_ctx *ctx; + }; + struct akcipher_request *req; +}; + #define YCC_DEV(ctx) (&(ctx)->ring->ydev->pdev->dev) int ycc_sym_register(void); void ycc_sym_unregister(void); int ycc_aead_register(void); void ycc_aead_unregister(void); +int ycc_pke_register(void); +void ycc_pke_unregister(void); #endif diff --git a/drivers/crypto/ycc/ycc_drv.c b/drivers/crypto/ycc/ycc_drv.c index b8af132..aab4419 100644 --- a/drivers/crypto/ycc/ycc_drv.c +++ b/drivers/crypto/ycc/ycc_drv.c @@ -98,8 +98,14 @@ int ycc_algorithm_register(void) if (ret) goto unregister_sym; + ret = ycc_pke_register(); + if (ret) + goto unregister_aead; + return 0; +unregister_aead: + ycc_aead_unregister(); unregister_sym: ycc_sym_unregister(); err: @@ -115,6 +121,7 @@ void ycc_algorithm_unregister(void) if (atomic_dec_return(&ycc_algs_refcnt)) return; + ycc_pke_unregister(); ycc_aead_unregister(); ycc_sym_unregister(); } diff --git a/drivers/crypto/ycc/ycc_pke.c b/drivers/crypto/ycc/ycc_pke.c new file mode 100644 index 00000000..3debd80 --- /dev/null +++ b/drivers/crypto/ycc/ycc_pke.c @@ -0,0 +1,696 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) "YCC: Crypto: " fmt + +#include +#include +#include +#include +#include +#include +#include "ycc_algs.h" + +static int ycc_rsa_done_callback(void *ptr, u16 state) +{ + struct ycc_pke_req *rsa_req = (struct ycc_pke_req *)ptr; + struct ycc_pke_ctx *ctx = rsa_req->ctx; + struct akcipher_request *req = rsa_req->req; + struct device *dev = YCC_DEV(ctx); + unsigned int dma_length = ctx->key_len; + + if (rsa_req->desc.cmd.rsa_enc_cmd.cmd_id == YCC_CMD_RSA_VERIFY) + dma_length = ctx->key_len << 1; + + /* For signature verify, dst is NULL */ + if (rsa_req->dst_vaddr) { + sg_copy_from_buffer(req->dst, sg_nents_for_len(req->dst, req->dst_len), + rsa_req->dst_vaddr, req->dst_len); + dma_free_coherent(dev, ALIGN(ctx->key_len, 64), + rsa_req->dst_vaddr, rsa_req->dst_paddr); + } + dma_free_coherent(dev, ALIGN(dma_length, 64), + rsa_req->src_vaddr, rsa_req->src_paddr); + + if (req->base.complete) + req->base.complete(&req->base, state == CMD_SUCCESS ? 0 : -EBADMSG); + + return 0; +} + +static int ycc_prepare_dma_buf(struct ycc_pke_req *rsa_req, int is_src) +{ + struct ycc_pke_ctx *ctx = rsa_req->ctx; + struct akcipher_request *req = rsa_req->req; + struct device *dev = YCC_DEV(ctx); + unsigned int dma_length = ctx->key_len; + dma_addr_t tmp; + void *ptr; + int shift; + + /* + * Ycc requires 2 key_len blocks, the first block stores + * message pre-padding with 0, the second block stores signature. + * LCKF akcipher verify, the first sg contains signature and + * the second contains message while src_len is signature + * length, dst len is message length + */ + if (rsa_req->desc.cmd.rsa_enc_cmd.cmd_id == YCC_CMD_RSA_VERIFY) { + dma_length = ctx->key_len << 1; + shift = ctx->key_len - req->dst_len; + } else { + shift = ctx->key_len - req->src_len; + } + + if (unlikely(shift < 0)) + return -EINVAL; + + ptr = dma_alloc_coherent(dev, ALIGN(dma_length, 64), &tmp, GFP_ATOMIC); + if (unlikely(!ptr)) { + pr_err("Failed to alloc dma for %s data\n", is_src ? "src" : "dst"); + return -ENOMEM; + } + + memset(ptr, 0, ALIGN(dma_length, 64)); + if (is_src) { + if (rsa_req->desc.cmd.rsa_enc_cmd.cmd_id == + YCC_CMD_RSA_VERIFY) { + /* Copy msg first with prepadding 0 */ + sg_copy_buffer(req->src, sg_nents(req->src), ptr + shift, + req->dst_len, req->src_len, 1); + /* Copy signature */ + sg_copy_buffer(req->src, sg_nents(req->src), ptr + ctx->key_len, + req->src_len, 0, 1); + } else { + sg_copy_buffer(req->src, sg_nents(req->src), ptr + shift, + req->src_len, 0, 1); + } + rsa_req->src_vaddr = ptr; + rsa_req->src_paddr = tmp; + } else { + rsa_req->dst_vaddr = ptr; + rsa_req->dst_paddr = tmp; + } + + return 0; +} + +/* + * Using public key to encrypt or verify + */ +static int ycc_rsa_submit_pub(struct akcipher_request *req, bool is_enc) +{ + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct ycc_pke_req *rsa_req = akcipher_request_ctx(req); + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + struct ycc_rsa_enc_cmd *rsa_enc_cmd; + struct ycc_ring *ring = ctx->ring; + struct device *dev = YCC_DEV(ctx); + struct ycc_flags *aflags; + int ret = -ENOMEM; + + if (req->dst_len > ctx->key_len || req->src_len > ctx->key_len) + return -EINVAL; + + rsa_req->ctx = ctx; + rsa_req->req = req; + + if (unlikely(!ctx->pub_key_vaddr)) + return -EINVAL; + + aflags = kzalloc(sizeof(struct ycc_flags), GFP_ATOMIC); + if (!aflags) + goto out; + + aflags->ptr = (void *)rsa_req; + aflags->ycc_done_callback = ycc_rsa_done_callback; + + memset(&rsa_req->desc, 0, sizeof(rsa_req->desc)); + rsa_req->desc.private_ptr = (u64)(void *)aflags; + + rsa_enc_cmd = &rsa_req->desc.cmd.rsa_enc_cmd; + rsa_enc_cmd->cmd_id = is_enc ? YCC_CMD_RSA_ENC : YCC_CMD_RSA_VERIFY; + rsa_enc_cmd->keyptr = ctx->pub_key_paddr; + rsa_enc_cmd->elen = ctx->e_len << 3; + rsa_enc_cmd->nlen = ctx->key_len << 3; + + ret = ycc_prepare_dma_buf(rsa_req, 1); + if (unlikely(ret)) + goto free_aflags; + + rsa_enc_cmd->sptr = rsa_req->src_paddr; + if (is_enc) { + ret = ycc_prepare_dma_buf(rsa_req, 0); + if (unlikely(ret)) + goto free_src; + + rsa_enc_cmd->dptr = rsa_req->dst_paddr; + } else { + rsa_req->dst_vaddr = NULL; + } + + ret = ycc_enqueue(ring, (u8 *)&rsa_req->desc); + if (!ret) + return -EINPROGRESS; + + if (rsa_req->dst_vaddr) + dma_free_coherent(dev, ALIGN(ctx->key_len, 64), + rsa_req->dst_vaddr, rsa_req->dst_paddr); + +free_src: + dma_free_coherent(dev, ALIGN(is_enc ? ctx->key_len : ctx->key_len << 1, 64), + rsa_req->src_vaddr, rsa_req->src_paddr); +free_aflags: + kfree(aflags); +out: + return ret; +} + +/* + * Using private key to decrypt or signature + */ +static int ycc_rsa_submit_priv(struct akcipher_request *req, bool is_dec) +{ + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct ycc_pke_req *rsa_req = akcipher_request_ctx(req); + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + struct ycc_rsa_dec_cmd *rsa_dec_cmd; + struct ycc_ring *ring = ctx->ring; + struct device *dev = YCC_DEV(ctx); + struct ycc_flags *aflags; + int ret = -ENOMEM; + + if (req->dst_len > ctx->key_len || req->src_len > ctx->key_len) + return -EINVAL; + + rsa_req->ctx = ctx; + rsa_req->req = req; + + if (unlikely(!ctx->priv_key_vaddr)) + return -EINVAL; + + aflags = kzalloc(sizeof(struct ycc_flags), GFP_ATOMIC); + if (!aflags) + goto out; + + aflags->ptr = (void *)rsa_req; + aflags->ycc_done_callback = ycc_rsa_done_callback; + + memset(&rsa_req->desc, 0, sizeof(rsa_req->desc)); + rsa_req->desc.private_ptr = (u64)(void *)aflags; + + rsa_dec_cmd = &rsa_req->desc.cmd.rsa_dec_cmd; + rsa_dec_cmd->keyptr = ctx->priv_key_paddr; + rsa_dec_cmd->elen = ctx->e_len << 3; + rsa_dec_cmd->nlen = ctx->key_len << 3; + if (ctx->crt_mode) + rsa_dec_cmd->cmd_id = is_dec ? YCC_CMD_RSA_CRT_DEC : YCC_CMD_RSA_CRT_SIGN; + else + rsa_dec_cmd->cmd_id = is_dec ? YCC_CMD_RSA_DEC : YCC_CMD_RSA_SIGN; + + ret = ycc_prepare_dma_buf(rsa_req, 1); + if (unlikely(ret)) + goto free_aflags; + + ret = ycc_prepare_dma_buf(rsa_req, 0); + if (unlikely(ret)) + goto free_src; + + rsa_dec_cmd->sptr = rsa_req->src_paddr; + rsa_dec_cmd->dptr = rsa_req->dst_paddr; + + ret = ycc_enqueue(ring, (u8 *)&rsa_req->desc); + if (!ret) + return -EINPROGRESS; + + dma_free_coherent(dev, ALIGN(ctx->key_len, 64), rsa_req->dst_vaddr, + rsa_req->dst_paddr); +free_src: + dma_free_coherent(dev, ALIGN(ctx->key_len, 64), rsa_req->src_vaddr, + rsa_req->src_paddr); +free_aflags: + kfree(aflags); +out: + return ret; +} + +static inline bool ycc_rsa_do_soft(struct akcipher_request *req) +{ + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + struct ycc_dev *ydev = ctx->ring->ydev; + + if (ctx->key_len == YCC_RSA_KEY_SZ_512 || + ctx->key_len == YCC_RSA_KEY_SZ_1536 || + !test_bit(YDEV_STATUS_READY, &ydev->status)) + return true; + + return false; +} + +enum rsa_ops { + RSA_ENC, + RSA_DEC, + RSA_SIGN, + RSA_VERIFY, +}; + +static inline int ycc_rsa_soft_fallback(struct akcipher_request *req, int ops) +{ + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + int ret = -EINVAL; + + akcipher_request_set_tfm(req, ctx->soft_tfm); + + switch (ops) { + case RSA_ENC: + ret = crypto_akcipher_encrypt(req); + break; + case RSA_DEC: + ret = crypto_akcipher_decrypt(req); + break; + case RSA_SIGN: + ret = crypto_akcipher_sign(req); + break; + case RSA_VERIFY: + ret = crypto_akcipher_verify(req); + break; + default: + break; + } + + akcipher_request_set_tfm(req, tfm); + return ret; +} + +static int ycc_rsa_encrypt(struct akcipher_request *req) +{ + if (ycc_rsa_do_soft(req)) + return ycc_rsa_soft_fallback(req, RSA_ENC); + + return ycc_rsa_submit_pub(req, true); +} + +static int ycc_rsa_decrypt(struct akcipher_request *req) +{ + if (ycc_rsa_do_soft(req)) + return ycc_rsa_soft_fallback(req, RSA_DEC); + + return ycc_rsa_submit_priv(req, true); +} + +static int ycc_rsa_verify(struct akcipher_request *req) +{ + if (ycc_rsa_do_soft(req)) + return ycc_rsa_soft_fallback(req, RSA_VERIFY); + + return ycc_rsa_submit_pub(req, false); +} + +static int ycc_rsa_sign(struct akcipher_request *req) +{ + if (ycc_rsa_do_soft(req)) + return ycc_rsa_soft_fallback(req, RSA_SIGN); + + return ycc_rsa_submit_priv(req, false); +} + +static int ycc_rsa_validate_n(unsigned int len) +{ + unsigned int bitslen = len << 3; + + switch (bitslen) { + case 512: + case 1024: + case 1536: + case 2048: + case 3072: + case 4096: + return 0; + default: + return -EINVAL; + } +} + +static void __ycc_rsa_drop_leading_zeros(const u8 **ptr, size_t *len) +{ + if (!*ptr) + return; + + while (!**ptr && *len) { + (*ptr)++; + (*len)--; + } +} + +static int ycc_rsa_set_n(struct ycc_pke_ctx *ctx, const char *value, + size_t value_len, bool private) +{ + const char *ptr = value; + + /* e should be set before n as we need e_len */ + if (!ctx->e_len || !value_len) + return -EINVAL; + + if (!ctx->key_len) + ctx->key_len = value_len; + + if (private && !ctx->crt_mode) + memcpy(ctx->priv_key_vaddr + ctx->e_len + YCC_PIN_SZ + + ctx->rsa_key->d_sz, ptr, value_len); + + memcpy(ctx->pub_key_vaddr + ctx->e_len, ptr, value_len); + return 0; +} + +static int ycc_rsa_set_e(struct ycc_pke_ctx *ctx, const char *value, + size_t value_len, bool private) +{ + const char *ptr = value; + + if (!ctx->key_len || !value_len || value_len > YCC_RSA_E_SZ_MAX) + return -EINVAL; + + ctx->e_len = value_len; + if (private) + memcpy(ctx->priv_key_vaddr, ptr, value_len); + + memcpy(ctx->pub_key_vaddr, ptr, value_len); + return 0; +} + +static int ycc_rsa_set_d(struct ycc_pke_ctx *ctx, const char *value, + size_t value_len) +{ + const char *ptr = value; + + if (!ctx->key_len || !value_len || value_len > ctx->key_len) + return -EINVAL; + + memcpy(ctx->priv_key_vaddr + ctx->e_len + YCC_PIN_SZ, ptr, value_len); + return 0; +} + +static int ycc_rsa_set_crt_param(char *param, size_t half_key_len, + const char *value, size_t value_len) +{ + const char *ptr = value; + size_t len = value_len; + + if (!len || len > half_key_len) + return -EINVAL; + + memcpy(param, ptr, len); + return 0; +} + +static int ycc_rsa_setkey_crt(struct ycc_pke_ctx *ctx, struct rsa_key *rsa_key) +{ + unsigned int half_key_len = ctx->key_len >> 1; + u8 *tmp = (u8 *)ctx->priv_key_vaddr; + int ret; + + tmp += ctx->rsa_key->e_sz + 16; + /* TODO: rsa_key is better to be kept original */ + ret = ycc_rsa_set_crt_param(tmp, half_key_len, rsa_key->p, rsa_key->p_sz); + if (ret) + goto err; + + tmp += half_key_len; + ret = ycc_rsa_set_crt_param(tmp, half_key_len, rsa_key->q, rsa_key->q_sz); + if (ret) + goto err; + + tmp += half_key_len; + ret = ycc_rsa_set_crt_param(tmp, half_key_len, rsa_key->dp, rsa_key->dp_sz); + if (ret) + goto err; + + tmp += half_key_len; + ret = ycc_rsa_set_crt_param(tmp, half_key_len, rsa_key->dq, rsa_key->dq_sz); + if (ret) + goto err; + + tmp += half_key_len; + ret = ycc_rsa_set_crt_param(tmp, half_key_len, rsa_key->qinv, rsa_key->qinv_sz); + if (ret) + goto err; + + ctx->crt_mode = true; + return 0; + +err: + ctx->crt_mode = false; + return ret; +} + +static void ycc_rsa_clear_ctx(struct ycc_pke_ctx *ctx) +{ + struct device *dev = YCC_DEV(ctx); + size_t size; + + if (ctx->pub_key_vaddr) { + size = ALIGN(ctx->rsa_key->e_sz + ctx->key_len, YCC_CMD_DATA_ALIGN_SZ); + dma_free_coherent(dev, size, ctx->pub_key_vaddr, ctx->pub_key_paddr); + ctx->pub_key_vaddr = NULL; + } + + if (ctx->priv_key_vaddr) { + size = ALIGN(ctx->rsa_key->e_sz + YCC_PIN_SZ + ctx->rsa_key->d_sz + + ctx->key_len, YCC_CMD_DATA_ALIGN_SZ); + memzero_explicit(ctx->priv_key_vaddr, size); + dma_free_coherent(dev, size, ctx->priv_key_vaddr, ctx->priv_key_paddr); + ctx->priv_key_vaddr = NULL; + } + + if (ctx->rsa_key) { + memzero_explicit(ctx->rsa_key, sizeof(struct rsa_key)); + kfree(ctx->rsa_key); + ctx->rsa_key = NULL; + } + + ctx->key_len = 0; + ctx->e_len = 0; + ctx->crt_mode = false; +} + +static void ycc_rsa_drop_leading_zeros(struct rsa_key *rsa_key) +{ + __ycc_rsa_drop_leading_zeros(&rsa_key->n, &rsa_key->n_sz); + __ycc_rsa_drop_leading_zeros(&rsa_key->e, &rsa_key->e_sz); + __ycc_rsa_drop_leading_zeros(&rsa_key->d, &rsa_key->d_sz); + __ycc_rsa_drop_leading_zeros(&rsa_key->p, &rsa_key->p_sz); + __ycc_rsa_drop_leading_zeros(&rsa_key->q, &rsa_key->q_sz); + __ycc_rsa_drop_leading_zeros(&rsa_key->dp, &rsa_key->dp_sz); + __ycc_rsa_drop_leading_zeros(&rsa_key->dq, &rsa_key->dq_sz); + __ycc_rsa_drop_leading_zeros(&rsa_key->qinv, &rsa_key->qinv_sz); +} + +static int ycc_rsa_alloc_key(struct ycc_pke_ctx *ctx, bool priv) +{ + struct device *dev = YCC_DEV(ctx); + struct rsa_key *rsa_key = ctx->rsa_key; + unsigned int half_key_len; + size_t size; + int ret; + + ycc_rsa_drop_leading_zeros(rsa_key); + ctx->key_len = rsa_key->n_sz; + + ret = ycc_rsa_validate_n(ctx->key_len); + if (ret) { + pr_err("Invalid n size:%d bits\n", ctx->key_len << 3); + goto out; + } + + ret = -ENOMEM; + if (priv) { + if (!(rsa_key->p_sz + rsa_key->q_sz + rsa_key->dp_sz + + rsa_key->dq_sz + rsa_key->qinv_sz)) { + size = ALIGN(rsa_key->e_sz + YCC_PIN_SZ + rsa_key->d_sz + + ctx->key_len, YCC_CMD_DATA_ALIGN_SZ); + } else { + half_key_len = ctx->key_len >> 1; + size = ALIGN(rsa_key->e_sz + YCC_PIN_SZ + half_key_len * + YCC_RSA_CRT_PARAMS, YCC_CMD_DATA_ALIGN_SZ); + ctx->crt_mode = true; + } + ctx->priv_key_vaddr = dma_alloc_coherent(dev, size, + &ctx->priv_key_paddr, + GFP_KERNEL); + if (!ctx->priv_key_vaddr) + goto out; + memset(ctx->priv_key_vaddr, 0, size); + } + + if (!ctx->pub_key_vaddr) { + size = ALIGN(ctx->key_len + rsa_key->e_sz, YCC_CMD_DATA_ALIGN_SZ); + ctx->pub_key_vaddr = dma_alloc_coherent(dev, size, + &ctx->pub_key_paddr, + GFP_KERNEL); + if (!ctx->pub_key_vaddr) + goto out; + memset(ctx->pub_key_vaddr, 0, size); + } + + ret = ycc_rsa_set_e(ctx, rsa_key->e, rsa_key->e_sz, priv); + if (ret) { + pr_err("Failed to set e for rsa %s key\n", priv ? "private" : "public"); + goto out; + } + + ret = ycc_rsa_set_n(ctx, rsa_key->n, rsa_key->n_sz, priv); + if (ret) { + pr_err("Failed to set n for rsa private key\n"); + goto out; + } + + if (priv) { + if (ctx->crt_mode) { + ret = ycc_rsa_setkey_crt(ctx, rsa_key); + if (ret) { + pr_err("Failed to set private key for rsa crt key\n"); + goto out; + } + } else { + ret = ycc_rsa_set_d(ctx, rsa_key->d, rsa_key->d_sz); + if (ret) { + pr_err("Failed to set d for rsa private key\n"); + goto out; + } + } + } + + return 0; + +out: + ycc_rsa_clear_ctx(ctx); + return ret; +} + +static int ycc_rsa_setkey(struct crypto_akcipher *tfm, const void *key, + unsigned int keylen, bool priv) +{ + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + struct rsa_key *rsa_key; + int ret; + + if (priv) + ret = crypto_akcipher_set_priv_key(ctx->soft_tfm, key, keylen); + else + ret = crypto_akcipher_set_pub_key(ctx->soft_tfm, key, keylen); + if (ret) + return ret; + + ycc_rsa_clear_ctx(ctx); + + rsa_key = kzalloc(sizeof(struct rsa_key), GFP_KERNEL); + if (!rsa_key) + return -ENOMEM; + + if (priv) + ret = rsa_parse_priv_key(rsa_key, key, keylen); + else if (!ctx->pub_key_vaddr) + ret = rsa_parse_pub_key(rsa_key, key, keylen); + if (ret) { + pr_err("Failed to parse %s key\n", priv ? "private" : "public"); + kfree(rsa_key); + return ret; + } + + ctx->rsa_key = rsa_key; + return ycc_rsa_alloc_key(ctx, priv); +} + +static int ycc_rsa_setpubkey(struct crypto_akcipher *tfm, const void *key, + unsigned int keylen) +{ + return ycc_rsa_setkey(tfm, key, keylen, false); +} + +static int ycc_rsa_setprivkey(struct crypto_akcipher *tfm, const void *key, + unsigned int keylen) +{ + return ycc_rsa_setkey(tfm, key, keylen, true); +} + +static unsigned int ycc_rsa_max_size(struct crypto_akcipher *tfm) +{ + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + + /* + * 512 and 1536 bits key size are not supported by YCC, + * we use soft tfm instead + */ + if (ctx->key_len == YCC_RSA_KEY_SZ_512 || + ctx->key_len == YCC_RSA_KEY_SZ_1536) + return crypto_akcipher_maxsize(ctx->soft_tfm); + + return ctx->rsa_key ? ctx->key_len : 0; +} + +static int ycc_rsa_init(struct crypto_akcipher *tfm) +{ + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + struct ycc_ring *ring; + + ctx->soft_tfm = crypto_alloc_akcipher("rsa-generic", 0, 0); + if (IS_ERR(ctx->soft_tfm)) { + pr_err("Can not alloc_akcipher!\n"); + return PTR_ERR(ctx->soft_tfm); + } + + /* Reserve enough space if soft request reqires additional space */ + akcipher_set_reqsize(tfm, sizeof(struct ycc_pke_req) + + crypto_akcipher_alg(ctx->soft_tfm)->reqsize); + + ring = ycc_crypto_get_ring(); + if (!ring) { + crypto_free_akcipher(ctx->soft_tfm); + return -EINVAL; + } + + ctx->ring = ring; + ctx->key_len = 0; + return 0; +} + +static void ycc_rsa_exit(struct crypto_akcipher *tfm) +{ + struct ycc_pke_ctx *ctx = akcipher_tfm_ctx(tfm); + + if (ctx->ring) + ycc_crypto_free_ring(ctx->ring); + + ycc_rsa_clear_ctx(ctx); + crypto_free_akcipher(ctx->soft_tfm); +} + +static struct akcipher_alg ycc_rsa = { + .base = { + .cra_name = "rsa", + .cra_driver_name = "rsa-ycc", + .cra_priority = 1000, + .cra_module = THIS_MODULE, + .cra_ctxsize = sizeof(struct ycc_pke_ctx), + }, + .sign = ycc_rsa_sign, + .verify = ycc_rsa_verify, + .encrypt = ycc_rsa_encrypt, + .decrypt = ycc_rsa_decrypt, + .set_pub_key = ycc_rsa_setpubkey, + .set_priv_key = ycc_rsa_setprivkey, + .max_size = ycc_rsa_max_size, + .init = ycc_rsa_init, + .exit = ycc_rsa_exit, +}; + +int ycc_pke_register(void) +{ + return crypto_register_akcipher(&ycc_rsa); +} + +void ycc_pke_unregister(void) +{ + crypto_unregister_akcipher(&ycc_rsa); +} diff --git a/drivers/crypto/ycc/ycc_ring.h b/drivers/crypto/ycc/ycc_ring.h index 1bb301b..67c7f0b 100644 --- a/drivers/crypto/ycc/ycc_ring.h +++ b/drivers/crypto/ycc/ycc_ring.h @@ -100,9 +100,32 @@ struct ycc_aead_cmd { u8 taglen; /* authenc size */ } __packed; +struct ycc_rsa_enc_cmd { + u8 cmd_id; + u64 sptr:48; + u16 key_id; + u64 keyptr:48; /* public key e+n Bytes */ + u16 elen; /* bits not byte */ + u16 nlen; + u64 dptr:48; +} __packed; + +struct ycc_rsa_dec_cmd { + u8 cmd_id; + u64 sptr:48; + u16 key_id; + u16 kek_id; + u64 keyptr:48; /* private key e + pin + d + n */ + u16 elen; /* bits not byte */ + u16 nlen; + u64 dptr:48; +} __packed; + union ycc_real_cmd { struct ycc_skcipher_cmd ske_cmd; struct ycc_aead_cmd aead_cmd; + struct ycc_rsa_enc_cmd rsa_enc_cmd; + struct ycc_rsa_dec_cmd rsa_dec_cmd; u8 padding[32]; }; From patchwork Thu Nov 3 07:40:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: guanjun X-Patchwork-Id: 621133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21C2FC4332F for ; Thu, 3 Nov 2022 07:42:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231472AbiKCHmN (ORCPT ); Thu, 3 Nov 2022 03:42:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231382AbiKCHl3 (ORCPT ); Thu, 3 Nov 2022 03:41:29 -0400 Received: from out199-7.us.a.mail.aliyun.com (out199-7.us.a.mail.aliyun.com [47.90.199.7]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C7D563D7; Thu, 3 Nov 2022 00:41:02 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R891e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046050; MF=guanjun@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0VTrcGMO_1667461258; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VTrcGMO_1667461258) by smtp.aliyun-inc.com; Thu, 03 Nov 2022 15:40:59 +0800 From: 'Guanjun' To: herbert@gondor.apana.org.au, elliott@hpe.com Cc: zelin.deng@linux.alibaba.com, artie.ding@linux.alibaba.com, guanjun@linux.alibaba.com, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, xuchun.shang@linux.alibaba.com Subject: [PATCH v3 RESEND 9/9] MAINTAINERS: Add Yitian Cryptography Complex (YCC) driver maintainer entry Date: Thu, 3 Nov 2022 15:40:43 +0800 Message-Id: <1667461243-48652-10-git-send-email-guanjun@linux.alibaba.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> References: <1667461243-48652-1-git-send-email-guanjun@linux.alibaba.com> Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Zelin Deng I will continue to add new feature, optimize the performance, and handle the issues of Yitian Cryptography Complex (YCC) driver. Guanjun and Xuchun Shang focus on various algorithms support, add them as co-maintainers. Signed-off-by: Zelin Deng Acked-by: Guanjun Acked-by: Xuchun Shang --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9774e7b..5975c1b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -953,6 +953,14 @@ S: Supported F: drivers/crypto/ccp/sev* F: include/uapi/linux/psp-sev.h +ALIBABA YITIAN CRYPTOGRAPHY COMPLEX (YCC) ACCELERATOR DRIVER +M: Zelin Deng +M: Guanjun +M: Xuchun Shang +L: ali-accel@list.alibaba-inc.com +S: Supported +F: drivers/crypto/ycc/ + AMD DISPLAY CORE M: Harry Wentland M: Leo Li