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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:19 -0800 Message-Id: <20190307170440.3113-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 01/22] target/arm: Add MTE_ACTIVE to tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE, then arrange to perform the check while stripping the TBI. The check is not yet implemented, just the plumbing to that point. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Clean TBI bits exactly. Fix license to lgpl 2.1. v3: Remove stub helper_mte_check; moved to a later patch. --- target/arm/cpu.h | 12 +++++++++ target/arm/internals.h | 18 ++++++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 51 ++++++++++++++++++++++++++++++-------- target/arm/translate-a64.c | 1 + 5 files changed, 73 insertions(+), 11 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5f23c62132..0cf9eacebe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1214,6 +1214,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3127,6 +3128,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 14, 1) static inline bool bswap_code(bool sctlr_b) { @@ -3507,6 +3509,16 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; } +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..6c018e773c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -983,4 +983,22 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr != 0; +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index 912cc2a4a5..e07c2c3330 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -70,6 +70,8 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE tag checks affect the PE. */ + bool mte_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 2607d39ad1..90d15578ca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1863,6 +1863,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= SCR_ATA; + } /* Clear all-context RES0 bits. */ value &= valid_mask; @@ -4050,22 +4053,31 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = arm_env_get_cpu(env); - if (raw_read(env, ri) == value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { /* M bit is RAZ/WI for PMSA with no MPU implemented */ value &= ~SCTLR_M; } - raw_write(env, ri, value); + if (!cpu_isar_feature(aa64_mte, cpu)) { + if (ri->opc1 == 6) { /* SCTLR_EL3 */ + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); + + if (raw_read(env, ri) != value) { + /* + * This may enable/disable the MMU, so do a TLB flush. + * Skip the TLB flush if nothing actually changed; + * Linux likes to do a lot of pointless SCTLR writes. + */ + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4561,6 +4573,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= HCR_API | HCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= HCR_ATA; + } /* Clear RES0 bits. */ value &= valid_mask; @@ -12869,6 +12884,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); uint64_t sctlr; + int tbid; *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -12877,7 +12893,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; + int tbii; /* FIXME: ARMv8.1-VHE S2 translation regime. */ if (regime_el(env, stage1) < 2) { @@ -12930,6 +12946,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + + /* + * If MTE is enabled, and tag checks affect the PE, + * then we check the tag as we strip the TBI field. + * Note that if TBI is disabled, all accesses are unchecked. + */ + if (tbid + && cpu_isar_feature(aa64_mte, cpu) + && allocation_tag_access_enabled(env, current_el, sctlr) + && !(env->pstate & PSTATE_TCO) + && (sctlr & (current_el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1959046343..d971b57037 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14351,6 +14351,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->mte_active = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Thu Mar 7 17:04:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159894 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7673540jad; Thu, 7 Mar 2019 09:09:27 -0800 (PST) X-Google-Smtp-Source: APXvYqzOZ4b+hYRjB88OvYRA32D0ZKepiPkbQSUT4LHemur8KUeMC83tNn3qXZ/11a9TzBaar69I X-Received: by 2002:a5b:989:: with SMTP id c9mr12086322ybq.47.1551978567710; Thu, 07 Mar 2019 09:09:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978567; cv=none; d=google.com; s=arc-20160816; b=kmXDdHV4YphoQSZSdD6+boG7ELFwm4rGFRrPsec/nMHM66zvzc9edIXGXEw7JBgiYs fAGjyN+WwIFyUehvP+HBb56E5N2TZlO4lxog0fJDN8HEItt3DDxrJnLMJCyR255h5Sfh cdKiJTQANYYxN3sR/KuavPa/TN/uxoL/hPnrC9QF1TRhQRUGmKmchpTjN4Fs9MlzlTOX KQaywY+lg68HMHlHuVYbiwO3BlUskrdi6KeA5S6F0hh1kuGDX2jAeMVl0o8+wt2NLQCB hWfojfPBkT5UG743sxfDbOjiYjH5P4Xk2pwJzZfP6xY0MC36vEmfIoMFkHzaeplGn1qG iRww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=G3hGr7nsLX8r/HzFuX2/VbjTSq7xNhp+OIN31NWN5vY=; b=lkB82fjnfseLrv4Tx+lADh/7AGZcFguE/JaxDHbFNbzybtlSTxfWSw/Y907wGWRH77 x0ms4vtKZYasdoduADM5vcqRe+ACx/t8kurG+GyH/R9SeU15A15kkiQ0a2kmn6R8BzjR Fomwk9fd7RuPh1/YmUR7ipS6RhfYYrKg5YvndW3N9hVz0L0Ec8D389um3Mwe7x9XqfwN E1p/SXER11dd+8CPrfFn+IE9KJkbu9gNad/QPQMojVLd23aW3xh5oVeSymW9ZoOnX5f5 2sU7lboqaHea0VNe65dDR/zJdF6UdqS/1hy8tlVF18/uA9wE8cJRcINkzV2HOsQ60xBH 0xGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xYyRjz3D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 02/22] target/arm: Extract TCMA with ARMVAParameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c018e773c..2922324f63 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -959,6 +959,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; diff --git a/target/arm/helper.c b/target/arm/helper.c index 90d15578ca..ab8006291b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10599,7 +10599,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; /* @@ -10614,11 +10614,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi = tbid = hpd = false; + tbi = tbid = hpd = tcma = false; } else { tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); tbid = extract32(tcr, 29, 1); + tcma = extract32(tcr, 30, 1); } epd = false; } else if (!select) { @@ -10629,6 +10630,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); tbid = extract64(tcr, 51, 1); + tcma = extract64(tcr, 57, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; @@ -10638,6 +10640,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); tbid = extract64(tcr, 52, 1); + tcma = extract64(tcr, 58, 1); } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -10649,6 +10652,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, .tbid = tbid, .epd = epd, .hpd = hpd, + .tcma = tcma, .using16k = using16k, .using64k = using64k, }; From patchwork Thu Mar 7 17:04:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159893 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7672645jad; Thu, 7 Mar 2019 09:08:44 -0800 (PST) X-Google-Smtp-Source: APXvYqyZbBlGpEKr0n5uGB7Dc5sQoA8sfg/FeyFqknYvwpIPqzmRLQHhHt6vmAsNUSSoBP/xCW54 X-Received: by 2002:a81:a196:: with SMTP id y144mr11060363ywg.270.1551978524407; Thu, 07 Mar 2019 09:08:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978524; cv=none; d=google.com; s=arc-20160816; b=IF1MC6T4q75vFnVMoB9clWuXk7xXJ/nDbq3xU/7CuXtRf2P+jMP4lJWQABvw4JVflq Aa5ZkDV531nf3vh2p9cOH7rKys8Q8hRac2AmwXBfSFPPFcH/MqoMSSlZ6N4RT08HBjA5 v0+ft+odMoULR/0PMcTq2fUPXak+43+hGZ9LUoUkiB3kBCcEWO5g1/u4rsUnmzrN4h61 DlUZcsXp9VlW+Ng3Fy5MqNxDssds36bW+u9n6rHHEfuOlWA4EikRo+bUvsB4yVttlb79 N4irKn+O+jKY9P097KQ/7tagK28PiE5tFUPGTPNhFcf8FHwZ5M/f5ZP863D/YevLnWRg V9kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=O5uY6lTEl2e1lbjggWAv4dvfwd54ah51eZXdZW99lJw=; b=dLXaDs5fT0zq7cc75eN2AYydPr0mOIXpdfJDtcBeIbOTr5+Q1P6xK1D22zsqWkMtRh Mrm9kLsAuTZuDCU4fBgDirAYfJVItFwTRL/9NMrY0aOgOXFCfncjmD1av34UKM+s2vos sDj2Bm46Bu8oQJBk3guNgaG5ScNeoV1hA+Yqp7W9XxeyTAx0OBHOH+C7CgNdGxw7OiEs W3B4aFqB/7iRaAfMgoGfk4IupxjQeT0HLEpl5E1DmFAM0XTYkF+zxnw5TlFDV2h8E9nI jcqO/8wfAXnJWOZJ0H8oGnGV1U0nIe1oTZw7xVaMLmy1aeYm2ehurW7+SoQNJDWA+i5S 9sbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZknBlb9q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:21 -0800 Message-Id: <20190307170440.3113-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 03/22] target/arm: Add MTE system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- v3: Add GMID; add access_mte. --- target/arm/cpu.h | 3 ++ target/arm/internals.h | 6 ++++ target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 +++++++ 4 files changed, 86 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0cf9eacebe..b9b33bc285 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -495,6 +495,9 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; } cp15; struct { diff --git a/target/arm/internals.h b/target/arm/internals.h index 2922324f63..fbfa770c23 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,4 +1002,10 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, return sctlr != 0; } +/* + * The log2 of the words in the tag block, for GMID_EL1.BS. + * The is the maximum, 256 bytes, which manipulates 64-bits of tags. + */ +#define GMID_EL1_BS 6 + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index ab8006291b..7b30e1a1a9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5732,6 +5732,69 @@ static const ARMCPRegInfo pauth_reginfo[] = { .fieldoffset = offsetof(CPUARMState, apib_key.hi) }, REGINFO_SENTINEL }; + +static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ATA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) +{ + env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] = { + { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 6, .opc2 = 1, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL2_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 6, .opc2 = 0, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, + { .name = "TCO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, + .type = ARM_CP_NO_RAW, + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + REGINFO_SENTINEL +}; #endif static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6676,6 +6739,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d971b57037..128b7f2e32 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1746,6 +1746,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_UPDATE; break; + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s); From patchwork Thu Mar 7 17:04:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159890 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7668606jad; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:22 -0800 Message-Id: <20190307170440.3113-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH v4 04/22] target/arm: Add helper_mte_check{1, 2} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already implied by TB_FLAGS_MTE_ACTIVE. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- v2: Fix TFSR update. v3: Split helper_mte_check per {1,2} IAs; take tbi data from translate. --- target/arm/helper-a64.h | 3 + target/arm/mte_helper.c | 133 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 14 +++- target/arm/Makefile.objs | 2 +- 4 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 target/arm/mte_helper.c -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..c88797a922 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,6 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 0000000000..bcd82a9be0 --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,133 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ + return extract64(ptr, 56, 4); +} + +/* + * Perform a checked access for MTE. + * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. + */ +static uint64_t do_mte_check(CPUARMState *env, uint64_t dirty_ptr, + uint64_t clean_ptr, uint32_t select, + uintptr_t ra) +{ + int ptr_tag, mem_tag; + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules R0076 & R0077 are written with logical tags, + * and we need the physical tag below anyway. + */ + ptr_tag = allocation_tag_from_addr(dirty_ptr); + if (ptr_tag == 0) { + ARMMMUIdx stage1 = arm_stage1_mmu_idx(env); + ARMVAParameters p = aa64_va_parameters(env, dirty_ptr, stage1, true); + if (p.tcma) { + return clean_ptr; + } + } + + /* + * If an access is made to an address that does not provide tag storage, + * the result is implementation defined (R0006). We choose to treat the + * access as unchecked. + * This is similar to MemAttr != Tagged, which are also unchecked. + */ + mem_tag = get_allocation_tag(env, clean_ptr, ra); + if (mem_tag < 0) { + return clean_ptr; + } + + /* If the tags do not match, the tag check operation fails. */ + if (unlikely(ptr_tag != mem_tag)) { + int tcf, el = arm_current_el(env); + + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + tcf = extract64(env->cp15.sctlr_el[1], 38, 2); + } else { + tcf = extract64(env->cp15.sctlr_el[el], 40, 2); + } + if (tcf == 1) { + /* + * Tag check fail causes a synchronous exception. + * + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(ENV_GET_CPU(env), ra, true); + env->exception.vaddress = dirty_ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11), + exception_target_el(env)); + } else if (tcf == 2) { + /* Tag check fail causes asynchronous flag set. */ + env->cp15.tfsr_el[el] |= 1 << select; + } + } + + return clean_ptr; +} + +/* + * Perform check in translation regime w/single IA range. + * It is known that TBI is enabled on entry. + */ +uint64_t HELPER(mte_check1)(CPUARMState *env, uint64_t dirty_ptr) +{ + uint64_t clean_ptr = extract64(dirty_ptr, 0, 56); + return do_mte_check(env, dirty_ptr, clean_ptr, 0, GETPC()); +} + +/* + * Perform check in translation regime w/two IA ranges. + * The TBI argument is the concatenation of TBI1:TBI0. We have filtered + * TBI==0, but still need to check the IA range being referenced. + */ +uint64_t HELPER(mte_check2)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) +{ + uint32_t select = extract64(dirty_ptr, 55, 1); + + if ((tbi >> select) & 1) { + uint64_t clean_ptr = sextract64(dirty_ptr, 0, 56); + return do_mte_check(env, dirty_ptr, clean_ptr, select, GETPC()); + } else { + /* TBI is disabled; the access is unchecked. */ + return dirty_ptr; + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 128b7f2e32..6ec77fc67c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -343,7 +343,19 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean = new_tmp_a64(s); - gen_top_byte_ignore(s, clean, addr, s->tbid); + + if (s->mte_active) { + if (s->current_el >= 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + gen_helper_mte_check1(clean, cpu_env, addr); + } else { + TCGv_i32 tbi = tcg_const_i32(s->tbid); + gen_helper_mte_check2(clean, cpu_env, addr, tbi); + tcg_temp_free_i32(tbi); + } + } else { + gen_top_byte_ignore(s, clean, addr, s->tbid); + } return clean; } diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 6bdcc65c2c..c22cbc5567 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,7 +8,7 @@ obj-y += translate.o op_helper.o helper.o cpu.o obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o vfp_helper.o obj-y += gdbstub.o obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-$(TARGET_AARCH64) += pauth_helper.o +obj-$(TARGET_AARCH64) += pauth_helper.o mte_helper.o obj-y += crypto_helper.o obj-$(CONFIG_SOFTMMU) += arm-powerctl.o From patchwork Thu Mar 7 17:04:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159898 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7679844jad; Thu, 7 Mar 2019 09:14:42 -0800 (PST) X-Google-Smtp-Source: APXvYqwwF6jLFbVZPKWL8tDbRlZLqGS6Jv+io6XJXa2a3bX9Pl5VBoifv5EJ12VFgdzTmrpLGgnV X-Received: by 2002:a81:2c89:: with SMTP id s131mr10555675yws.64.1551978881805; Thu, 07 Mar 2019 09:14:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978881; cv=none; d=google.com; s=arc-20160816; b=f7Pg04Ee/j3wG9H2ZeO295on+f+3feV2PgO6TGcghJrC6I6ktyn7dNsNhnIrL31e+4 bwYc8iHzDGTJ5mCwi+3s2XLaMD8Jq1h192aUHlxeWlLIvCWQe8wHHjRFelxKOo0togPK UVII6mP2pnhzyzTb4ztnB16RNFT1//XWVUvXVOE+P2Y/MDpU70xS4plYM/MEyxrk0V5y 8ZZTOYPhZeX9fbZrehREYqgg7ggLBWJcNJE1X1LchJXbIz/C+qjK2Vh3vcxq1E2X72a2 Hv2pPhjsKTLE3muAQhnJdlYn8fSp71aj8K7FIRaeemvWsf+ThVvuqRhQtf9LTilSaMZn p2bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RbkXrsv19E2YAEIvT8x8QaVcLAnqxFUL0bdiWTfxaWg=; b=q0enxFX+umMLagz6TwtNV+3Zw2ez9GjR+fyROQz5fYshEk/10ceArFXgH4Tuq7XTwI bH3sGTL9XKylF2kWzrRVz5V8l3I2B0pEyLae+RWJaWRvfTv8bwZpVSFGuO7FQkmr6iVB 6ILWMrpxIVhDYLcrLaiBxgHUzxAH8HZZDpVG0C1R5AshUq+sR6N4cc6QxZ25AzzdZ3RD 9a1LgdH2OYDK6KFrnqGPFgXwyf4k5dzVJPlV82jxc2W5f2clJOq2Dx6VblffNA2qoeYa XPrXv/upTS+x9IzLmcXEMDS//2gjgeW+twqYRvwV9UV+c52G181rpVk7riApH/+hIsdb Vlrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="XP/bbCZh"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:23 -0800 Message-Id: <20190307170440.3113-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v4 05/22] target/arm: Suppress tag check for sp+offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0078 specifies that base register, or base register plus immediate offset, is unchecked when the base register is SP. Signed-off-by: Richard Henderson --- v2: Include writeback addresses as checked. --- target/arm/translate-a64.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6ec77fc67c..0d35c07504 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -340,11 +340,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) * This is always a fresh temporary, as we need to be able to * increment this independently of a dirty write-back address. */ -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool check) { TCGv_i64 clean = new_tmp_a64(s); - if (s->mte_active) { + if (check && s->mte_active) { if (s->current_el >= 2) { /* FIXME: ARMv8.1-VHE S2 translation regime. */ gen_helper_mte_check1(clean, cpu_env, addr); @@ -2464,7 +2464,7 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2482,7 +2482,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); if (size == 2) { TCGv_i64 cmp = tcg_temp_new_i64(); @@ -2607,7 +2607,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; @@ -2616,7 +2616,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2636,7 +2636,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2652,7 +2652,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2666,7 +2666,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2684,7 +2684,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2874,7 +2874,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); if (is_vector) { if (is_load) { @@ -3012,7 +3012,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, writeback || rn != 31); if (is_vector) { if (is_store) { @@ -3119,7 +3119,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, true); if (is_vector) { if (is_store) { @@ -3204,7 +3204,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, dirty_addr = read_cpu_reg_sp(s, rn, 1); offset = imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn != 31); if (is_vector) { if (is_store) { @@ -3288,7 +3288,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_rs = read_cpu_reg(s, rs, true); if (o3_opc == 1) { /* LDCLR */ @@ -3350,7 +3350,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, is_wback || rn != 31); tcg_rt = cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, @@ -3510,7 +3510,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) elements = (is_q ? 16 : 8) / ebytes; tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (r = 0; r < rpt; r++) { @@ -3653,7 +3653,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (xs = 0; xs < selem; xs++) { From patchwork Thu Mar 7 17:04:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159907 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7691557jad; Thu, 7 Mar 2019 09:24:52 -0800 (PST) X-Google-Smtp-Source: APXvYqxAJCFrbbKJOPT/1I32eUtefwqOSDI2p2GuECJw8PhJyWhxThn8eDhQrHjQCP8Cb1xkWL1N X-Received: by 2002:a25:3249:: with SMTP id y70mr6148221yby.481.1551979492880; Thu, 07 Mar 2019 09:24:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979492; cv=none; d=google.com; s=arc-20160816; b=oVDpc/0X4WPCVJG0eKi5JshzvWntDxVljZeO79NAcMkxu50k/EcJZaGKF9JmZuK+l/ GIxRjYxzAwknWoG4Y0ROmSU+Da3CPm61OCX64dr8NMny0BLC4N7N+er5u+2ZtCk+RsvJ uwS0oJF45WPicPBjY/D8grZaQ06nggiZ9haR/WlI8vELVP89NHVDJ62BpB+9w76vSgcb WwqRx4yzG2ubLgbAU/JfLaLzBPlc8LJCTja3q3lyB59B48402aFQbaRYjW0FpZW6gMC/ bmWHkHp8kWeapMKraCZpQrkvAuXQ1/b4CQXorgi8hBkM2ry2gULXFS55FGx9q4058z86 ENvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=YA7+KS9+y0PKar4rFGxNDUkIxvCbaFWUtCdK+r92mgo=; b=G5w/FNUMMNIlTQq+Q6ydLIz+POuQSTCk7nzUafffg7R8d7L0YHL3VTzRiY8umOrDdT yCv7t3/ypdv+dquCIf1DXMc9wLKHp8k22X0uV8na8bmTS59PHi35WErJqB1Rdwzuj+Sv jnTbrBQxvEFzALSi14pMVR3gOac9MXX15ioI9F19/5TIuZ7o4MTy72JPsGq3G30ejhSE e3TkKNSPXDar/M8c0CoWK0xZznYluywnsGyDjzWqryOCEnila1mSwwnE14+i1ynq0JlB im0uXcSt6jL3spzMz08RpsHnx6fksGrhJdY1tyQjv4M2kQ+sS/SX0cF1CcyJb+a2XwiT Eb0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hFGBRW4c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 06/22] target/arm: Implement the IRG instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Update to 00eac5. Merge choose_random_nonexcluded_tag into helper_irg since that pseudo function no longer exists separately. --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 +++++ 3 files changed, 65 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index c88797a922..0f6e78c77e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,4 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index bcd82a9be0..cd04e4954b 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -37,6 +37,31 @@ static int allocation_tag_from_addr(uint64_t ptr) return extract64(ptr, 56, 4); } +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude == 0xffff) { + return 0; + } + if (offset == 0) { + while (exclude & (1 << tag)) { + tag = (tag + 1) & 15; + } + } else { + do { + do { + tag = (tag + 1) & 15; + } while (exclude & (1 << tag)); + } while (--offset > 0); + } + return tag; +} + +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + rtag -= extract64(ptr, 55, 1); + return deposit64(ptr, 56, 4, rtag); +} + /* * Perform a checked access for MTE. * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. @@ -131,3 +156,35 @@ uint64_t HELPER(mte_check2)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) return dirty_ptr; } } + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + /* + * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if + * GCR_EL1.RRND==0, always producing deterministic results. + */ + uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); + int start = extract32(env->cp15.rgsr_el1, 0, 4); + int seed = extract32(env->cp15.rgsr_el1, 8, 16); + int offset, i; + + /* RandomTag */ + for (i = offset = 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed = (top << 15) | (seed >> 1); + offset |= top << i; + } + rtag = choose_nonexcluded_tag(start, offset, exclude); + + env->cp15.rgsr_el1 = rtag | (seed << 8); + } + + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0d35c07504..6d8fd045da 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5284,6 +5284,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Thu Mar 7 17:04:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159889 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7668594jad; Thu, 7 Mar 2019 09:05:32 -0800 (PST) X-Google-Smtp-Source: APXvYqzYNP7NchDVwUopk1Nwq2t7aw1ZR1oGsfComHlUjSNkQFHbjaGMzqq0ZRaBb7FLIKpiYVWE X-Received: by 2002:a25:3247:: with SMTP id y68mr11768073yby.321.1551978332097; Thu, 07 Mar 2019 09:05:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978332; cv=none; d=google.com; s=arc-20160816; b=P9jq6uFKXGAkjmwkZl0BlpdNGvbgfeayNJFvh/5ZILGI4w0AtqZ52gpd0E7oc/zj1y VXNxkskOfMvwVIKQ/BgWtrL3gF1DjkIF1EtwwCGjbN+pYtjOV51mTRt2XFAlDpVUJ7/p +kc2g+MCNp3qtq36Zf6AgNfcJ9UqQvdPwRsWXCUzFf7sd42eXniLrNGN6M8xIhTB8taE 2rH7rnJyQ9F7yI/x7PVbgmI8nFZuCXUrkc8o32Mj/l/RpPKHYtHXet9lhIPlDUWtV6V3 a2z25LoVvJj4G5anKRQJseHWujfkc9pH5f/cTYpCFjOy61WOetCHWk2jlkphUBGDLpA0 jd0Q== ARC-Message-Signature: i=1; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:25 -0800 Message-Id: <20190307170440.3113-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 07/22] target/arm: Implement ADDG, SUBG instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Shift offset in translate; use extract32. --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 4 +++ target/arm/mte_helper.c | 32 +++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 86 insertions(+), 23 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 0f6e78c77e..6ad23bf9ee 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -106,3 +106,5 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index fbfa770c23..8d1a81df8c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1008,4 +1008,8 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, */ #define GMID_EL1_BS 6 +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 +#define TAG_GRANULE (1 << LOG2_TAG_GRANULE) + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index cd04e4954b..7aca5b074f 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -188,3 +188,35 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6d8fd045da..181692cd1b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3758,7 +3758,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3769,10 +3771,10 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) bool setflags = extract32(insn, 29, 1); bool sub_op = extract32(insn, 30, 1); bool is_64bit = extract32(insn, 31, 1); + bool is_tag = false; TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; switch (shift) { case 0x0: @@ -3780,35 +3782,58 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) case 0x1: imm <<= 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag = true; + break; default: + do_unallocated: unallocated_encoding(s); return; } - tcg_result = tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm = tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset = tcg_const_i32(imm & 15); + TCGv_i32 offset = tcg_const_i32((imm >> 6) << LOG2_TAG_GRANULE); - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result = tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm = tcg_const_i64(imm); + tcg_result = new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } /* The input should be a value in the bottom e bits (with higher From patchwork Thu Mar 7 17:04:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159904 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7685431jad; Thu, 7 Mar 2019 09:19:23 -0800 (PST) X-Google-Smtp-Source: APXvYqytYYpOz76s3aCN5vsYJdYTN4VVqnLAAwYZSwHRtVfeqaGrV04ausLHn1NiScub3db8LAxO X-Received: by 2002:a25:4056:: with SMTP id n83mr12615284yba.105.1551979163845; Thu, 07 Mar 2019 09:19:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979163; cv=none; d=google.com; s=arc-20160816; b=WmiKreTNJTLv74Gns9+eOoB7IW2el7xTcOjjHsVGMIYLMSXIMSBp5pD75dG4HtEQKp v/L9EF5eiAQTQxDB8TIpNFAp9n2hgka2+J+rUZ7ZN1sclp6T2Ie589kDtlLhEPbWsk1r DDoN/pOqt8powE/jpdDntYCWgbsmFPkegOQcwSC5kl95ZzKrfLyx3DIBbRwciV5Crofd F/jT2TX/qbocFAcgWUGlS/N4q3sfZgqmQNIeKnkSCaQQRpyHHakx4LSbO4hbtU0kQ/RM p9VI1vYpuwY5tPQX5jzqaVQ7RXj/lK5votyO805zfhQGy9gKcPUc7LZpG6A6sE4Le7Fn QBRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=F8FPG9SENuqhdf6hDTRz0uq8wwt3hGfwP2PIDIambNs=; b=bn6MLR43e8MLowCHli/3/bjTMLJOsy78AARE3TmBLqStCbSYIs+cICc6fR8jKMH1ym fetoDdU1ZVnpg/WhWCbu9ExJM9K1lUkjZdxjCXa+Oix3okH/2EpEaZf6LagAYXUbbEvk xz2tiB7uUfkwM4Sl5zouJmufTCN1teVhuRnoS6mnp2xbeeawoqDZ2fsikcMJ3wHdgHiB NVzfjrpt7jH0r1L5BjwOgA97tINRTkePLs02nDlmgNTW6IVOx8eAY8cX8n/pGh8HbynN RMkziWhega/ZakV8ixl2XBUzFXia/5QfOpM+lYrUpJvBguGT1pN39J2Gq0Qp/N2k4pV8 9GcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kgnnDqsR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:26 -0800 Message-Id: <20190307170440.3113-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v4 08/22] target/arm: Implement the GMI instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6ad23bf9ee..3b78e19279 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -108,3 +108,4 @@ DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 7aca5b074f..e60c6f48eb 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -220,3 +220,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag = allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 181692cd1b..e756985982 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5316,6 +5316,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Thu Mar 7 17:04:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159903 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7684864jad; Thu, 7 Mar 2019 09:18:55 -0800 (PST) X-Google-Smtp-Source: APXvYqwKeljCl4gHz6orMGjyyXqLHmNoxZJhNTgusLgM8nl+Pj2OKU6GO8DnKGlFvrhaw9HHazm5 X-Received: by 2002:a81:4e0e:: with SMTP id c14mr11050314ywb.503.1551979135434; Thu, 07 Mar 2019 09:18:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979135; cv=none; d=google.com; s=arc-20160816; b=x0cuOpflI/egy8zDCPjerGW0d4HRiaCOMT9ZdKWE3ADHyj9MN51BZmI1+D3zlkA+Vg kVfHt/UyIlRPSSFgkb8Xi1lUPdmo3DbCRboIjq8JQxu2hxUQOefTa3I/Rp5ibDTy4DNb JS8mVWGmH7Bs5cNAOOfdigLq0WjVWH1DszAGlOo5+PwlQn75ezPKBFjBoaqsx7C0IgAR e9BQjzAZwn70lJm/A2nHUbwhOv6uncc1t0roU6MuLa8WzH0xKff46RZB9lsIrgzDF501 6sEyfdnB23EQfKQSLFboMBOg8lJh0PpuWxJNfL6hbXBqEKJgFkXi8gy/nvJ8LFDr8ksJ glPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Qjf8/+eMsRpPN3rEl0yhqiJZbFAONC5pwBHjHSM3tpI=; b=VzWNn7Vu/d62NxfPBPSVOzcgzK0PkYb3jO+3RhOX2DjtqMRPBK0dFCK7ENdYkccRwk 5VFun6WiHToEdOXJjNDeCH/k5gIDIZcp7WHfQFok/PFGlDMMcYHJ49jWvkG7WG4WgMo5 7LLp+P/COmYNe6HCmHVh6L6QNKdMkHtyx4J+X+pH1iNYK/CH0kB8kV0gJKp/EkmIrq/Z k4nZThwYJor8wb7hRNcRouDARRimIvCVRpmzqPGCt6AMBkOGMHyc7uqPV7yT5WhjRT4P ywxlHRrtfI/Zow8u6hjnpWGySN/y8u0pXUXqLOiFiJQcpDy+vnRXlKfnRG2BquH5t4aE Sb3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EnnaHOzQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:27 -0800 Message-Id: <20190307170440.3113-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v4 09/22] target/arm: Implement the SUBP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Fix extraction length. --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e756985982..b27f5c697a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5290,19 +5290,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf = extract32(insn, 31, 1); + setflag = extract32(insn, 29, 1); rm = extract32(insn, 16, 5); opcode = extract32(insn, 10, 6); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - if (extract32(insn, 29, 1)) { + if (setflag && opcode != 0) { unallocated_encoding(s); return; } switch (opcode) { + case 0: /* SUBP(S) */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n = read_cpu_reg_sp(s, rn, true); + tcg_m = read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); + tcg_d = cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; From patchwork Thu Mar 7 17:04:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159911 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7698142jad; Thu, 7 Mar 2019 09:30:58 -0800 (PST) X-Google-Smtp-Source: APXvYqzqmHR6xV/Aq0waJOXBL2pb6WRWMdgCCXMHb+8S5+zFn4niqOxB99GFQIcVhWonDSXLflrN X-Received: by 2002:a81:3dc8:: with SMTP id k191mr10981557ywa.139.1551979858737; Thu, 07 Mar 2019 09:30:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979858; cv=none; d=google.com; s=arc-20160816; b=QgcU67fwToHNvJLsNkGNbOaGZWGqQNbhlSJSXXIEBtkxplliUbvQ4QlNZ8RPQ1Px55 SV9CyPe5C3nA125MHe7ic6B2k8ezxn6xnTRFITA7ojbIAwQAo4sGHVXIEU4VvzB6IQrU sPVZrMMrxiqisRD/i7T84V+vovmQp+Lk13OndzhNHh6DTwOjGw7rL32azpyNf8XfxJum /AlM3rwrk2/8Rn5UOHePUnnCcygIIHkqtNt45pn5W0WLulL3eStbpf5VdRX1Jb2ufUeD XcFs8MSLqL+8k679/FpS+loDJ/Dygdf7Ns8jjrJ1WXIWZA8Afe+mzYjQE2WYLiSyxh2f 3AEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AmqIDdbNf59JA1t3/NmXQ2mwEInbv+gIdpyKJXCMyoQ=; b=bWRjfgz859wzAV/5eV6H6fpmIyaKUhYWZUGG1MpfC3kvZ3ZSl+wSb+uvkhP4+qZzv2 icYPpGFNspGyzXr01DknLBJ4JoOsDC6MUcAGwO6Og+/gnECBjmQrl017e2JlHLb/5AUj mbhWh6tcu0vUpWtrPZkkaUKA1oeD+ebAk2M/DtFks/oELMdtHP5/Gha/IeJNtRQ1nNU+ XMCxCmM2WW8ihV5Z8dT5eHMOncz9KHjPhm4qtz3mRYtD+gJ7wY6HUYWnvXLQLPDWwoRa 5FuH4N7GEEBAZ9NFC8Yrm43CPo1QSHE4w700oyBdzo1nyu6QeCFUsom9OVL6NdSMR6cA pXwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xMe3HR02; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:28 -0800 Message-Id: <20190307170440.3113-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will need this to raise unaligned exceptions from user mode. Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) -- 2.17.2 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..d3cf362e4b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -87,8 +87,6 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, return val; } -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -179,6 +177,22 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, raise_exception(env, exc, syn, target_el); } +/* Raise a data fault alignment exception for the specified virtual address */ +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + ARMMMUFaultInfo fi = {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.type = ARMFault_Alignment; + deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); +} + +#ifndef CONFIG_USER_ONLY /* try to fill the TLB and return an exception if error. If retaddr is * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) @@ -200,21 +214,6 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, } } -/* Raise a data fault alignment exception for the specified virtual address */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - ARMCPU *cpu = ARM_CPU(cs); - ARMMMUFaultInfo fi = {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.type = ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); -} - /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort * exception From patchwork Thu Mar 7 17:04:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159909 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7692119jad; Thu, 7 Mar 2019 09:25:24 -0800 (PST) X-Google-Smtp-Source: APXvYqxoZKpsLYrFYQ2Rd6aPh9T749o1uxfn8v+66g9vVCDtwqxfmV38pWa5dS+GD2bWnNPzo0Xn X-Received: by 2002:a25:e08e:: with SMTP id x136mr12487004ybg.326.1551979524437; Thu, 07 Mar 2019 09:25:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979524; cv=none; d=google.com; s=arc-20160816; b=mVK5rUyhmYveIVDPJa7ngqcCQ17Cvc5MTB3ogBHR8uR0p9RCUr0JbpixNPA9jB+DnM Mv9tZXOs/NkuuG9y3Q8fx41++YTXlVZnpVl2pOJ0D1QNf+gLFOt4rSS3zG5sUyVw98oL xMNvILw3eqs3vJ0paZVtNL3E++SI3lBKwszD6Qv8tIpmWfLx8jVkO8XzsCOuk5Ol16FD e2mddax5Dwj45RNuhrh6Lhyn1+KyfoLCWZKK3x2y+Tm14Q0q0hq4j/3QQrwL2VlFjRMm Po2EmvN3mlratYrAOK8gR+toU6zEAdnCCbjUAzNn+a90nQjqpitcyAuaHJyUg3pSIc6M hyUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kC8dGS5bwakRyiSkZDLhlwnGTV3wjN/suLzztl4IJdE=; b=fx9eNVPARwImRlCCo0FjjZzuy9aKZgQYQsNV+a9fg4eHfVNTlg566ZTu0UTyARCZ/F k+saFq3kOpQCRWBeLQoW88Y2Z2s02WDym3cTUpOoYTZ1KkPRnJtU09/uKguESzAC80l9 +ySeSTklCzO4/tHXkfxk8R6fHgMEZ6HgkokvMo/V8lgaEq8H8uAbRnS7J5sZm3saOmiV bAv6PsvAgbTB7u94r4WpHhMF6YE63ttxkRF6CyRvV1vAXWD1mKXK6pjdaQy2r7Obijh0 ZrUlXMcy2tNbvmagCVGXiNTKAgBhLVixNgqlonmDqXh1lYd0Sf5p4GC43soUwTnHILw3 0dww== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AoeJfQZt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:29 -0800 Message-Id: <20190307170440.3113-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 11/22] target/arm: Implement LDG, STG, ST2G instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Split out allocation_tag_mem. Handle atomicity of stores. v3: Add X[t] input to these insns; require pre-cleaned addresses. --- target/arm/helper-a64.h | 5 ++ target/arm/mte_helper.c | 151 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 115 ++++++++++++++++++++++++++++ 3 files changed, 271 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 3b78e19279..91e6a6ea94 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -109,3 +109,8 @@ DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e60c6f48eb..e8873f1e75 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,8 +25,21 @@ #include "exec/helper-proto.h" +static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, + bool write, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return NULL; +} + static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) { + uint8_t *mem = allocation_tag_mem(env, ptr, false, ra); + + if (mem) { + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + return extract32(atomic_read(mem), ofs, 4); + } /* Tag storage not implemented. */ return -1; } @@ -226,3 +239,141 @@ uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) int tag = allocation_tag_from_addr(ptr); return mask | (1ULL << tag); } + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + int el; + uint64_t sctlr; + int rtag; + + /* Trap if accessing an invalid page. */ + rtag = get_allocation_tag(env, ptr, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (rtag < 0 || !allocation_tag_access_enabled(env, el, sctlr)) { + rtag = 0; + } + + return address_with_allocation_tag(xt, rtag); +} + +static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { + arm_cpu_do_unaligned_access(ENV_GET_CPU(env), ptr, MMU_DATA_STORE, + cpu_mmu_index(env, false), ra); + g_assert_not_reached(); + } +} + +/* For use in a non-parallel context, store to the given nibble. */ +static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + uint8_t new = deposit32(old, ofs, 4, tag); + + atomic_set(mem, new); +} + +/* For use in a parallel context, atomically store to the given nibble. */ +static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + + while (1) { + uint8_t new = deposit32(old, ofs, 4, tag); + uint8_t cmp = atomic_cmpxchg(mem, old, new); + if (likely(cmp == old)) { + return; + } + old = cmp; + } +} + +typedef void stg_store1(uint64_t, uint8_t *, int); + +static void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int el; + uint64_t sctlr; + uint8_t *mem; + + check_tag_aligned(env, ptr, ra); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* Store if page supports tags and access is enabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (mem && allocation_tag_access_enabled(env, el, sctlr)) { + store1(ptr, mem, allocation_tag_from_addr(xt)); + } +} + +void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1_parallel); +} + +static void do_st2g(CPUARMState *env, uint64_t ptr1, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int el; + uint64_t ptr2, sctlr; + uint8_t *mem1, *mem2; + + check_tag_aligned(env, ptr1, ra); + ptr2 = ptr1 + TAG_GRANULE; + + /* Trap if accessing an invalid page(s). */ + mem1 = mem2 = allocation_tag_mem(env, ptr1, true, ra); + if (unlikely((ptr1 ^ ptr2) & TARGET_PAGE_MASK)) { + /* The two stores are across two pages. */ + mem2 = allocation_tag_mem(env, ptr2, true, ra); + } + + /* Store if page supports tags and access is enabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if ((mem1 || mem2) && allocation_tag_access_enabled(env, el, sctlr)) { + int tag = allocation_tag_from_addr(xt); + + if (likely(mem1 == mem2)) { + /* The two stores are aligned 32, and modify one byte. */ + tag |= tag << 4; + atomic_set(mem1, tag); + } else { + /* The two stores are unaligned and modify two bytes. */ + if (mem1) { + store1(ptr1, mem1, tag); + } + if (mem2) { + store1(ptr2, mem2, tag); + } + } + } +} + +void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b27f5c697a..b94a5571e0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3689,6 +3689,118 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } } +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 = extract32(insn, 10, 3); + int op1 = extract32(insn, 22, 2); + bool is_load = false, is_pair = false, is_zero = false; + int index = 0; + TCGv_i64 dirty_addr, clean_addr, tcg_rt; + + if ((insn & 0xff200000) != 0xd9200000 + || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + switch (op1) { + case 0: /* STG */ + if (op2 != 0) { + /* STG */ + index = op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 != 0) { + /* STZG */ + is_zero = true; + index = op2 - 2; + } else { + /* LDG */ + is_load = true; + } + break; + case 2: + if (op2 != 0) { + /* ST2G */ + is_pair = true; + index = op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 != 0) { + /* STZ2G */ + is_pair = is_zero = true; + index = op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + dirty_addr = read_cpu_reg_sp(s, rn, true); + if (index <= 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + + clean_addr = clean_data_tbi(s, dirty_addr, false); + tcg_rt = cpu_reg(s, rt); + + if (is_load) { + gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rt); + } + } else { + if (is_pair) { + gen_helper_st2g(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stg(cpu_env, clean_addr, tcg_rt); + } + } + + if (is_zero) { + TCGv_i64 tcg_zero = tcg_const_i64(0); + int mem_index = get_mem_index(s); + int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; + + for (i = 0; i < n; i += 8) { + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + tcg_temp_free_i64(tcg_zero); + } + + if (index != 0) { + /* pre-index or post-index */ + if (index > 0) { + /* post-index */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3713,6 +3825,9 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* Load/store tag */ + disas_ldst_tag(s, insn); + break; default: unallocated_encoding(s); break; From patchwork Thu Mar 7 17:04:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159895 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7676179jad; Thu, 7 Mar 2019 09:11:39 -0800 (PST) X-Google-Smtp-Source: APXvYqyxUwSMIahQ4Hh2L3dMiImOIF0xcOhgDlwuhF2Jq3mBXyC7tlrtDMy4LdqSjTELSkJSYNZA X-Received: by 2002:a25:938f:: with SMTP id a15mr11720379ybm.19.1551978699354; Thu, 07 Mar 2019 09:11:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:30 -0800 Message-Id: <20190307170440.3113-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 12/22] target/arm: Implement the STGP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v3: Handle atomicity, require pre-cleaned address. --- target/arm/translate-a64.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b94a5571e0..b7175897e4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2787,7 +2787,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2812,6 +2812,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) bool is_signed = false; bool postindex = false; bool wback = false; + bool set_tag = false; TCGv_i64 clean_addr, dirty_addr; @@ -2824,6 +2825,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (is_vector) { size = 2 + opc; + } else if (opc == 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { + unallocated_encoding(s); + return; + } + size = 3; + set_tag = true; } else { size = 2 + extract32(opc, 1, 1); is_signed = extract32(opc, 0, 1); @@ -2876,6 +2885,15 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) } clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); + if (set_tag) { + TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); + if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rn); + } else { + gen_helper_stg(cpu_env, clean_addr, tcg_rn); + } + } + if (is_vector) { if (is_load) { do_fp_ld(s, rt, clean_addr, size); From patchwork Thu Mar 7 17:04:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159910 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7695112jad; Thu, 7 Mar 2019 09:28:14 -0800 (PST) X-Google-Smtp-Source: APXvYqzNS5bRjluDEfCul6ZXnwEqFOb19VhIs8wC92ZfVe/n/GOILl4cdJjiF69g60XJIT3uBcbr X-Received: by 2002:a81:3a0d:: with SMTP id h13mr11182433ywa.224.1551979694594; Thu, 07 Mar 2019 09:28:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979694; cv=none; d=google.com; s=arc-20160816; b=XK3kkC3an0ZbEEeRrF3ag3DBTPmc7EDPkpzj/1eyQDL6Fe1WqB08Z1J6fwqTWcVU46 nMELcbSnyLj3e7SW4umElsUbdfiKPFYoA16yN5gKUczfGO11K0cyzsq6Eah8DTW2rrnu vjM6y9X38+oGjnsd6Vf5ZPDoMbUlonD4V9Z4JHdW0UfaPyVJGPJwIcNxCMJcZHjlbaT8 Sqo7znZ+LrC1TbDiLXN5TBmlWRozH3vlVTWTRMn0esYA8JYk3Lfh3lv9ZNDNl7jXaQ87 VD0IEnO6kgtysrYtvyiyUxIqbZ39qmjh4ghClBdWbb2/b+K7tRFEVHzrYPvgdNv3d5EF 7Kvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=LF5r/FY6qT7SXcssQE+itHyGE4T5BmL5LQGu28GFm3g=; b=Plfrk1lmm7STNQ/odGY73RzJbnD+sjb6HIGUd/n32XuW5/rUH5DUo5KFmvMEq1uVaX F8uwnxx4z2LoQJr8kgRcyyoo2Tn3sSsR3N18AOO7DHOj1+GfmKJ9c2ut4RbA+1GjI8et 1ySner/Q6mbYt9DcTpPbCJ+zCQg1mFqvBNZ4glf9cqeo6JzHmTOC6PDGMikKKLRi6+H9 /F6aXHyVj2geQsW1XvznMuj/1uK/IFyxKdAYihPlFw4flbf3vkTyEChUGplXayVwBEh1 eZ73iA54yAPaGGjEIQ4sxA+g/0xOi45cV7XnL6bIwtw0nbgPJI7m6PUwxiC0jAnDdBWx Acmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rsFcbwz+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:31 -0800 Message-Id: <20190307170440.3113-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 13/22] target/arm: Implement the LDGM and STGM instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v3: Require pre-cleaned addresses. --- target/arm/helper-a64.h | 3 ++ target/arm/mte_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 42 +++++++++++++---- 3 files changed, 132 insertions(+), 9 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 91e6a6ea94..5bcdfcf81b 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -114,3 +114,6 @@ DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e8873f1e75..afa4c26535 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -377,3 +377,99 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) { do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); } + +uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, false, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return 0; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are loading 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + return ldq_le_p(mem); +} + +static uint64_t do_stgm(CPUARMState *env, uint64_t ptr, + uint64_t val, uintptr_t ra) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* + * No action if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return ptr; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are storing 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + stq_le_p(mem, val); + + return ptr; +} + +void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + do_stgm(env, ptr, val, GETPC()); +} + +void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + int i, mmu_idx, size = 4 << GMID_EL1_BS; + uintptr_t ra = GETPC(); + void *mem; + + ptr = do_stgm(env, ptr, val, ra); + + /* + * We will have just probed this virtual address in do_stgm. + * If the tlb_vaddr_to_host fails, then the memory is not ram, + * or is monitored in some other way. Fall back to stores. + */ + mmu_idx = cpu_mmu_index(env, false); + mem = tlb_vaddr_to_host(env, ptr, MMU_DATA_STORE, mmu_idx); + if (mem) { + memset(mem, 0, size); + } else { + for (i = 0; i < size; i += 8) { + cpu_stq_data_ra(env, ptr + i, 0, ra); + } + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7175897e4..e02d85f317 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3722,7 +3722,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; int op2 = extract32(insn, 10, 3); int op1 = extract32(insn, 22, 2); - bool is_load = false, is_pair = false, is_zero = false; + bool is_load = false, is_pair = false, is_zero = false, is_mult = false; int index = 0; TCGv_i64 dirty_addr, clean_addr, tcg_rt; @@ -3732,13 +3732,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) } switch (op1) { - case 0: /* STG */ + case 0: if (op2 != 0) { /* STG */ index = op2 - 2; - break; + } else { + /* STZGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_zero = true; } - goto do_unallocated; + break; case 1: if (op2 != 0) { /* STZG */ @@ -3754,17 +3759,27 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) /* ST2G */ is_pair = true; index = op2 - 2; - break; + } else { + /* STGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = true; } - goto do_unallocated; + break; case 3: if (op2 != 0) { /* STZ2G */ is_pair = is_zero = true; index = op2 - 2; - break; + } else { + /* LDGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_load = true; } - goto do_unallocated; + break; default: do_unallocated: @@ -3781,7 +3796,16 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) clean_addr = clean_data_tbi(s, dirty_addr, false); tcg_rt = cpu_reg(s, rt); - if (is_load) { + if (is_mult) { + if (is_load) { + gen_helper_ldgm(tcg_rt, cpu_env, clean_addr); + } else if (is_zero) { + gen_helper_stzgm(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stgm(cpu_env, clean_addr, tcg_rt); + } + return; + } else if (is_load) { gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (is_pair) { From patchwork Thu Mar 7 17:04:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159892 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7672619jad; Thu, 7 Mar 2019 09:08:43 -0800 (PST) X-Google-Smtp-Source: APXvYqwOqzA5s+rhRwz8ZqicTcd1mQxf/hjyt6szv8+4xkZG0sjFRn2TU/3GKMOxLFVgqckdtU3P X-Received: by 2002:a0c:8698:: with SMTP id 24mr11602897qvf.188.1551978523550; Thu, 07 Mar 2019 09:08:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978523; cv=none; d=google.com; s=arc-20160816; b=CBOsXa5hhkIKJF6cOx5Yd6R3qA32Pfh1uqeAAbenEhlqoD8JZKedL4fBxeIJMwGtjn dL6/Ew5O4KEtEpD/N9h36Sg7s8qANfOefUkjpzEplwuvKaSD33Q9XhCBwtrwX1LabNf3 OQTrsB2cAnJd7SGY7qfWrFUT4Yk7UbAGlTmcF6kMPDDxHeWwyo/JuehtzZu8hEN+sFTP XLtGPufnhFwQgPiNupwZ+K3vTy0fb3Mq0PYDvNoQLdoX9M5aRACMhcf9jLMk0Jb5ogOn 7x7bUU60L4j4QFZjXQ1zM7lqGjEtJ8j2RBllNZsiZsCcH08MwwdmnC7CXfoULZUI2o86 mgXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=KjM4haI49S06I+pNMa6BJgUxdWD4RG+/BNqUDF5OoYk=; b=bw/jY70XPUXvHbRW9/qfr6GvHN87BLGM9YFV00H9DQrYXJgeYCr0OS90aZPvoTkq4k d5YwUsgYO/cnGk0BMo0jgAijCQdRUF4VQng7/JRiJxY4pQKR8WaFRfMfg/oMLhCaq6oh f3QIBFS/yoYlx6PGF1cYLEPlr2vESN6JGXzsW7K65rXbIwG0DOOlIPfcEoOHN1CV2Tzn +GyU/edUmV/py4Ivxt03mMIdeMOcea+Zuf4/Yp+OAw8OK2FZEdc3OuihYFNZ4XGj9J0U t987fp928qlZa7ahaGQmRE9Lc5GYsVeDdou4OHofu7GXKG05/87b184Hk0cfqFRdmLom F1Vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ha80EfvH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.04.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:04:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:32 -0800 Message-Id: <20190307170440.3113-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 14/22] target/arm: Implement the access tag cache flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Like the regular data cache flushes, these are nops within qemu. Signed-off-by: Richard Henderson --- target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b30e1a1a9..a16c87d0d9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5793,6 +5793,54 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + { .name = "IGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, REGINFO_SENTINEL }; #endif From patchwork Thu Mar 7 17:04:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159908 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7692058jad; Thu, 7 Mar 2019 09:25:21 -0800 (PST) X-Google-Smtp-Source: APXvYqw3tc+uOL5eZmarDS/5ecUSLqhRp2OAn+5Slpqxemu8B+UITk5JfB9fk7V+CQFl8aAnJrOb X-Received: by 2002:a25:886:: with SMTP id 128mr12141838ybi.50.1551979521450; Thu, 07 Mar 2019 09:25:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979521; cv=none; d=google.com; s=arc-20160816; b=yc8Fc1E1KSqiCh+eUuxW0U6xbcnZdmo/FwW+RLp73fZ0yyeBeGvGlUfP6Fn3RzlLM7 kbR957zGYSln1mqiY+OhhB+50F6/RPK/3YIiKtitOHzuSQGgsyF2DdKN+jFPEOsPTJnn umLwVvOgx5DUFEtW4ZFOzq/msFwzpcX8EPq4xFIqbdPJJoYEccxnA/n02KAeA0jL/u53 Ex88J+jI+929OI/c8lFTFy1CGuCmWlkBHcWq9V0NqpAEsw6RrhVtdrIoZcC9tYjcWGPb BVIH+RQDJtPdlCpmBp6GiEhJOBm4fICH4qYeU5gX2Hr6FkV6kDOL7EtuqLwblPvtSc1P 1cNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qOMrzassKCDwtZ4xoDYEipVJ3Cgth507RSry7kgDyHs=; b=mLEOv4vmJi8aPVQUzvbzAVY8wqC7YiOQp51d0XBZq/07KAfNLH5CJSGWZB5QDfLMdQ F/Ha9VxBP/0BULtLDXU+GK/LYnxCmF5mYBa/WYg9FYO266GezKw+ntWQPq2NvXzr9Xwm 15DCoq06WNoWKsfs2Cc3cug7+6SfpLM/NqQZwpGn5if6iAMHG2ZjfckoukAqHl8x8Oxa eAOpGV1mVMv13IEIBLEP1PHDxgw3/juvs1eKkErP2tb2i3loHr81Lk5GaOUY4NMh4/EW 9dXw0J7BjallYEmAVUWyE1GWBI7pKYwB0T9p7wZZb60pui8YJQBfpa2Qrmk1QWunTP4U UnVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LnrYb58z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:33 -0800 Message-Id: <20190307170440.3113-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v4 15/22] target/arm: Clean address for DC ZVA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data access was forgotten in the previous patch. Fixes: 3a471103ac1823ba Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e02d85f317..a02c829db2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1894,7 +1894,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ - tcg_rt = cpu_reg(s, rt); + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); gen_helper_dc_zva(cpu_env, tcg_rt); return; default: From patchwork Thu Mar 7 17:04:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159906 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7689896jad; Thu, 7 Mar 2019 09:23:22 -0800 (PST) X-Google-Smtp-Source: APXvYqyObE3AmyJIif1gF13IXHNB4qInghR1SJkBAe9qINSP/4MNWmCjyMS2CQVrwEa6ajuDNtLB X-Received: by 2002:a25:d614:: with SMTP id n20mr12287590ybg.436.1551979402130; Thu, 07 Mar 2019 09:23:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979402; cv=none; d=google.com; s=arc-20160816; b=v8YUMsgxJgoxkEephvlL2t5zZOBaU/DdqSJLqNyDl6U+VZeewNSVIz2WS+ZO79za8+ 5FcXxVjcjYagnMTHkyRhw6X0uPhy4WoOZY14jnkGQdtlWW8go79Cmm1LRddxYEAt2iDC OmWaCIQh3P4DrC8oEIf2pDWQxzBWjc7UQYHrTBQ7IC0ZblHATneQKw/ONll2raWVfRGf Tv76/m1bU7q3Xk9hs9liDhIFEfJdVzs1BollZfjwVqesvDtWrfh/z2NdSBU2oW1WMK8a okGRKMfnLtEvmW9aRv3kJhiehr6vmJ1/pjsQgVjAKVs3KP1FBqJ28Cp3tOty0PQrE2bk XSkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=S62ne+fzmxVWOcg1VdlK0dr2mFZWCa/ldZdfdyxAfIs=; b=LKpUnOJ2YAhhA13NWFWWmJrltFQfl451gZ4UDJ03spqRFzC6L1VMWww05NjnBpkBnD uc9KJwYMyEl5bTMA3844LlL4Safpz0A2qdr0gBoyINsmJamgbsoA7/+wmHxcZdpq7UBg mIfOW8/YlKsRH/fq8E2YKw2MUUNWcgc5qKVuAsyr/F/ml1ro323Rbk/nNS8uUqXMm+TF DEGFwfOLrI3p7dBHrYCDVCnxRNd5ffgiVJipAo22zam0yoIIL5AtVcAtiVplwnaa4YSN F2WIz84k2OSreVN6fX1BmV/tks0BIP6nKDwvft6Fl/jR7pX6oIFBI5WJJVoCxIeCPXQo ltng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="R4b/ReyR"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:34 -0800 Message-Id: <20190307170440.3113-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 16/22] target/arm: Implement data cache set allocation tags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is DC GVA and DC GZVA. Signed-off-by: Richard Henderson --- v2: Use allocation_tag_mem + memset. v3: Require pre-cleaned addresses. --- target/arm/cpu.h | 4 +++- target/arm/helper-a64.h | 1 + target/arm/helper.c | 16 ++++++++++++++++ target/arm/mte_helper.c | 28 ++++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++++ 5 files changed, 57 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b9b33bc285..e24d1e082c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2178,7 +2178,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 5bcdfcf81b..ec4e7f7cf5 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -117,3 +117,4 @@ DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(dc_gva, TCG_CALL_NO_RWG, void, env, i64) diff --git a/target/arm/helper.c b/target/arm/helper.c index a16c87d0d9..c8773a5528 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5841,6 +5841,22 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "GVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, + .access = PL0_W, .type = ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, + { .name = "GZVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, + .access = PL0_W, .type = ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index afa4c26535..6d0f82eb99 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -473,3 +473,31 @@ void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) } } } + +void HELPER(dc_gva)(CPUARMState *env, uint64_t ptr) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + size_t blocklen = 4 << cpu->dcz_blocksize; + int el; + uint64_t sctlr; + uint8_t *mem; + int rtag; + + ptr = QEMU_ALIGN_DOWN(ptr, blocklen); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, GETPC()); + + /* No action if page does not support tags, or if access is disabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag = allocation_tag_from_addr(ptr); + rtag |= rtag << 4; + + assert(QEMU_IS_ALIGNED(blocklen, 2 * TAG_GRANULE)); + memset(mem, rtag, blocklen / (2 * TAG_GRANULE)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a02c829db2..74ef1cd9c1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1897,6 +1897,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; + case ARM_CP_DC_GZVA: + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); + gen_helper_dc_zva(cpu_env, tcg_rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; default: break; } From patchwork Thu Mar 7 17:04:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159897 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7679551jad; Thu, 7 Mar 2019 09:14:26 -0800 (PST) X-Google-Smtp-Source: APXvYqxaOGw/JieKOgn4UAxS5oMWzTOoDP1Yp1HL2u0e+WzznJMEsH7UwJNonHssEASJCChReQ99 X-Received: by 2002:a25:d656:: with SMTP id n83mr11696536ybg.423.1551978866397; Thu, 07 Mar 2019 09:14:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978866; cv=none; d=google.com; s=arc-20160816; b=n/+Nv3X/3mpYGjbSa5Fpca4OXmcNu+/z27z5icRbRax7juED4baGc8yQMR1ZLNdedW f7p1GSGVTP5UP8li2gmY08W9yhPbaW2nac12wauJRdFxFWNsPU8KRFbCtXamKMpRa4ML FykD27z8WnlqAdVt7XEImYZBin8jaIeKtxL79PPZcbN6VxQ6IaruOfHuSthMQZrPefvA cBI2bVvtdPVd0q4JKxpNuCQwKw+i06msZQPGP87WmoG4U0GFHZGVYu9UAJJmafezbmsq UVgNG4EKwJHpjpmmL2JDBn9Q9S+L0KIjyqbuPP1lyEvexrUBeUcov2R0Cczs+bwMlzU+ zUQQ== ARC-Message-Signature: i=1; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:35 -0800 Message-Id: <20190307170440.3113-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PATCH v4 17/22] target/arm: Set PSTATE.TCO on exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0085 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Only set if MTE feature present. --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index c8773a5528..a529d30700 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9628,6 +9628,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int cur_el = arm_current_el(env); + unsigned int new_pstate; /* * Note that new_el can never be 0. If cur_el is 0, then @@ -9721,7 +9722,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); - pstate_write(env, PSTATE_DAIF | new_mode); + new_pstate = new_mode | PSTATE_DAIF; + if (cpu_isar_feature(aa64_mte, cpu)) { + new_pstate |= PSTATE_TCO; + } + pstate_write(env, new_pstate); env->aarch64 = 1; aarch64_restore_sp(env, new_el); From patchwork Thu Mar 7 17:04:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159905 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7689129jad; Thu, 7 Mar 2019 09:22:41 -0800 (PST) X-Google-Smtp-Source: APXvYqwScvOKRb0rDmtxAi2jlcJxiwf72yCL+873C06IshWWGJHmvfp/U3/UZhvoBNyAaFw+NZ3D X-Received: by 2002:a81:4907:: with SMTP id w7mr11140136ywa.150.1551979361454; Thu, 07 Mar 2019 09:22:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979361; cv=none; d=google.com; s=arc-20160816; b=JPJEmsqtmYQbBZUuZRWwdkaUhPdghbbDVWQjy5uq17pOxi7FjXnJXZPaMsEG3rzWFa 9XV9yaG0PGBnHiclGCjSmoYG+en/e7On+T76TgtYqpC3fztSlZINhvTmyRlEqxwJ9NMT X5tKB979JfkbPzpnP8nx/T1aWJQz730xzoH70wIFSRLubhGUVoaIaMFq3T1QHLOWbWjb OL/e70IOgRgJ1uwOgxwcs2YNW9Lk8ghtUHLv/IqC3pOeQ6UIHIWif75+tb6luUXPmtag OITGXIBzw8I2BjEAYyFiI28PTj02erLPDZxDzzCVCdSiLOzypKPRdvK5GMUmNO+P7Rwv dA+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kZSCj41zsLv3G3Z37H9nlBKFYKrUJPFTvgfq0XY5xHA=; b=g0bmmvhJS3T9DjBqSM+9ZqjI4bHDeghRYWbBU/9y+d+rwT1EV4nKrGBXONDROZeDpP SBMY9k47FtyY+Vg5r7NSWV+2g3zT1s++bzKKeaKJBCeOrEmcRkX8uhfJSdwPNVur1aA2 BkAEe0VM783zrmawDzJqqDexEBt7+AEWhGXV95oSQW57sP7TBfXtKvW8+xzaA0V75JrL UVbg/qN/ivg6nUCWWkKqCYkLeZZcI+tuWcsErcO04o2slMZUMWsCetFsEVq+M/9UtNgU aw3A4bhaBjiEdc/kh88eilsIZUCXeRvNjHQS3bHBPegaCJLMTTi4AdtuOmDjvLoX67dH eckw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ghDXqfWz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:36 -0800 Message-Id: <20190307170440.3113-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 18/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index a529d30700..fcab7f99be 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10892,6 +10892,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; + uint8_t memattr; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -11122,17 +11123,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, txattrs->target_tlb_bit0 = true; } + if (mmu_idx == ARMMMUIdx_S2NS) { + memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint64_t mair = env->cp15.mair_el[el]; + memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8); + } + + /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */ + if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) { + txattrs->target_tlb_bit1 = true; + } + if (cacheattrs != NULL) { - if (mmu_idx == ARMMMUIdx_S2NS) { - cacheattrs->attrs = convert_stage2_attrs(env, - extract32(attrs, 0, 4)); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 0, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); - } + cacheattrs->attrs = memattr; cacheattrs->shareability = extract32(attrs, 6, 2); } From patchwork Thu Mar 7 17:04:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159902 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7684279jad; Thu, 7 Mar 2019 09:18:26 -0800 (PST) X-Google-Smtp-Source: APXvYqwRjzU0X39af4cK9NCV3cNcy4O3aG2RhJ9a7ssmwq/fuFI25Fw/vTwKruAWXrOuDaLu5/C8 X-Received: by 2002:a81:3083:: with SMTP id w125mr10716979yww.170.1551979106414; Thu, 07 Mar 2019 09:18:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979106; cv=none; d=google.com; s=arc-20160816; b=nUVjG1Dn0rT59U+Upi+kod6B/xLIgEtLLbs0bZ2V46oCHuvlE6hgU5SisN0vwSyXJ2 RYTE3xaw8weACByXuRlY7k86k4j9j7YJDnOEhUJnq89+91AA+opIl+S/NSNTlRdq8F6S xDpktH2xVRER1+K05gEdX3dBfu28xSUVPPYODI+9IoYE7bVUzt8C5D5aReQi1ZjVWrec IxUwRIeHoD+JxTdAX1Gm0i/twL1l/9ISQ8tf2XJQOrXLU8KpvLTIXLDFxgy7YO1aOQW/ v5pT83now1HlN8nAHbNa19gYI+kVxmMnUdYECuzSXLFmq5OLP0x8lEVJt+mrD8SpRko0 YvCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5wOghOycvZtgp0mOC7bWOAxKbOp0TkaWZxNo1dw3p8Q=; b=o3igRQvOyVYFiSbx5x3gUtmCF3NrWyfwqvGdVohnmt//gTjSQPoe1ZPLK3owMfznQu /FMUZuXT0zEYD+en5YGM8gfmefBfYApUwTjtLnlMFrki9QSr4EtRMEyYY9nxG2tCrrKK NeJRxtFdTGmiemk87Luvt/IUwE+JX+Us6yY3IBhBiDUjTz593/nw31lRQMsRI+N5kjkV tADGXbw+4806dQl7NOpTUcX7945tNZeDDjnTmTCrlnOwMGhIOE9gH2ZsqSwIFK/euDUh FRNuoUCHjvz6EOYKPPySYnCgSDegMeWnkoYcSKbky6t/8ZE5kfKTL+z2t+1iUsNfePro Qjfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BqcrZTke; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:37 -0800 Message-Id: <20190307170440.3113-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PATCH v4 19/22] target/arm: Create tagged ram when MTE is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ target/arm/cpu.c | 21 ++++++++++++++++++--- 3 files changed, 55 insertions(+), 3 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e24d1e082c..6d60d2f37d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -768,6 +768,9 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; @@ -2904,6 +2907,7 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch); typedef enum ARMASIdx { ARMASIdx_NS = 0, ARMASIdx_S = 1, + ARMASIdx_TAG = 2, } ARMASIdx; /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c7fb5348ae..5be76fc2ee 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1265,6 +1265,21 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } +static void create_tag_ram(VirtMachineState *vms, MachineState *machine, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *tagram = g_new(MemoryRegion, 1); + hwaddr base = vms->memmap[VIRT_MEM].base / 32; + hwaddr size = machine->ram_size / 32; + + memory_region_init_ram(tagram, NULL, "mach-virt.tag", size, &error_fatal); + memory_region_add_subregion(tag_sysmem, base, tagram); + + /* ??? Do we really need an fdt entry, or is MemTag enabled sufficient. */ + /* ??? We appear to need secure tag mem to go with secure mem. */ + /* ??? Does that imply we need a fourth address space? */ +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board = container_of(binfo, VirtMachineState, @@ -1423,6 +1438,7 @@ static void machvirt_init(MachineState *machine) qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *secure_sysmem = NULL; + MemoryRegion *tag_sysmem = NULL; int n, virt_max_cpus; MemoryRegion *ram = g_new(MemoryRegion, 1); bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); @@ -1584,6 +1600,20 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } + /* + * The cpu adds the property iff MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem = g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + } + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + } + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } @@ -1626,6 +1656,9 @@ static void machvirt_init(MachineState *machine) create_secure_ram(vms, secure_sysmem); create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } + if (tag_sysmem) { + create_tag_ram(vms, machine, tag_sysmem); + } vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 96f0ff0ec7..96506cf56d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -870,6 +870,18 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); + } +#endif } static void arm_cpu_finalizefn(Object *obj) @@ -1182,16 +1194,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) init_cpreg_list(cpu); #ifndef CONFIG_USER_ONLY + cs->num_ases = 1; if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { cs->num_ases = 2; - if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases = 1; + } + if (cpu->tag_memory != NULL) { + cs->num_ases = 3; + cpu_address_space_init(cs, ARMASIdx_TAG, "cpu-tag-memory", + cpu->tag_memory); } cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); From patchwork Thu Mar 7 17:04:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159896 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7676189jad; Thu, 7 Mar 2019 09:11:39 -0800 (PST) X-Google-Smtp-Source: APXvYqwoYuDWiqclLKJjjxGlR6W3hLeV+FfEmKnsrSRGtk4yDRip+vD0yCIG9OM63Km0K2yw7p+4 X-Received: by 2002:a81:4fd6:: with SMTP id d205mr10393663ywb.80.1551978699680; Thu, 07 Mar 2019 09:11:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978699; cv=none; d=google.com; s=arc-20160816; b=0PiJKTFdQR490/zXy0+c6VwN2hzxaxl2RzLzpJJd2W6cRq/h56dE+P/t+tyjGxmvh2 G7NMkl94b8RZT4dBtN8F6Y8UEWfN6+ogqTlZjGyWrfDgHtm7G9IGCbbIH4HAz05pnFoU fakFflkbk1Crqcvvp/OEpQmakg4YZhpvQrq3kQtdVOPhyueGdD+QxzGhWl07slcu8ar5 S21pRRKhk2EWrp9YafI1D9JBnVf2VPoe5oirG+HKxpFyyZSXB5ZvJ4vwfEFsdq6W3Qta Xo8O18sQTKnxND/637591zm2Bq4BTRQ7+2nPXgTSHs7eZGHSnrUxD3EIcooI9zqO+T7D WjSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=cmTN8SMbp3T8WkH71yni2MTau4zctsJ5FFiTQjgOTKI=; b=ZJEuuyMAuyYlyTAWI5g+vP+vxncUFsfh+7TWxNNkJLKq+Dgc8608/lyKEyVH4nds6P ZOdWFae7ZSsowX5N+xd01MWiqedHInFSH8MNNLz8XbhgnD7iBEyDpqJfSBjHZgPJJI0Z Q5gI5pdKvyDI5bRYfDXPO1J71HTzZTqrc0HrDBIEPfEhjzGLhp2s6nxkmshP8oTXb5o+ VBhQZ0BEc1zZF7y3o4Ns8fWuzSjfLNErLOLWXEx5m5YChnsh825Jzgzq6wWn4xP2WRm/ wOY9P7Vi2Bvlmpu1590EIOvUsAw7Vfy0NpWqaBbxpH9F8q48ok4XW/jFpATN8FdvBhDM grBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qEjNMPe1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 20/22] target/arm: Create a TLB entry for tag physical address space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 45 ++++++++++++++++++++++++++++++++++++++------- target/arm/helper.c | 20 +++++++++++++++++++- 2 files changed, 57 insertions(+), 8 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6d60d2f37d..3647c5bb55 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2758,10 +2758,15 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * S EL0 (aka S PL0) * S EL1 (not used if EL3 is 32 bit) * NS EL0+1 stage 2 + * NS physical tag storage * - * (The last of these is an mmu_idx because we want to be able to use the TLB - * for the accesses done as part of a stage 1 page table walk, rather than - * having to walk the stage 2 page table over and over.) + * (The NS EL0+1 stage 2 is an mmu_idx because we want to be able to use the + * TLB for the accesses done as part of a stage 1 page table walk, rather + * than having to walk the stage 2 page table over and over.) + * + * (The NS physical tag storage is an mmu_idx because we want to be able to + * use the TLB to avoid replicating the path through the rcu locks, flatview, + * and qemu_map_ram_ptr.) * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -2819,6 +2824,7 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, + ARMMMUIdx_TagNS = 7 | ARM_MMU_IDX_A, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, @@ -2845,6 +2851,7 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_S1SE1 = 1 << 5, ARMMMUIdxBit_S2NS = 1 << 6, + ARMMMUIdxBit_TagNS = 1 << 7, ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, ARMMMUIdxBit_MUserNegPri = 1 << 2, @@ -2874,11 +2881,29 @@ static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) /* Return the exception level we're running at if this is our mmu_idx */ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) { - switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { - case ARM_MMU_IDX_A: + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_S1E2: + case ARMMMUIdx_S1E3: + case ARMMMUIdx_S1SE0: + case ARMMMUIdx_S1SE1: + case ARMMMUIdx_S2NS: return mmu_idx & 3; - case ARM_MMU_IDX_M: + + case ARMMMUIdx_MUser: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MPrivNegPri: + case ARMMMUIdx_MSUser: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSUserNegPri: + case ARMMMUIdx_MSPrivNegPri: return mmu_idx & ARM_MMU_IDX_M_PRIV; + + case ARMMMUIdx_TagNS: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_S1NSE1: default: g_assert_not_reached(); } @@ -3183,7 +3208,13 @@ enum { /* Return the address space index to use for a memory access */ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) { - return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; + if (attrs.target_tlb_bit2) { + return ARMASIdx_TAG; + } else if (attrs.secure) { + return ARMASIdx_S; + } else { + return ARMASIdx_NS; + } } /* Return the AddressSpace to use for a memory access diff --git a/target/arm/helper.c b/target/arm/helper.c index fcab7f99be..eb7b719687 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11948,7 +11948,9 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -11999,6 +12001,22 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, */ mmu_idx = stage_1_mmu_idx(mmu_idx); } + break; + + case ARMMMUIdx_TagNS: + /* + * The tag tlb is physically addressed -- pass through 1:1. + * The real work is done in arm_asidx_from_attrs, selecting the + * address space, based on target_tlb_bit2. + */ + attrs->target_tlb_bit2 = 1; + *phys_ptr = address; + *prot = PAGE_READ | PAGE_WRITE; + *page_size = TARGET_PAGE_SIZE; + return 0; + + default: + break; } /* The page table entries may downgrade secure to non-secure, but From patchwork Thu Mar 7 17:04:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159899 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7680370jad; Thu, 7 Mar 2019 09:15:10 -0800 (PST) X-Google-Smtp-Source: APXvYqxJ3U/aayztOLQF3D3w2qyJRPCJfA9Z53n0WOzVE/Ol0Fq+ypvZsx+TXmG9ryCUBT2vaNn1 X-Received: by 2002:a5b:2cf:: with SMTP id h15mr12094422ybp.237.1551978910815; Thu, 07 Mar 2019 09:15:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551978910; cv=none; d=google.com; s=arc-20160816; b=VlfW37gUYrMLzPDveHWWkDpYxEsAzDh8VsSb3X114VWWcbU5meg7glfPpNYCf1NZ+M M9f45mhZMlY9lN3lCAqlmKUUgGAdwqtbGICtGxnM4Gl1FsnvN1MEs74uCv7dME+8lp6n 4D6uw+v94z9BeRCD9LZvZ62GaEQMllYeZHEsECQCBD52OgAoHFYP8GY5aVceP4RWENhi 1r/n9wKDTbf66nrNjjrFWcFJahhnNVczvVlrHKzWjdWvCiMTpgB3Y0LoM1WdyjGIv5rt TFts5gSF3LtBmtDgiIinn7B+4A7ARZUW2ViwcP8KhMphq8k5fJqwnnSUwaTBD3v09vqk 5E5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=fyyeoWJcJBeUCksPssnZkmETvY0jGmj18qrnYmQxK5I=; b=Br22d0NvYg8AEa+R1bVlN4M5vVZNf+oF0zoCM4GP1eQAox5kg8TQeYDH6JpiehUG0d IRebJIxpf0oNNcYelDc15K8dDhPjcTlUCYySpQKvaXd11mNhLhhXkH94oONOSiEtWr59 Q0jUIyy/bj3Lmc7TQx89Jpvzs3nmcpn2nz48QdO9dt/knvjfTFpFPAshFh7DCFFtaSLG Tdool+sLdMFjIW/jHaBW8telG8vYiPxPLJyKgsie9iF9mLhorCfU96uhnE+W/WHe9daZ D/C6YYis8jax2ORIarLP0PEp0VwXI9JWQWDNsPL4ELD1m5L0wPKOH2gssbdENN1MXvTC oUUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x+aN6Hgj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:39 -0800 Message-Id: <20190307170440.3113-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH v4 21/22] target/arm: Add allocation tag storage for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 6d0f82eb99..6657f57ca6 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -28,8 +28,64 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); + uintptr_t index; + int mmu_idx; + CPUTLBEntry *te; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + hwaddr physaddr, tag_physaddr; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + */ + mmu_idx = cpu_mmu_index(env, false); + index = tlb_index(env, mmu_idx, ptr); + te = tlb_entry(env, mmu_idx, ptr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, ptr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, ptr, 16, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + index = tlb_index(env, mmu_idx, ptr); + te = tlb_entry(env, mmu_idx, ptr); + } + + /* If the virtual page MemAttr != Tagged, nothing to do. */ + iotlbentry = &env->iotlb[mmu_idx][index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* If the board did not allocate tag memory, nothing to do. */ + if (!cpu_get_address_space(cs, ARMASIdx_TAG)) { + return NULL; + } + + /* Find the physical address for the virtual access. */ + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr + + section->offset_within_address_space + - section->offset_within_region); + tag_physaddr = physaddr >> (LOG2_TAG_GRANULE + 1); + + /* Find the memory backing the tag address in tag address space. */ + mmu_idx = arm_to_core_mmu_idx(ARMMMUIdx_TagNS); + te = tlb_entry(env, mmu_idx, tag_physaddr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, tag_physaddr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, tag_physaddr, 1, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + te = tlb_entry(env, mmu_idx, tag_physaddr); + } + + return (void *)(tag_physaddr + te->addend); +#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) From patchwork Thu Mar 7 17:04:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159901 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp7683318jad; Thu, 7 Mar 2019 09:17:37 -0800 (PST) X-Google-Smtp-Source: APXvYqzkRWUIsTcUyxjKgWmjJqRmSUCADfiZ2bE7wiOiSP2/PAm245bovaoZXpTxuNVtSxq8r7KZ X-Received: by 2002:a81:5f86:: with SMTP id t128mr11236229ywb.467.1551979057695; Thu, 07 Mar 2019 09:17:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551979057; cv=none; d=google.com; s=arc-20160816; b=KS1wZzW+GD6+uKbQ8ZZ0qTg0i9sQUzGvfTNc1QaCqLMs4JuBbDuM2x4Xv2/OK/MLoN yzUYJNWeghVO2+8xYocDivkQ1FiRqjS8RXOw7e0v60kej7PxofXwbs2YJ9okT38eDAEf teYIskHRz7YRWIuL229dO7bngUz3WaDitkYSK5pyuEN+ykCPrIsi+K9CwBvAcpNiHOXe gRz57bcV7wzDnGPadyC57nHPBkdKHhfxXihSEHRCTt+p63L2R1atzTQXdAMCN4/WN7if 6mtzycSA/MdbIzzKf7Lx58Q5Y2jdALXVQSRH3dvzy7Mwf8E2KJakD4QONnAi1JNKPiAK t97Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=f6NbayENDVu3RlTJsh9RCENM2lT4V95Ir1l4t74DIVU=; b=LezuX+x1m6mlARmzEKxxvm0YLsZZSjfu3BPlXZdTSTeSc/ZRU1jZn8UJUy6kIJwFPA M1ipE30KyfggQKi0FS9I9eLx3um5b9W+8FKnQri3iUd7U717HcEU8tru1T1MhKGlEiWA 77habV8FoIJc0/LuJmgYsUv3+bJiD4+oY3SPhpHMVH4pUMT3xe1iZSlUpMGOmNbS946r QXcf400bimxVFqiar7aj/MrbcLuQwEjKzyfRGTub11nJHsLJuUqmpfMeZJMVPgbNfZVJ 2KKb87MuU6DzBfqKDC+PIXgHObXYpC8RZ8oHbavWLy4VwrjjjQC890BEKBkYWZfOKqlE T5Cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="wnPG/Ehx"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id r82sm10040562pfa.161.2019.03.07.09.05.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Mar 2019 09:05:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:40 -0800 Message-Id: <20190307170440.3113-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 22/22] target/arm: Enable MTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.2 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 228906f267..27c85370c0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -332,6 +332,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr1;