From patchwork Mon Nov 7 18:59:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 622470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 029D2C433FE for ; Mon, 7 Nov 2022 18:59:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232270AbiKGS7j (ORCPT ); Mon, 7 Nov 2022 13:59:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231701AbiKGS7h (ORCPT ); Mon, 7 Nov 2022 13:59:37 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D50F121E2B for ; Mon, 7 Nov 2022 10:59:35 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id b9so17750236ljr.5 for ; Mon, 07 Nov 2022 10:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=mzBdSHu6u/NiAzmAan71AbHEXCztDx1eWL0MFLAjVBw=; b=eXWffAkvcIDnpIT9k3tN/pH23NmpS9g1ezQUyC4o6pP3m9rAiOWXxdMoQN3mrCwSzh mxEcG8m5Sl8UHiMsm05BINaRZfGAnr5l9fJ+21eVmQ6uT0a6e1Pn1iTIwNyFqk0heP9y YihmAswiiTjDleWGouA4s4PkEFWrhDaY1yq57UoOTVvB4nTtRDq0ZiKP1N+mwKaD1Vz/ RD6j3ffiy1bs7aFywSYySzNcknoDU0s/XKhDKPGC0Glr6Y7iRFVMiQcPIQ3748X2QS8/ ZiRwEwuGQfy66+1Xqu0vE39GeabAlcxGaHkFrjFPNAKOk5jAukmJ+N2lkH40uowMiu16 p5EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=mzBdSHu6u/NiAzmAan71AbHEXCztDx1eWL0MFLAjVBw=; b=P05PeehspAT7Neg1ipJjAH0jThJC7C6kaIrITHtHdRf7qpG46Ft0Je9kP3VBx7RQjj me4FWVq/EJB2Nt9WAXSA1Viuyl1YncimQ46CSkIEkxVoXEMBouBn3WvX+s+YjBn0fquT 8qKjRS98mnE1FyYEzHXGvdNxfVjTgy0QJv35A/rAu/NsfdShXxoPJz/roaVctmEIkU80 v9mVvymt59vb+WwMaBn07x8nSF5PxSnmJY9k7JR9NpdBAULwipn97YsKb1PRTCvN79Lu d1tzlFyv2rADyapF33h/qy1HERAqFyaf13RnWRPFt0LMC4OZrDAlI5Krti5GWVWvyi3u Xekg== X-Gm-Message-State: ACrzQf2Aq+nhqXO6PXuTfo0Q6MIPa9KFULqoYINs9qOXxIBYRXu947lG 8/Wq+SrDjNM1xBoEjQdCYs8p3A== X-Google-Smtp-Source: AMsMyM5hqxGfwz8P6yjzN7RdozQ/Ufrx1pPbdjNFT9maL8BpEkZziOYwFfCO3upfHVZBBSMO4WgpOQ== X-Received: by 2002:a2e:6e03:0:b0:277:d99:9971 with SMTP id j3-20020a2e6e03000000b002770d999971mr18911047ljc.34.1667847574140; Mon, 07 Nov 2022 10:59:34 -0800 (PST) Received: from krzk-bin.NAT.warszawa.vectranet.pl (088156142199.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.199]) by smtp.gmail.com with ESMTPSA id y5-20020a05651c106500b002770a9ed61bsm1327875ljm.66.2022.11.07.10.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 10:59:33 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom,msm8660: convert to dtschema Date: Mon, 7 Nov 2022 19:59:30 +0100 Message-Id: <20221107185931.22075-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert Qualcomm MSM8660 pin controller bindings to DT schema. Keep the parsing of pin configuration subnodes consistent with other Qualcomm schemas (children named with '-state' suffix, their children with '-pins'). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring --- .../bindings/pinctrl/qcom,msm8660-pinctrl.txt | 96 -------------- .../pinctrl/qcom,msm8660-pinctrl.yaml | 125 ++++++++++++++++++ 2 files changed, 125 insertions(+), 96 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt deleted file mode 100644 index f095209848c8..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt +++ /dev/null @@ -1,96 +0,0 @@ -Qualcomm MSM8660 TLMM block - -Required properties: -- compatible: "qcom,msm8660-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Qualcomm's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - - pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength, - output-low, output-high. - -Non-empty subnodes must specify the 'pins' property. - -Valid values for pins are: - gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data - -Valid values for function are: - gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b, - gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, - gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, - gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, - gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s, - lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1, - usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs - -Example: - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8660-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 173>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - - pinctrl-names = "default"; - pinctrl-0 = <&gsbi12_uart>; - - gsbi12_uart: gsbi12-uart { - mux { - pins = "gpio117", "gpio118"; - function = "gsbi12"; - }; - - tx { - pins = "gpio118"; - drive-strength = <8>; - bias-disable; - }; - - rx { - pins = "gpio117"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml new file mode 100644 index 000000000000..ad0cad4694c0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8660 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC. + +properties: + compatible: + const: qcom,msm8660-pinctrl + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 86 + + gpio-line-names: + maxItems: 173 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8660-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8660-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8660-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-2])$" + - enum: [ sdc3_clk, sdc3_cmd, sdc3_data, sdc4_clk, sdc4_cmd, sdc4_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, + gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, + gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, + gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, gsbi2_spi_cs3_n, gsbi3, + gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4, + gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, + hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, + sdc5, tsif1, tsif2, usb_fs1, usb_fs1_oe_n, usb_fs2, + usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs ] + + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@800000 { + compatible = "qcom,msm8660-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + gpio-ranges = <&tlmm 0 0 173>; + #gpio-cells = <2>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + + gsbi3-i2c-state { + pins = "gpio43", "gpio44"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; From patchwork Mon Nov 7 18:59:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 623154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FFDCC4332F for ; Mon, 7 Nov 2022 18:59:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230438AbiKGS7l (ORCPT ); Mon, 7 Nov 2022 13:59:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232291AbiKGS7j (ORCPT ); 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[88.156.142.199]) by smtp.gmail.com with ESMTPSA id y5-20020a05651c106500b002770a9ed61bsm1327875ljm.66.2022.11.07.10.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 10:59:34 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] ARM: dts: qcom-apq8060: align TLMM pin configuration with DT schema Date: Mon, 7 Nov 2022 19:59:31 +0100 Message-Id: <20221107185931.22075-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107185931.22075-1-krzysztof.kozlowski@linaro.org> References: <20221107185931.22075-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski --- .../arm/boot/dts/qcom-apq8060-dragonboard.dts | 126 +++++++----------- 1 file changed, 51 insertions(+), 75 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 0baf202a82ba..7a4c59e04af6 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -789,28 +789,24 @@ &sdcc5 { &tlmm { /* eMMC pins, all 8 data lines connected */ - dragon_sdcc1_pins: sdcc1 { - mux { - pins = "gpio159", "gpio160", "gpio161", - "gpio162", "gpio163", "gpio164", - "gpio165", "gpio166", "gpio167", - "gpio168"; - function = "sdc1"; - }; - clk { + dragon_sdcc1_pins: sdcc1-state { + clk-pins { pins = "gpio167"; /* SDC1 CLK */ + function = "sdc1"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "gpio168"; /* SDC1 CMD */ + function = "sdc1"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { /* SDC1 D0 to D7 */ pins = "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166"; + function = "sdc1"; drive-strength = <10>; bias-pull-up; }; @@ -820,18 +816,18 @@ data { * The SDCC3 pins are hardcoded (non-muxable) but need some pin * configuration. */ - dragon_sdcc3_pins: sdcc3 { - clk { + dragon_sdcc3_pins: sdcc3-state { + clk-pins { pins = "sdc3_clk"; drive-strength = <8>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc3_cmd"; drive-strength = <8>; bias-pull-up; }; - data { + data-pins { pins = "sdc3_data"; drive-strength = <8>; bias-pull-up; @@ -839,101 +835,82 @@ data { }; /* Second SD card slot pins */ - dragon_sdcc5_pins: sdcc5 { - mux { - pins = "gpio95", "gpio96", "gpio97", - "gpio98", "gpio99", "gpio100"; - function = "sdc5"; - }; - clk { + dragon_sdcc5_pins: sdcc5-state { + clk-pins { pins = "gpio97"; /* SDC5 CLK */ + function = "sdc5"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "gpio95"; /* SDC5 CMD */ + function = "sdc5"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { /* SDC5 D0 to D3 */ pins = "gpio96", "gpio98", "gpio99", "gpio100"; + function = "sdc5"; drive-strength = <10>; bias-pull-up; }; }; - dragon_gsbi3_i2c_pins: gsbi3_i2c { - mux { - pins = "gpio43", "gpio44"; - function = "gsbi3"; - }; - pinconf { - pins = "gpio43", "gpio44"; - drive-strength = <8>; - /* These have external pull-up 2.2kOhm to 1.8V */ - bias-disable; - }; + dragon_gsbi3_i2c_pins: gsbi3-i2c-state { + pins = "gpio43", "gpio44"; + function = "gsbi3"; + drive-strength = <8>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; }; - dragon_gsbi8_i2c_pins: gsbi8_i2c { - mux { - pins = "gpio64", "gpio65"; - function = "gsbi8"; - }; - pinconf { - pins = "gpio64", "gpio65"; - drive-strength = <16>; - /* These have external pull-up 2.2kOhm to 1.8V */ - bias-disable; - }; + dragon_gsbi8_i2c_pins: gsbi8-i2c-state { + pins = "gpio64", "gpio65"; + function = "gsbi8"; + drive-strength = <16>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; }; - dragon_gsbi12_i2c_pins: gsbi12_i2c { - mux { - pins = "gpio115", "gpio116"; - function = "gsbi12"; - }; - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <16>; - /* These have external pull-up 4.7kOhm to 1.8V */ - bias-disable; - }; + dragon_gsbi12_i2c_pins: gsbi12-i2c-state { + pins = "gpio115", "gpio116"; + function = "gsbi12"; + drive-strength = <16>; + /* These have external pull-up 4.7kOhm to 1.8V */ + bias-disable; }; /* Primary serial port uart 0 pins */ - dragon_gsbi12_serial_pins: gsbi12_serial { - mux { - pins = "gpio117", "gpio118"; - function = "gsbi12"; - }; - tx { + dragon_gsbi12_serial_pins: gsbi12-serial-state { + tx-pins { pins = "gpio117"; + function = "gsbi12"; drive-strength = <8>; bias-disable; }; - rx { + rx-pins { pins = "gpio118"; + function = "gsbi12"; drive-strength = <2>; bias-pull-up; }; }; - dragon_ebi2_pins: ebi2 { + dragon_ebi2_pins: ebi2-state { /* * Pins used by EBI2 on the Dragonboard, actually only * CS2 is used by a real peripheral. CS0 is just * routed to a test point. */ - mux0 { + mux0-pins { pins = /* "gpio39", CS1A_N this is not good to mux */ "gpio40", /* CS2A_N */ "gpio134"; /* CS0_N testpoint TP29 */ function = "ebi2cs"; }; - mux1 { + mux1-pins { pins = /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ "gpio123", "gpio124", "gpio125", "gpio126", @@ -951,22 +928,21 @@ mux1 { }; /* Interrupt line for the KXSD9 accelerometer */ - dragon_kxsd9_gpios: kxsd9 { - irq { - pins = "gpio57"; /* IRQ line */ - bias-pull-up; - }; + dragon_kxsd9_gpios: kxsd9-state { + pins = "gpio57"; /* IRQ line */ + function = "gpio"; + bias-pull-up; }; - dragon_tma340_gpios: tma340 { - reset { + dragon_tma340_gpios: tma340-state { + reset-pins { /* RESET line, TS_ATTN, WAKE_CTP */ pins = "gpio58"; function = "gpio"; drive-strength = <6>; bias-disable; }; - irq { + irq-pins { pins = "gpio61"; /* IRQ line */ function = "gpio"; drive-strength = <2>;