From patchwork Tue Nov 8 14:22:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 623149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D07FDC43219 for ; Tue, 8 Nov 2022 14:22:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234829AbiKHOWf (ORCPT ); Tue, 8 Nov 2022 09:22:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234589AbiKHOWI (ORCPT ); Tue, 8 Nov 2022 09:22:08 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E51C54B13; Tue, 8 Nov 2022 06:22:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667917328; x=1699453328; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jmvq9J3vKVtopSojPs7YdH4K99jNadewdc2yE8CsvjU=; b=HWwT3AIgrd+7IjtOHLu8rOxuFRIE+nHxD9Y/YFfDpslBBK6uMbmIXPKj fGOH2Jz4/rwjPweGLDf/DfKDzv5HjE1XyGrNZAZAC91zAw/KP41I6j3mz VCmZzK6+ByKmsUinDLrD0wFUDOVfCu3wrcpKuvTpPvgPB3X/kTVPBAuHk K98NUMTfceJ+SNapnoW2BoPudAueCDegVcd+6BnTgrDtFRp5JVxj4ZgBa mw9PrcBE21vKuFNBoy+psZMjfskc+NxKUgAhp5JQRoPAgrV48bScBDd3n /laBS19PBW6tOa6Ou6iJ0K/2JObZ4B+XB/DJPDnazwTnbUBDzdVpZtXjj A==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="298219282" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="298219282" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:22:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="699938291" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="699938291" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga008.fm.intel.com with ESMTP; 08 Nov 2022 06:22:03 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 6B189155; Tue, 8 Nov 2022 16:22:27 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Mika Westerberg , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v2 1/6] pwm: Add a stub for devm_pwmchip_add() Date: Tue, 8 Nov 2022 16:22:21 +0200 Message-Id: <20221108142226.63161-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> References: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org devm_pwmchip_add() can be called by a module that optionally instantiates PWM chip. In case of CONFIG_PWM=n, the compilation can't be performed. Hence, add a necessary stub. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- include/linux/pwm.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/pwm.h b/include/linux/pwm.h index d70c6e5a839d..bba492eea96c 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -478,6 +478,11 @@ static inline int pwmchip_remove(struct pwm_chip *chip) return -EINVAL; } +static inline int devm_pwmchip_add(struct device *dev, struct pwm_chip *chip) +{ + return -EINVAL; +} + static inline struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, unsigned int index, const char *label) From patchwork Tue Nov 8 14:22:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 622753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 075D0C4321E for ; Tue, 8 Nov 2022 14:22:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233924AbiKHOWw (ORCPT ); Tue, 8 Nov 2022 09:22:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234352AbiKHOWT (ORCPT ); Tue, 8 Nov 2022 09:22:19 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 809DE54B2F; Tue, 8 Nov 2022 06:22:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667917338; x=1699453338; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E9ags/i2eDk5WiEL1lMfAOWBo+2EbAcbpeazBtcJaqI=; b=IY8eOGG5AbGU/thfTYtpls063zxVpV5GhebaF0WBpN2XhwgrSwOyfsur BRM61jpRSb4AobgbzZ+yG5nimeoU1d1v7Do86xiHmC/G6KJi9qOS9BQFv Qq0ImAW8CxPffvRmL9vCtmOQK75sXKwYmaphjjLea5UZdu4zkguVYJrow LSzqAE0zazYMulRy5y+mGWyHYLPYZrqlMDX4xmUDu1B973kBe9+nAcEVm 4RiIabUdg2lD8fJ1L1iTbSY48pDbzWmsXUNXTS4XlIgxeoAC8SUWH2RFK pjS4y4T6biqEi/Id9/ILyH35ko5Mtlxx6KC4MU05w0g7TJaUAUJA3qmy4 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="310700753" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="310700753" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:22:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="587386418" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="587386418" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 08 Nov 2022 06:22:03 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 75ED429D; Tue, 8 Nov 2022 16:22:27 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Mika Westerberg , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v2 2/6] pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS Date: Tue, 8 Nov 2022 16:22:22 +0200 Message-Id: <20221108142226.63161-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> References: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The MAX_PWMS definition is already being used by PWM core. Using the same name in the certain driver confuses people and potentially can clash with it. Hence, rename it by adding LPSS prefix. Reported-by: Uwe Kleine-König Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg Reviewed-by: Uwe Kleine-König --- drivers/pwm/pwm-lpss.c | 2 +- drivers/pwm/pwm-lpss.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index accdef5dd58e..b8739cd2c235 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -252,7 +252,7 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, int i, ret; u32 ctrl; - if (WARN_ON(info->npwm > MAX_PWMS)) + if (WARN_ON(info->npwm > LPSS_MAX_PWMS)) return ERR_PTR(-ENODEV); lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index 8e82eb5a7e00..2c746c51b883 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -13,7 +13,7 @@ #include #include -#define MAX_PWMS 4 +#define LPSS_MAX_PWMS 4 struct pwm_lpss_chip { struct pwm_chip chip; From patchwork Tue Nov 8 14:22:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 622756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3E5BC433FE for ; Tue, 8 Nov 2022 14:22:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234710AbiKHOWd (ORCPT ); Tue, 8 Nov 2022 09:22:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234583AbiKHOWI (ORCPT ); Tue, 8 Nov 2022 09:22:08 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 374E854B0D; Tue, 8 Nov 2022 06:22:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667917327; x=1699453327; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3WwHPrGYys4CM9wArmF05npxQAsVuUHXIQrsJgDTthA=; b=ZN261CEaHOZHPI3HLUxY/UrppgnZgBuZlNn6VI7quBnUwrN+lgWzoSpV BeD07CBevYXyfrgUE7VivGWGNRJLLlZ/v5wCpU5Hs6lL8WaIvG4JYgqTo XQdd6VhQnJxjLgQv1pxZ08nM+l6aknOuwLSFmRwB5A8u5aejyA2aIr5AS qbbPGgsbBKb+Xbk2JHquK5RkHr5La0WZ/CjBSmd9gJaOJSrem6mBoOlhK Je0++cTO4vurwqRM/5P12zDOvgCrSt9MBrjffd7lnGpILcHYrW3u+87A5 cAoydPJl9VgeiAIoHmhrrTPlYSDAHKf/oSON+xzOm9rKTOyeHgbC1xYPM A==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="298219278" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="298219278" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:22:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="699938289" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="699938289" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga008.fm.intel.com with ESMTP; 08 Nov 2022 06:22:03 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 7D7B92B7; Tue, 8 Nov 2022 16:22:27 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Mika Westerberg , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v2 3/6] pwm: lpss: Include headers we are direct user of Date: Tue, 8 Nov 2022 16:22:23 +0200 Message-Id: <20221108142226.63161-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> References: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org For the sake of integrity, include headers we are direct user of. While at it, move the struct pwm_lpss_chip to be after the struct pwm_lpss_boardinfo as the former uses pointer to the latter. Replace device.h with a forward declaration in order to improve the compilation time due to reducing overhead of device.h parsing with entire train of dependencies. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg Reviewed-by: Hans de Goede --- drivers/pwm/pwm-lpss.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index 2c746c51b883..4561d229b27d 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -10,16 +10,12 @@ #ifndef __PWM_LPSS_H #define __PWM_LPSS_H -#include #include +#include -#define LPSS_MAX_PWMS 4 +struct device; -struct pwm_lpss_chip { - struct pwm_chip chip; - void __iomem *regs; - const struct pwm_lpss_boardinfo *info; -}; +#define LPSS_MAX_PWMS 4 struct pwm_lpss_boardinfo { unsigned long clk_rate; @@ -43,6 +39,12 @@ extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info; +struct pwm_lpss_chip { + struct pwm_chip chip; + void __iomem *regs; + const struct pwm_lpss_boardinfo *info; +}; + struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, const struct pwm_lpss_boardinfo *info); From patchwork Tue Nov 8 14:22:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 623147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC46CC4332F for ; Tue, 8 Nov 2022 14:22:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234434AbiKHOWu (ORCPT ); Tue, 8 Nov 2022 09:22:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234601AbiKHOWS (ORCPT ); Tue, 8 Nov 2022 09:22:18 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FEC854B2A; Tue, 8 Nov 2022 06:22:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667917337; x=1699453337; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9wMt9wnnchEhbLXtKxX2j9VHDQPKe8GNUSxFdZnl9NM=; b=JV+nccWw2tmUCMBzCMns2veaLpZAPZZGOmcNoiV+Op3gkbbTUHVu0Lpp DUURDi4g7UZ10OeHF6F3oHmQ7LGepLQElIXp0dD4hyNOo6AFh6fhhK7eH d1jBSlnDUnqvEhfsA4mGFD2E1LOWIq5mbk6d+kQQjEavKYLjEBewvr2Is 1+euyMRjxSHGUDfW0kKAioRUoLfEhWgwL2Bip4eis4d2Vut57+oAKcEgu wHHtLmxXNQYUR4t3Qlo3N82hdBv+iMuOlX6SOvkF63tUtoas/3aG7Qo2x 7VMSPfbizY1iD150L7jgD0pBbpVwRFjIZw7yw8mze6qvqOqKmJLimUrmh g==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="310700748" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="310700748" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:22:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="587386417" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="587386417" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 08 Nov 2022 06:22:03 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 89C534B5; Tue, 8 Nov 2022 16:22:27 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Mika Westerberg , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v2 4/6] pwm: lpss: Allow other drivers to enable PWM LPSS Date: Tue, 8 Nov 2022 16:22:24 +0200 Message-Id: <20221108142226.63161-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> References: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The PWM LPSS device can be embedded in another device. In order to enable it, allow that drivers to probe a corresponding device. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg Reviewed-by: Hans de Goede --- drivers/pwm/pwm-lpss.h | 22 +-------------- .../linux/platform_data/x86}/pwm-lpss.h | 28 ++++--------------- 2 files changed, 6 insertions(+), 44 deletions(-) copy {drivers/pwm => include/linux/platform_data/x86}/pwm-lpss.h (53%) diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index 4561d229b27d..b721532c6c3c 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -13,27 +13,10 @@ #include #include -struct device; +#include #define LPSS_MAX_PWMS 4 -struct pwm_lpss_boardinfo { - unsigned long clk_rate; - unsigned int npwm; - unsigned long base_unit_bits; - /* - * Some versions of the IP may stuck in the state machine if enable - * bit is not set, and hence update bit will show busy status till - * the reset. For the rest it may be otherwise. - */ - bool bypass; - /* - * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device - * messes with the PWM0 controllers state, - */ - bool other_devices_aml_touches_pwm_regs; -}; - extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; @@ -45,7 +28,4 @@ struct pwm_lpss_chip { const struct pwm_lpss_boardinfo *info; }; -struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, - const struct pwm_lpss_boardinfo *info); - #endif /* __PWM_LPSS_H */ diff --git a/drivers/pwm/pwm-lpss.h b/include/linux/platform_data/x86/pwm-lpss.h similarity index 53% copy from drivers/pwm/pwm-lpss.h copy to include/linux/platform_data/x86/pwm-lpss.h index 4561d229b27d..296bd837ddbb 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/include/linux/platform_data/x86/pwm-lpss.h @@ -1,21 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Intel Low Power Subsystem PWM controller driver - * - * Copyright (C) 2014, Intel Corporation - * - * Derived from the original pwm-lpss.c - */ +/* Intel Low Power Subsystem PWM controller driver */ -#ifndef __PWM_LPSS_H -#define __PWM_LPSS_H +#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H +#define __PLATFORM_DATA_X86_PWM_LPSS_H -#include #include struct device; -#define LPSS_MAX_PWMS 4 +struct pwm_lpss_chip; struct pwm_lpss_boardinfo { unsigned long clk_rate; @@ -34,18 +27,7 @@ struct pwm_lpss_boardinfo { bool other_devices_aml_touches_pwm_regs; }; -extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info; -extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; -extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; -extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info; - -struct pwm_lpss_chip { - struct pwm_chip chip; - void __iomem *regs; - const struct pwm_lpss_boardinfo *info; -}; - struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, const struct pwm_lpss_boardinfo *info); -#endif /* __PWM_LPSS_H */ +#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */ From patchwork Tue Nov 8 14:22:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 622754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86322C43217 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="298219292" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="298219292" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:22:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="761506503" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="761506503" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 08 Nov 2022 06:22:07 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 93544533; Tue, 8 Nov 2022 16:22:27 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Mika Westerberg , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v2 5/6] pwm: lpss: Add pwm_lpss_probe() stub Date: Tue, 8 Nov 2022 16:22:25 +0200 Message-Id: <20221108142226.63161-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> References: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In case the PWM LPSS module is not provided, allow users to be compiled with a help of a pwm_lpss_probe() stub. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- include/linux/platform_data/x86/pwm-lpss.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/linux/platform_data/x86/pwm-lpss.h b/include/linux/platform_data/x86/pwm-lpss.h index 296bd837ddbb..c868b396ed2c 100644 --- a/include/linux/platform_data/x86/pwm-lpss.h +++ b/include/linux/platform_data/x86/pwm-lpss.h @@ -4,6 +4,8 @@ #ifndef __PLATFORM_DATA_X86_PWM_LPSS_H #define __PLATFORM_DATA_X86_PWM_LPSS_H +#include +#include #include struct device; @@ -27,7 +29,16 @@ struct pwm_lpss_boardinfo { bool other_devices_aml_touches_pwm_regs; }; +#if IS_REACHABLE(CONFIG_PWM_LPSS) struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, const struct pwm_lpss_boardinfo *info); +#else +static inline +struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, + const struct pwm_lpss_boardinfo *info) +{ + return ERR_PTR(-ENODEV); +} +#endif /* CONFIG_PWM_LPSS */ #endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */ From patchwork Tue Nov 8 14:22:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 623148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 450DBC43219 for ; Tue, 8 Nov 2022 14:22:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234356AbiKHOWo (ORCPT ); Tue, 8 Nov 2022 09:22:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234674AbiKHOWK (ORCPT ); Tue, 8 Nov 2022 09:22:10 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 323C254B1D; Tue, 8 Nov 2022 06:22:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667917330; x=1699453330; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vyYkmlrH3FTwJFyY/NU3XVwDT0lsgxH2Rn0Y02epYKs=; b=G1+TTT565RKy1lMiBsTNmEHn5iMOuM8unZyEpMe+MWemIzobWOPfbfC8 Sf+QGiIRCuaIvGJmctei9VJl8rRomJCnx25omWEVtZ+HWykVCsqtb0dm7 eMSH658/teUTWEwbdD2q8QMKHFAH7p4LsjevAGxPN7qI/0ZNPWxnl0dI0 OC8+Pe6UxF6Wd26EcUDhOb2ZE7D5I4/jC+97KpvSzKjtZ0kdvfiAp/hye 03gtvqqoeQPMVhL1/VbyHojmli/bBXKf+N1PDa9w03hgiztobDtSUrgBO 2BaqU96GIKZyr4nzdzMwGdB5PFUL0LEomCDapyxOtqcr+yYrvtODfRGjF A==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="298219291" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="298219291" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 06:22:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="761506504" X-IronPort-AV: E=Sophos;i="5.96,148,1665471600"; d="scan'208";a="761506504" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga004.jf.intel.com with ESMTP; 08 Nov 2022 06:22:07 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 9945657A; Tue, 8 Nov 2022 16:22:27 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Mika Westerberg , Hans de Goede , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Andy Shevchenko , Linus Walleij Subject: [PATCH v2 6/6] pinctrl: intel: Enumerate PWM device when community has a capabilitty Date: Tue, 8 Nov 2022 16:22:26 +0200 Message-Id: <20221108142226.63161-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> References: <20221108142226.63161-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Some of the Communities may have PWM capability. In such cases, enumerate PWM device via respective driver. User is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 6e630e87fed6..6b685ff7041f 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -24,6 +24,8 @@ #include #include +#include + #include "../core.h" #include "pinctrl-intel.h" @@ -49,6 +51,8 @@ #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) #define PADOWN_GPP(p) ((p) / 8) +#define PWMC 0x204 + /* Offset from pad_regs */ #define PADCFG0 0x000 #define PADCFG0_RXEVCFG_SHIFT 25 @@ -1502,6 +1506,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) return 0; } +static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, + struct intel_community *community) +{ + static const struct pwm_lpss_boardinfo info = { + .clk_rate = 19200000, + .npwm = 1, + .base_unit_bits = 22, + .bypass = true, + }; + struct pwm_lpss_chip *pwm; + + if (!(community->features & PINCTRL_FEATURE_PWM)) + return 0; + + pwm = pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); + if (IS_ERR(pwm) && PTR_ERR(pwm) != -ENODEV) + return PTR_ERR(pwm); + + return 0; +} + static int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data) { @@ -1588,6 +1613,10 @@ static int intel_pinctrl_probe(struct platform_device *pdev, ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); if (ret) return ret; + + ret = intel_pinctrl_probe_pwm(pctrl, community); + if (ret) + return ret; } irq = platform_get_irq(pdev, 0);