From patchwork Tue Nov 8 18:43:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 622799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E01E2C43219 for ; Tue, 8 Nov 2022 18:44:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232233AbiKHSoV (ORCPT ); Tue, 8 Nov 2022 13:44:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231947AbiKHSoQ (ORCPT ); Tue, 8 Nov 2022 13:44:16 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 641E81C434 for ; Tue, 8 Nov 2022 10:44:15 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id p16so9399093wmc.3 for ; Tue, 08 Nov 2022 10:44:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vlDqIjsLXTsLOVaB8vd3OkA5S2UoaPdLtsIDpj43x2c=; b=BYOCyO+bb2kdgFf+IQXnllPA8KG+ULOKr2u5pTzNlB19Lf3j40UG1RZijo7Y0/dzq/ AF/aYrwiiIQaP6x1ELhtaWR9iD+iq5NQ4WKw+w1mWu7BMd/iGE/Oe6BSy+0sq2zMerak tKfhtNaasBcmEMbjNcQ+S202FCZ8DHMlSpAcFazGAs3Ztv0/k3CNF+sXyka79AFVN0Yb oODBPM2zMi7AM+sMh5oSCd9Snr5CJqFF0Az0yuneh4yvlmm5mA7UjNnPlZ/RAXttBKAw ehA3rPKyQ5e76hLebM3PW8ehPYNlVlIRJ1wEgXDn29f3frWeYEs8lUma3DWbj51RsnpH YQag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vlDqIjsLXTsLOVaB8vd3OkA5S2UoaPdLtsIDpj43x2c=; b=qAIDGYcRQBBh8k4zhilMSCvwrwCsf6ZjRFW11MmOFlBGsDQyy2bhfvYNZEV4sf1RJC HdefjWVQ24qufPPjCqpY2WcOnbbzGpCamIcgr++8yMQyLVggHGz5YRYxP2t3P7Jt5V34 PfBydBJ1LmODLlGynUzEUy8x2XqJXJhHzKbxVhFOT6njKevyDURGiJrCuNiRBiAx3SN3 1ag4s4B2BxwzJ+gd8iWAuawDsW928RXgRVnXafRoawrL79B22yKo48Q0y+8G6ucXIaLW Cl1b+SIeHA4ou0EIk4urLqY1FPMzbjqeV2TV7h7KLOjoUlN1r5+pYS7gVwAnloMPtSbx QJ6Q== X-Gm-Message-State: ACrzQf3ftLEj6EeP15yJdQI1kqLhulMD8VluShqZUkBpLnDGWZg0QgHo 7Gvpzip7rYpmCz7ZZnld2V6DYFa3oA5MDbEgtNI= X-Google-Smtp-Source: AMsMyM58wAq1y+h8vVNYOMiF2ELmoU8hLvCu+Jchx0EIlxqBBtZMzUw41rs50l4rbL73f9+wR+N22w== X-Received: by 2002:a05:600c:a0b:b0:3b4:f9a7:f79b with SMTP id z11-20020a05600c0a0b00b003b4f9a7f79bmr46623457wmp.99.1667933053693; Tue, 08 Nov 2022 10:44:13 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:12 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:36 +0100 Subject: [PATCH v4 1/9] dt-bindings: input: mtk-pmic-keys: add binding for MT6357 PMIC MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-1-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1006; i=amergnat@baylibre.com; h=from:subject:message-id; bh=acIU37N8P1oQiEeAFVfuuIgjK7XT7A/zFtqy1fGJDhM=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN66fYqgivLlb/uwv5YlVdM2vSdwHFMjBG7yoYS chbjgBeJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjegAKCRArRkmdfjHURS8vD/ 9gWsBxvGWsnueLnh+8eZVcOIt9VpVXe/hbrY/M7yOPoesCPZrw9orB99mUw7w16iA5vi7QmlADzcCk XKCUdnEoSqJU0QQgq2pmaqt4T8G7eWPd9idhG6bOEAly6+/XkomG1VJBJoxO/Xsex9I+L3lsR8XQRe Ig8dka7HNNaOwYthiaU4zJlr91/+IdPlxjQTY6NC0N65rYpTGxDHzMlK5TuCcv71gU4+ekosVAedS9 s1boIO2Gu2laFxKTo7yq15gXZnNgF2yvvCfh45yyvMoIDgP2nL9OOgS2FUDCPAtIs4q7hhNo0udrqt kroGhHXGsOpHQxVMDUhCgImaB1uF26RLrfTQ5Z+FAC5rcOL0eMSwVbzkyrLKvFoaarSMI5sFnmUi50 6LcVB3ZaIgJF/9/fz25eiB86kv4iaVflcodnroQoab8g7EuxTEXyUydVl5RCqZS05gPtexK5viqfnL XbEI8dw/ofSgWVHKxQMryxjqPS/uK9b6i/aTBCUco5XMjXSzKHAiZ7497KyUapChIuKR8CiuYXlcYj BQSpgqHVt/ZE3Kbp4cZg1eChLbp1J71DpP3bhOw394Z0yE/8RK2Q4+noiTKJ1EsCY2oE8a0lNKAHNA vnSGkM/iJVQazBlpAQ9cp83Xrvq8Q0US1bYvss5JF/XX4lRPEI/xTe0gQZ/A== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org From: Fabien Parent Add binding documentation for the PMIC keys on MT6357. Signed-off-by: Fabien Parent Acked-by: Rob Herring Acked-by: Dmitry Torokhov Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index 2f72ec418415..037c3ae9f1c3 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -26,6 +26,7 @@ properties: enum: - mediatek,mt6323-keys - mediatek,mt6331-keys + - mediatek,mt6357-keys - mediatek,mt6358-keys - mediatek,mt6397-keys From patchwork Tue Nov 8 18:43:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 623511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C840C4167B for ; Tue, 8 Nov 2022 18:44:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232068AbiKHSoZ (ORCPT ); Tue, 8 Nov 2022 13:44:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232158AbiKHSoS (ORCPT ); Tue, 8 Nov 2022 13:44:18 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72F921EAEA for ; Tue, 8 Nov 2022 10:44:16 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id v1so22398520wrt.11 for ; Tue, 08 Nov 2022 10:44:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0/WfzvHJubbv56pooqVBj0w476tmu7QbHTTDbRCIA5E=; b=TewWiwo/fKUKHnrl/jdGAA26gbsYfnUGzuWcy1Z6I8182suw87I83Z6VUuQrsVqIgV 8eYu6BsyAZSa2Nbii6LBsVNDvsHOXsbu9sQiuVGO3cAJ+MaATm0I8yqJ0Xw8ffODeFyL oTtw//bUxz0QR9Rh/ZOuKZkYUjsGnf9FlVVE5pDQJCY138jZVgeOhO4agYzEX4G5dVHx 8mhro01GcAXguWqqFwAsc/+Jrq6ya5VG5hzHT+nBE2q+KKQIyaSgn8PzHEezPJsZWA2V aPgzrhpztrn9y9rs5z0CAn2TxZ3lj53L1G5uTCW/ogDbt2i3PrGJkAnF1k6Ihwz+nclx vZ7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0/WfzvHJubbv56pooqVBj0w476tmu7QbHTTDbRCIA5E=; b=0mFxbaUe7H6SJBs05Ja2ojJ+sh4sh9Mt6dvO4BPdbxg96j6+sa28R+KcMvfoXPidYw 0oI089GtM3vM+qNF3x+ZOZ5G71EddDP/3qwoh0TroIDYlyu4i2Xu1ZbisK4k2o6T3ICM tK3RDKYQ7LgDNukcWcUlTZDo0hGsPbnuEPhVq3cmVKkYyoXBKoiKGt4qWVntsunygRkA M99gMWTHDBBUmmCoQBVXRNB0f4kNpBT30tLkEnj74ljTPzgNVffwJR1kJY582ix6/xZX Q2qARYPaDpymeNVlq8c4kV3qN6X0QhIMetZxjtlr9ODE8v/PDvmGy5WY7jVCBn8/BFfV mScw== X-Gm-Message-State: ACrzQf2+bn9ZOjqwFlJFNyFsItoizkEzsLmp683lRc7o48qAZCMYnqi5 pky5Pma5GCDZAod15VpUBN7RERD6cVGzcNdHaVc= X-Google-Smtp-Source: AMsMyM4GRByfBs2rOhytOJLVqo5arouXEthW3hO7pFcl3jL2IFAN0WwzGLcg7+E4ljaUFdtb9RkLag== X-Received: by 2002:adf:ba8f:0:b0:22c:def3:1179 with SMTP id p15-20020adfba8f000000b0022cdef31179mr36812897wrg.571.1667933054732; Tue, 08 Nov 2022 10:44:14 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:14 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:37 +0100 Subject: [PATCH v4 2/9] dt-bindings: rtc: mediatek: convert MT6397 rtc documentation MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-2-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3705; i=amergnat@baylibre.com; h=from:subject:message-id; bh=/h7YGXK8tw+BLV0bfVCW4btQXGCozMogPt+Hd7yMb0w=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN6CcEIylfYlBT9eGuZhBXMu2i4n3Ib1lYHdH1n C4gPsFeJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjegAKCRArRkmdfjHURVVaD/ 0RFrYM5QhJtj1wxw1WP8Su/8jf7SX9w6CEJdEwgOv8MoNVRPajQAS1CfjLMls9gf9+mBKCXnidGzPM bDWm+UFzkoCFRRfvNaz03yHPv/xtw4d1Mx68maavKuNtPHP4G4A1b4nK72gTK06NCa3RDJ/0LO94kJ 2szrH6wmsgb2qAIMxhv5J8IFuVg4KlGa0/GKRz2CNljD6gD33IRqmel1gDHoPLxcKgqRnTVleGNZOr obiskESHGXywTJ8h3BABgXOCUbnXOnSscs7//0XL4e61yBMOSQmeQV9e6xm9Ia1ZR3o+IAywUazdho GihclUAEcvj2Lgwu7T/xgwYy4zt8hbvK9M2m7JC4hRhtdrNMjPYpuj/irv5uAUVafwyP5PK4tAdnkU EOeTLNmgd4xgCbgVVB8hgA0Cuxfrrp1+CG4y0Y+NIBneVy3ghLzMgM1wDwTCC+BWlRaPBp1n/4tgCa 1v7AsxSaYYhb7wEeKQP//eBC0mrsfkQ5xx9MbhDWB5qq02BCwjfHci9hPcJ9YSGWQehuyckkmLIyKx fxLuAqts76aL7lWlnt+7GplIKMWrT6ORB9Lq79G2j4VVY1SM8TXFgoHUpBhYhFtDoCggWrehJLnEl4 hLr4Ae2OS/ZHx0MFVFeEJJ8C/A0cs4jE2IrLSZhbLGxc8tYCtZWq/Z2j49aQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org - Convert rtc/rtc-mt6397.txt to rtc/mt6397-rtc.yaml - Add mediatek,mt6357-rtc compatible. - Add maintainer - Remove the .txt binding file Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/mfd/mt6397.txt | 2 +- .../bindings/rtc/mediatek,mt6397-rtc.yaml | 40 ++++++++++++++++++++++ .../devicetree/bindings/rtc/rtc-mt6397.txt | 31 ----------------- 3 files changed, 41 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index 0088442efca1..79aaf21af8e9 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -33,7 +33,7 @@ Optional subnodes: - compatible: "mediatek,mt6331-rtc" - compatible: "mediatek,mt6358-rtc" - compatible: "mediatek,mt6397-rtc" - For details, see ../rtc/rtc-mt6397.txt + For details, see ../rtc/mediatek,mt6397-rtc.yaml - regulators Required properties: - compatible: "mediatek,mt6323-regulator" diff --git a/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml b/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml new file mode 100644 index 000000000000..bb48c0150f95 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml @@ -0,0 +1,40 @@ + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mediatek,mt6397-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6397/MT6366/MT6358/MT6357/MT6323 RTC + +maintainers: + - Alexandre Mergnat + +description: | + MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works + as a type of multi-function device (MFD). The RTC can be configured and set up + with PMIC wrapper bus which is a common resource shared with the other + functions found on the same PMIC. + +properties: + compatible: + enum: + - mediatek,mt6323-rtc + - mediatek,mt6357-rtc + - mediatek,mt6358-rtc + - mediatek,mt6366-rtc + - mediatek,mt6397-rtc + +additionalProperties: false + +required: + - compatible + +examples: + - | + pmic { + compatible = "mediatek,mt6397"; + + rtc { + compatible = "mediatek,mt6397-rtc"; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt b/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt deleted file mode 100644 index 7212076a8f1b..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt +++ /dev/null @@ -1,31 +0,0 @@ -Device-Tree bindings for MediaTek PMIC based RTC - -MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works -as a type of multi-function device (MFD). The RTC can be configured and set up -with PMIC wrapper bus which is a common resource shared with the other -functions found on the same PMIC. - -For MediaTek PMIC MFD bindings, see: -../mfd/mt6397.txt - -For MediaTek PMIC wrapper bus bindings, see: -../soc/mediatek/pwrap.txt - -Required properties: -- compatible: Should be one of follows - "mediatek,mt6323-rtc": for MT6323 PMIC - "mediatek,mt6358-rtc": for MT6358 PMIC - "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC - "mediatek,mt6397-rtc": for MT6397 PMIC - -Example: - - pmic { - compatible = "mediatek,mt6323"; - - ... - - rtc { - compatible = "mediatek,mt6323-rtc"; - }; - }; From patchwork Tue Nov 8 18:43:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 622798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E69CC38A02 for ; Tue, 8 Nov 2022 18:44:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232100AbiKHSo0 (ORCPT ); Tue, 8 Nov 2022 13:44:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232151AbiKHSoS (ORCPT ); Tue, 8 Nov 2022 13:44:18 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94C2B1CFDB for ; Tue, 8 Nov 2022 10:44:16 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id j15so22434981wrq.3 for ; Tue, 08 Nov 2022 10:44:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FxoXRucYOlQcIPNmHGXslDcgaR7dKA/vgefs8OdMAqA=; b=UvYMLmtfX4HhUwlEDRbPtzKDwVKAXqsZISwQv6EczKtcrIPuayj6+djC7G94vFrd2o sOFQh7oQ2oKTN+VN5p+mXCLlHeMmenlXpy9tAsdsyFeo9i1pkW7uMTXqwfnX+rTEGN0p rT3w9Xdeo2F/AoB7i0zbZus3sgssPsyk/faaJlnbpc9ZN8vusVNfDFbymN1OLdncsdtn VlPxtH6vJxbPPtDXrTlKesn5KN89vRktbbNY29fgU2LQkvCK1J+ZzSkgLvmLj02fy5Sl trz4FT0fjiNwe/8kKQCrqlcth9MHBwsWsPxmHDEAAoxtqYEvWqWTHdBvlP2bFQhWZLnq lMdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FxoXRucYOlQcIPNmHGXslDcgaR7dKA/vgefs8OdMAqA=; b=1H0/fdXo/6pnnUjBPS61uaySIIggwCqjCyoCLsg3pkYypW/L79+Fc2ZwXrFJIdCMFV HwBUmyGSkkI6OBf6RyBK6eik7BwRbaj2HIeFlgHvjzR95LfmPQ3kl48yx63r169mNzxB wTyQz25KaR3Fkg/JU74YYUMjPSMNvj6PTskbp1CTvMnd+5kTjT/CGXhGr9CYjBpzohXK PiHn5wxEVq0Hsf/x+WznnoOWOQtSKJL0hYpQgZehdjU//envP4Hto5W0LLXjH9NYlu74 HKsrlPHGmysO3uaGr498PUuArtNG+zzyQdZLVjxoUIcF8e9k2kWP0vcpxyFDUTWuose8 UJ/w== X-Gm-Message-State: ACrzQf3pagpI1LtEfYh5jXu6WiUlXvffDoaTImqVcqO7PK/DOBFhm/nN Mn1QerzECPGh+mWVbBOeQ6FwFtp7pgl04tt2dy8= X-Google-Smtp-Source: AMsMyM5r6bXE97XzRGyY5M7A6tXwv1+uBzXMSfbsbWThNqLrM+z3gAYXNmE0opiYI7RCXhggU0pSwQ== X-Received: by 2002:a5d:6887:0:b0:236:8ead:47ab with SMTP id h7-20020a5d6887000000b002368ead47abmr37583365wru.372.1667933055823; Tue, 08 Nov 2022 10:44:15 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:15 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:38 +0100 Subject: [PATCH v4 3/9] dt-bindings: regulator: Add binding schema for mt6357 regulators MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-3-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=11326; i=amergnat@baylibre.com; h=from:subject:message-id; bh=R/hUvRzGMGVuvwCEAEDVCzo5G1CT3iFbEyaH+7jjKSw=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN6gU9v6m7eXTXwCmlFeVU5KKWAhsT99/m8qNBP GeliAe6JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjegAKCRArRkmdfjHURawaD/ 9WBYVrsinp0auHADCGkq4e97NBcCUPZL/zyAY8CDWN9vb/wu42gxtlfn+d8Xl+FDpggKzP4vPeKjBE VU/t6FLJk9g/hnq4ROkgs5SX2z1qCexe9rACLm42jI5GUuNp62J5OMgRjTLzs3AHjEy8YyuYi5b1oT Xalre1xJ1ewKqGEQEFSoecMw1HIh0xNistox6MtqHYHYuP/SoDt6TQoFCb5qeo7qP05YRWSw5tlg3M OWtOkxnWD+6ILIF83aHw7GWpIs7YVTOrgii8Sh6BQgGtFztpM20eJZoFgE+/AHdKnoUWgDhkOa6Tq+ 03zsE4eyQPQDX0K6pLS+ikv0zYSZxy/gAVd69323l2avY18XlE3qRbVU0TUlsJHpAl7K/BHbaFLhRy NX6SIqWuwR2g4nCat/ef02+gco/N36Oy/mZ0dGVMQJwUeF2GFhFry6WOVCLEUkkZmPbOEWBH0FksA+ i/usfokqK7wWGwUhGhhFbqFVW85quh75Vfy7KNLtK9pYUx1UBqIgfHgAp0Paj+GRhsw/tV5VPLnTFP JCxM6YLfFAkHr2BFqgA8bNSxdtnmLtsErqnyktd3f8ggy5bUFlGcc3zKWnVsHoK1YKBKF95IJb7OSU Ggoqy/m63mJdPbQsJdJbjHyuQutAbDF0fwEmHJFP15Wc2T/4P5YKm9NOj+uA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org From: Fabien Parent Add YAML schema for the MediaTek MT6357 regulators. Signed-off-by: Fabien Parent Signed-off-by: Alexandre Mergnat Reviewed-by: Krzysztof Kozlowski --- .../regulator/mediatek,mt6357-regulator.yaml | 292 +++++++++++++++++++++ 1 file changed, 292 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml new file mode 100644 index 000000000000..3997a70a8b6c --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator.yaml @@ -0,0 +1,292 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6357-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6357 Regulators + +maintainers: + - Fabien Parent + - Alexandre Mergnat + +description: | + The MT6357 PMIC provides 5 BUCK and 29 LDO. + Regulators and nodes are named according to the regulator type: + buck- and ldo-. + MT6357 regulators node should be sub node of the MT6397 MFD node. + +patternProperties: + "^buck-v(core|modem|pa|proc|s1)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + + "^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$": + type: object + $ref: fixed-regulator.yaml# + unevaluatedProperties: false + description: + Properties for single fixed LDO regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + + "^ldo-v(efuse|ibr|ldo28|mch|cama|camd|cn33-bt|cn33-wifi)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + + "^ldo-v(xo22|emc|mc|sim1|sim2|sram-others|sram-proc|dram|usb33)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + +additionalProperties: false + +examples: + - | + pmic { + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name = "vproc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + mt6357_vcore_reg: buck-vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + mt6357_vmodem_reg: buck-vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + }; + mt6357_vs1_reg: buck-vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + mt6357_vpa_reg: buck-vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-ramp-delay = <50000>; + regulator-enable-ramp-delay = <220>; + }; + mt6357_vfe28_reg: ldo-vfe28 { + compatible = "regulator-fixed"; + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vxo22_reg: ldo-vxo22 { + regulator-name = "vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2400000>; + regulator-enable-ramp-delay = <110>; + }; + mt6357_vrf18_reg: ldo-vrf18 { + compatible = "regulator-fixed"; + regulator-name = "vrf18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <110>; + }; + mt6357_vrf12_reg: ldo-vrf12 { + compatible = "regulator-fixed"; + regulator-name = "vrf12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <110>; + }; + mt6357_vefuse_reg: ldo-vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vcn33_bt_reg: ldo-vcn33-bt { + regulator-name = "vcn33-bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vcn33_wifi_reg: ldo-vcn33-wifi { + regulator-name = "vcn33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vcn28_reg: ldo-vcn28 { + compatible = "regulator-fixed"; + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vcn18_reg: ldo-vcn18 { + compatible = "regulator-fixed"; + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vcama_reg: ldo-vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vcamd_reg: ldo-vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vcamio_reg: ldo-vcamio18 { + compatible = "regulator-fixed"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vldo28_reg: ldo-vldo28 { + regulator-name = "vldo28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vsram_others_reg: ldo-vsram-others { + regulator-name = "vsram-others"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + mt6357_vsram_proc_reg: ldo-vsram-proc { + regulator-name = "vsram-proc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + mt6357_vaux18_reg: ldo-vaux18 { + compatible = "regulator-fixed"; + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vaud28_reg: ldo-vaud28 { + compatible = "regulator-fixed"; + regulator-name = "vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vio28_reg: ldo-vio28 { + compatible = "regulator-fixed"; + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vio18_reg: ldo-vio18 { + compatible = "regulator-fixed"; + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + }; + mt6357_vdram_reg: ldo-vdram { + regulator-name = "vdram"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <3300>; + }; + mt6357_vmc_reg: ldo-vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + mt6357_vmch_reg: ldo-vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + mt6357_vemc_reg: ldo-vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + regulator-always-on; + }; + mt6357_vsim1_reg: ldo-vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vsim2_reg: ldo-vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + mt6357_vibr_reg: ldo-vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + }; + }; +... From patchwork Tue Nov 8 18:43:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 623510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF8EEC43217 for ; Tue, 8 Nov 2022 18:44:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233326AbiKHSow (ORCPT ); Tue, 8 Nov 2022 13:44:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232323AbiKHSoX (ORCPT ); Tue, 8 Nov 2022 13:44:23 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 878011FCD0 for ; Tue, 8 Nov 2022 10:44:18 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id o4so22448089wrq.6 for ; Tue, 08 Nov 2022 10:44:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=U4S2wIE6tyE7Z7qbLSq9JMEZ2ArGmgl84IUzu0C5hxo=; b=Y18ug5W0xJ8M2ZFE/O6Dml7V2y527QV4+8AI560P/BOLhBwON5i0Tw/UMHtkCbl2nP Xe5PsLzdW5Qvg08vLvDU3C3XoSuvti5dZy2kWVEjEQqr1c6hJ/mzKvXE49LTiYnWl53d KY7FpivWfmO47FbSByagIKOeEy1qklqwB9lzCzzg66oJeb5MX+TMKQfrB+4S2s3NdLfM tLBVh6xDA2/STz36yzH8SgtliR4TiekMByVoHtCWDF9O+4Ao9aRAb8RGL/CkLBD2QPYH kF2BnyIy9128m0WtWDR5K2nXao38GXXT6fsJvas3c2QsvTqUnApeNS5fZIWsm6/wYTnd p8mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U4S2wIE6tyE7Z7qbLSq9JMEZ2ArGmgl84IUzu0C5hxo=; b=pxlKaxTERUd6HJ9PoZo+AFNI8HxYUNLVSvQTaJdnNUkQx2lny2cCqFC/XWfJ4B3m04 vyABlbnyf5QLSC4pPph7ZMlkcj5KdABILTUF8odltvKm+MJiuYa4StDpypf0lrkhtStQ ss/ubkOVnL3lmokP0bOPcBfVcSTZAJrLyUDq5jr4MdVyIJmGtBPwyM0ppdXj7gNA7Y3H fr61hO9jZsR1kgIPsWHU7U2xBtlvQ/qw/Ah7qACrZQcVsCTrBeuzOyykM6yU0Ltzjznd 2PE4LUTX9fNGouLEOHq900Hegu6LP6tYSTu3zrzqH3U62zttkZMRlYJBaQ+FoXZU7oKO WnVw== X-Gm-Message-State: ACrzQf11hJnPSLv7sbtvw1+6yeuwfQyE14+lwtYS3FwOTOlVrMjZ4CwY PY8djIXfu7ZQ1aDXAuPhgDe6GussbyJQAdxdpRM= X-Google-Smtp-Source: AMsMyM5Ccq1UQUqi9rNjGygn/pMbp/xasjQS+U+T8va1YRV/PnQrpGPJoYqD4qXFi+5S/YCMWmNHOg== X-Received: by 2002:adf:f701:0:b0:236:e2b2:3b69 with SMTP id r1-20020adff701000000b00236e2b23b69mr27104551wrp.532.1667933056836; Tue, 08 Nov 2022 10:44:16 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:16 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:39 +0100 Subject: [PATCH v4 4/9] dt-bindings: mfd: mediatek: Add bindings for MT6357 PMIC MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-4-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3744; i=amergnat@baylibre.com; h=from:subject:message-id; bh=MbwBHR/2mMa0XKDOyJjMyD4H+RezYnxtaWTa6yRYsv8=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN6aU0sSWGEnsfMfHfVFyHyKDwvQ8KraqhxKnN6 R4u3soWJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjegAKCRArRkmdfjHURYtbEA C7GlgDFkDrcsYCJ5KKJkexnAlem/nnnMTjuS7nXgDPhq1edcxjZdL0TxW/XaCExibNMtC6/gajNxxB gxws2eBOERFMjzVOHjUdh2xNklErHnuBEWqjh7FKRCsUVkQ9ydVNMbYwwmyA1tC3CU5HxQwQ7J8M4L VTQczexFohJ0+y0oG3OdKpx8qkyEDUtyhqb+urR5doCEaq/Ath0NAPwzukDiL04cg2UHpE8GJgoe+Q x/iXkZfw9gsCmAh9xnTH2uqO5mPjQXhTzIM5AmlvcJGAS9wVf8O1fZkDuHr+nGFeNKewCjxnzFXl/e BHn7VgUt6dBadMK7YHm3E2DXETA0badpK7r4LdHkNFCA+8K/751FS8TulQv8QDmh57WOm1wRA/HqPu 8RI74f1on4ucyZMQ7LS9GBlheWd4DQtFTgZtgfGoppwECLoDVAUM5+ptWLbcKcbqb8seDGxvEF08Cx EO2SI1Ev56nfBRRYZA0st/yVFto2P1HPRmhFewfzDRqoyQQQIpo+F1XTQWHaq/kGN1GMH8QkMy3bIC gPMpBfhhjX3RlL3H2pdRZPR/BYjodJoqQwg6NR72MxjnNd5GD7O6mHVhKjYjj/uue5MvLw2/sOlc/H TquTcrWAtBHpk7+1n//WvF6rwlY5O5NvVxHMNgYRNh89PK1ltQ0+Gi+wufmA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org Currently, almost all MT63XX PMIC are documented mfd/mt6397.txt. Unfortunately, the PMICs haven't always similar HW sub-features. To have a better human readable schema, I chose to make one PMIC schema to match the exact HW capabilities instead of convert mt6397.txt to mediatek,mt63xx.yaml and put a bunch of properties behind "if contain ... then ..." - add interrupt property - change property refs to match with new yaml documentation Signed-off-by: Alexandre Mergnat --- .../devicetree/bindings/mfd/mediatek,mt6357.yaml | 102 +++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml new file mode 100644 index 000000000000..7b421f21d3f5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6357 Multifunction Device Driver + +maintainers: + - Alexandre Mergnat + +description: | + MT6357 is a power management system chip containing 5 buck + converters and 29 LDOs. Supported features are audio codec, + USB battery charging, fuel gauge, RTC + + This is a multifunction device with the following sub modules: + - Regulator + - RTC + - Keys + + It is interfaced to host controller using SPI interface by a proprietary hardware + called PMIC wrapper or pwrap. This MFD is a child device of pwrap. + See the following for pwrap node definitions: + ../soc/mediatek/mediatek,pwrap.yaml + +properties: + compatible: + const: mediatek,mt6357 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + regulators: + type: object + $ref: ../regulator/mediatek,mt6357-regulator.yaml + description: + Child node that specify the regulator. + + rtc: + type: object + $ref: ../rtc/mediatek,mt6397-rtc.yaml + description: + Child node that specify the RTC. + + keys: + type: object + $ref: ../input/mediatek,pmic-keys.yaml + description: + Child node that specify the keys. + +required: + - compatible + - regulators + +additionalProperties: false + +examples: + - | + pwrap { + pmic { + compatible = "mediatek,mt6357"; + + interrupt-parent = <&pio>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name = "vproc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + // ... + + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + rtc { + compatible = "mediatek,mt6357-rtc"; + }; + + keys { + compatible = "mediatek,mt6357-keys"; + }; + }; + }; From patchwork Tue Nov 8 18:43:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 622797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3F83C4321E for ; Tue, 8 Nov 2022 18:44:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233829AbiKHSox (ORCPT ); Tue, 8 Nov 2022 13:44:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232355AbiKHSoX (ORCPT ); Tue, 8 Nov 2022 13:44:23 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F42922BE3 for ; Tue, 8 Nov 2022 10:44:19 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id w14so22410475wru.8 for ; Tue, 08 Nov 2022 10:44:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KxbWMbCkLf2CZt0JWp3FbnSlefS2q4v4vpwjT3uyBkQ=; b=nmGXyLUsErw5uIAa+fZqWW7kRk09fk1ngioE+3GczLTiN6c0YYI59Xtkr+zwE1RrIy yu/m++l3gmJif+U5lTi4dKbPeJZYbPyU2qVNUQ7tSG5N1v5+bCe1r9R4ksge+vbrT8HY QI7dL6axXXQH0kYwcKddUTWXrQV4n+y9xpUK06iu3usQLSlzu/+5T+hnnXSF8AdJN53T LL5fnEElA6eKD5c0qzuIT9u8U/5xU5Ma+8GFPDhO+yzLTu5pku25elH2Yz0aQxvDimk4 bo2IVBp02YYQCKc3CnAu16Jbh2PWiCZAjJyzk1mnNdFm06Lmwh2hyChR+TDHBX/mIFwD 13fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KxbWMbCkLf2CZt0JWp3FbnSlefS2q4v4vpwjT3uyBkQ=; b=HPG92exiSkYf9QSHXAp6B3hJ+x+jjjUURoIR33VbGd5TL10IHrxuTWBjrWfKG54n9O dY0bzYEvcn/1S2D4W2hfLu37a24yovQB2FTTJqAAKOUkXnaLdKdHuaQ+CQ2nEeyBdxPm wIWu2fswGXHWE0NNxZ0Fn4oNhN89YK8ucMIzsxKNq+J7zuyUJPrAJ3HNEF2hr2n3VReN BjVf4rSmjZkXh0x9pgAfrZzBe8ZWEqY0myNSuVNZv8CQsk0qJu8hDMGgcqXj4oH91W67 i7a6UJyjoGuCDyk/ReoMne/b/bw4W2kPahHIM1KH89fP14O8lwfE4BLOH+PKiLbIZpQd nPnA== X-Gm-Message-State: ACrzQf35AkMA5Hqsg6V542thiNXxVpPPoKq/1ywZc96WSo7RbYlEs8pK MfMjZK0g5c+OasXThd+5hiwXzjYQEUNf8+VQuEk= X-Google-Smtp-Source: AMsMyM4UXrchFzDtnHtEG890uxWtTUD5uXXk3PVb0j7isqdzlo5AMfehb75a3fDSvQoOPn8+pEtcbA== X-Received: by 2002:adf:ea10:0:b0:236:ec3e:869d with SMTP id q16-20020adfea10000000b00236ec3e869dmr25304812wrm.33.1667933057819; Tue, 08 Nov 2022 10:44:17 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:17 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:40 +0100 Subject: [PATCH v4 5/9] dt-bindings: soc: mediatek: convert pwrap documentation MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-5-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=9988; i=amergnat@baylibre.com; h=from:subject:message-id; bh=3vlZFWzs8N0acTLXMrSZvnl+PIo8Ay6uEyIXGvzMWuw=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN67MeFVNi9wj+YauXCOp5Adu3UBl+sqhO+iHXu EGGs7GyJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjegAKCRArRkmdfjHURY0xEA CkLBqbPGqeponCtdUBs1vuk3waC1p1QGY9X2mULKVA4gh7eWcuGINZBuREGCJVSjmlzmv78v7TroW/ PsJNRrs9z2skwt2xqLuxjF44lfENDWV3FLLZmi8i4QWzFF/sRs7sbT6gvrki4fhu0R/oFLznVUSsnE Zg4fi6fWvLXPtKBx7f3V6wYSiRAYqGZitoY9L2V1cK+FEYnmmSXJ3ia9u6WtiNO1Q53vTHPJl2VTop KMxigrUL+lBdA06UYyLKdiTGvViDRSKTWVmUJo4p3+JfwvOYkl2cc6VDCrpc9gCsUcxxxfXNhyyhwJ bbOdLoY0Cvewm4nQzC2DwkGnK5iN/Nir0eGd7jX2sWy1glSA/p6sHGlfHMwdXWb4wFALQGwNw7YC6W 2Lyp/70L2CYyGIH3cW6pt3D2g6alrEol+OwwfR75GLkcu4hayI8lntqg56xuflPMvqfCnGHiLwe72J ObnD4QXFgVVcIGSCRiJiJRzOkt6kbjFVoR6zOVNfx43bYDzNPjhYCHyG2h/l8gukZanxS4jGaluIH0 QeU47usGChNiEK5EdgYyKrXwX/AHSc3qPCjyRt94iS/pmKPuu59nPSxicp6PnbAEkvNvJ6DoYUmReo icZtN66EmhDEdoK4GkA9ptrNtaEQITWO1CbLAfQSEwtBFiDiQdMatyVpcvHg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org - Convert soc/mediatek/pwrap.txt to soc/mediatek/mediatek,pwrap.yaml - MT8365 SoC has 2 additional clock items and a yaml schema for its PMIC - Remove pwrap.txt file Signed-off-by: Alexandre Mergnat --- .../devicetree/bindings/leds/leds-mt6323.txt | 2 +- Documentation/devicetree/bindings/mfd/mt6397.txt | 2 +- .../bindings/soc/mediatek/mediatek,pwrap.yaml | 158 +++++++++++++++++++++ .../devicetree/bindings/soc/mediatek/pwrap.txt | 75 ---------- 4 files changed, 160 insertions(+), 77 deletions(-) diff --git a/Documentation/devicetree/bindings/leds/leds-mt6323.txt b/Documentation/devicetree/bindings/leds/leds-mt6323.txt index 45bf9f7d85f3..73353692efa1 100644 --- a/Documentation/devicetree/bindings/leds/leds-mt6323.txt +++ b/Documentation/devicetree/bindings/leds/leds-mt6323.txt @@ -9,7 +9,7 @@ MT6323 PMIC hardware. For MT6323 MFD bindings see: Documentation/devicetree/bindings/mfd/mt6397.txt For MediaTek PMIC wrapper bindings see: -Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml Required properties: - compatible : Must be "mediatek,mt6323-led" diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt index 79aaf21af8e9..3bee4a42555d 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -13,7 +13,7 @@ MT6397/MT6323 is a multifunction device with the following sub modules: It is interfaced to host controller using SPI interface by a proprietary hardware called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap. See the following for pwarp node definitions: -../soc/mediatek/pwrap.txt +../soc/mediatek/mediatek,pwrap.yaml This document describes the binding for MFD device and its sub module. diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml new file mode 100644 index 000000000000..fe83458b801a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek PMIC Wrapper + +maintainers: + - Alexandre Mergnat + +description: | + On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface + is not directly visible to the CPU, but only through the PMIC wrapper + inside the SoC. The communication between the SoC and the PMIC can + optionally be encrypted. Also a non standard Dual IO SPI mode can be + used to increase speed. + + IP Pairing + + On MT8135 the pins of some SoC internal peripherals can be on the PMIC. + The signals of these pins are routed over the SPI bus using the pwrap + bridge. In the binding description below the properties needed for bridging + are marked with "IP Pairing". These are optional on SoCs which do not support + IP Pairing + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-pwrap + - mediatek,mt6765-pwrap + - mediatek,mt6779-pwrap + - mediatek,mt6797-pwrap + - mediatek,mt6873-pwrap + - mediatek,mt7622-pwrap + - mediatek,mt8135-pwrap + - mediatek,mt8173-pwrap + - mediatek,mt8183-pwrap + - mediatek,mt8188-pwrap + - mediatek,mt8365-pwrap + - mediatek,mt8516-pwrap + - items: + - enum: + - mediatek,mt8186-pwrap + - mediatek,mt8195-pwrap + - const: syscon + + reg: + minItems: 1 + items: + - description: PMIC wrapper registers (mandatory) + - description: IP pairing registers + + reg-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + interrupts: + maxItems: 1 + description: IRQ for pwrap in SOC + + clocks: true + + clock-names: true + + resets: + minItems: 1 + items: + - description: PMIC wrapper reset + - description: IP pairing reset + + reset-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + pmic: + type: object + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8365-pwrap + then: + properties: + pmic: + $ref: /schemas/mfd/mediatek,mt6357.yaml# + + clocks: + items: + - description: SPI bus clock + - description: Main module clock + - description: System module clock + - description: Timer module clock + clock-names: + items: + - const: spi + - const: wrap + - const: sys + - const: tmr + else: + properties: + pmic: + description: | + List of child nodes that specify the regulators. + See ../../mfd/mt6397.txt for more details. + + clocks: + items: + - description: SPI bus clock + - description: Main module clock + clock-names: + items: + - const: spi + - const: wrap + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +additionalProperties: true + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pwrap@1000f000 { + compatible = "mediatek,mt8135-pwrap"; + reg = <0 0x1000f000 0 0x1000>, <0 0x11017000 0 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "wrap"; + + pmic { + compatible = "mediatek,mt6397"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt deleted file mode 100644 index 8424b93c432e..000000000000 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ /dev/null @@ -1,75 +0,0 @@ -MediaTek PMIC Wrapper Driver - -This document describes the binding for the MediaTek PMIC wrapper. - -On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface -is not directly visible to the CPU, but only through the PMIC wrapper -inside the SoC. The communication between the SoC and the PMIC can -optionally be encrypted. Also a non standard Dual IO SPI mode can be -used to increase speed. - -IP Pairing - -on MT8135 the pins of some SoC internal peripherals can be on the PMIC. -The signals of these pins are routed over the SPI bus using the pwrap -bridge. In the binding description below the properties needed for bridging -are marked with "IP Pairing". These are optional on SoCs which do not support -IP Pairing - -Required properties in pwrap device node. -- compatible: - "mediatek,mt2701-pwrap" for MT2701/7623 SoCs - "mediatek,mt6765-pwrap" for MT6765 SoCs - "mediatek,mt6779-pwrap" for MT6779 SoCs - "mediatek,mt6797-pwrap" for MT6797 SoCs - "mediatek,mt6873-pwrap" for MT6873/8192 SoCs - "mediatek,mt7622-pwrap" for MT7622 SoCs - "mediatek,mt8135-pwrap" for MT8135 SoCs - "mediatek,mt8173-pwrap" for MT8173 SoCs - "mediatek,mt8183-pwrap" for MT8183 SoCs - "mediatek,mt8186-pwrap" for MT8186 SoCs - "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs - "mediatek,mt8195-pwrap" for MT8195 SoCs - "mediatek,mt8365-pwrap" for MT8365 SoCs - "mediatek,mt8516-pwrap" for MT8516 SoCs -- interrupts: IRQ for pwrap in SOC -- reg-names: "pwrap" is required; "pwrap-bridge" is optional. - "pwrap": Main registers base - "pwrap-bridge": bridge base (IP Pairing) -- reg: Must contain an entry for each entry in reg-names. -- clock-names: Must include the following entries: - "spi": SPI bus clock - "wrap": Main module clock - "sys": System module clock (for MT8365 SoC) - "tmr": Timer module clock (for MT8365 SoC) -- clocks: Must contain an entry for each entry in clock-names. - -Optional properities: -- reset-names: Some SoCs include the following entries: - "pwrap" - "pwrap-bridge" (IP Pairing) -- resets: Must contain an entry for each entry in reset-names. -- pmic: Using either MediaTek PMIC MFD as the child device of pwrap - See the following for child node definitions: - Documentation/devicetree/bindings/mfd/mt6397.txt - or the regulator-only device as the child device of pwrap, such as MT6380. - See the following definitions for such kinds of devices. - Documentation/devicetree/bindings/regulator/mt6380-regulator.txt - -Example: - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8135-pwrap"; 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:18 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:41 +0100 Subject: [PATCH v4 6/9] arm64: dts: mt6358: change node names MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-6-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1271; i=amergnat@baylibre.com; h=from:subject:message-id; bh=c7wPKy75bT8ebg54aEIMfSMAkZtNftilP/SW804aUPE=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN6jeuBbx1egeCFBr+5jX9bet3A4Pwleqhx62Kq W/Ijc4GJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjegAKCRArRkmdfjHURf3LEA CF1Xpb/hnOAfCPOPFX4/cEosoj8b+gWVDOXucqf5mES7uM7fB/63fjBR64lOwygfpfgtD8mQVJZajm 4RmqRjRtQDXMLCV9vdTAc9WXJuMkgmy0VSFbCccqD1ATI4Fx1Wj48QHPoHL0HMjvUKe11ZQGMVi94g Au8t43WCgXn1kfSFPHZZF4vfevlovrT7DrAe8ySWJ8LRFc4KM3l6oB2+JFJzVQzip01X0mYaqIhSDN I+ZRUVKLKpriTI/IHkHySXgupWVds7RJnHYDKanWCDuS8zHGg/mNsqll3vnikVMl6+RfYtNabJOx4g FuTjd8+YdnDQwgLwGuPc+H6O34JCcjw1OA/DWu3u0j3mM9YUAaair3dPPISfqANCoAgAhSV0enbswd yvBSqmU/3PI2ybS9DAGQdKbkBPIq/qlbIqVNvtBnu3t32kvkYg8jVuYSgTLipUMTkmFzQ4bnNeA2pa vAs83nMOD1ppd5VVy3SKFkHAVZybS0TcjftKjFxNKlX5Hzp+PLZjOjRXmZQ6g6xHvmjJ7De3u90Kh6 iHHokLSky59s3h6UGCyvospzR+BtUN4jOvbi/50qtCvv8L90FrBrc9EMxmU0bWmwxrA1RJ8dtaCHNn xU45lFbJdLN2m/z2bcgC0imzHEbkPA853MdanRw8fT2NPnLXopYqhb9XIsZg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org - Change the node name from "mt6358" to "pmic" to be consistent with mediatek,pwrap.yaml documentation. - Change the node name from "mt6358rtc" to "rtc" to be consistent with mediatek,mt6397-rtc.yaml documentation. - Change the node name from "mt6358keys" to "keys" to be consistent with mediatek,pmic-keys.yaml documentation. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt6358.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi index 98f3b0e0c9f6..b605313bed99 100644 --- a/arch/arm64/boot/dts/mediatek/mt6358.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi @@ -5,7 +5,7 @@ #include &pwrap { - pmic: mt6358 { + pmic: pmic { compatible = "mediatek,mt6358"; interrupt-controller; interrupt-parent = <&pio>; @@ -355,11 +355,11 @@ mt6358_vsim2_reg: ldo_vsim2 { }; }; - mt6358rtc: mt6358rtc { + mt6358rtc: rtc { compatible = "mediatek,mt6358-rtc"; }; - mt6358keys: mt6358keys { + mt6358keys: keys { compatible = "mediatek,mt6358-keys"; power { linux,keycodes = ; From patchwork Tue Nov 8 18:43:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 623508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32F44C4321E for ; Tue, 8 Nov 2022 18:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231665AbiKHSpB (ORCPT ); Tue, 8 Nov 2022 13:45:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232603AbiKHSof (ORCPT ); Tue, 8 Nov 2022 13:44:35 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE2FA54B3B for ; Tue, 8 Nov 2022 10:44:21 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id j5-20020a05600c410500b003cfa9c0ea76so4249860wmi.3 for ; Tue, 08 Nov 2022 10:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=L20WZDfB4Ry2n4XJgPN1jHb78hlwsc6RiwrnFa7B3l8=; b=X86Oj3VmY3z3bN2okv+TrWhSiG93o1+Bir6b0bYrqyp135B2umDW7xqcJkVEhTmZ/Z MB+gadlvP0VfJtGVAp5at1NLQlI/Q5dFTB2ZeFTNY9KhKetvTIzlDVitWUM/bzArLYWq tuM8IJxSMFTMKRa6NzZ+vshthnbkHEe6spYuIXbSIK8AiFYtPY+XM66rxFlOrBk9ommT Uye0K15SbIfzFfgRHXGDJME3j3k+sssu/h0VH0g8kQGIzBB9/CtO80Rxjeb1Ckrnt2r7 WmEozoJR+lxVFcwH36Cba8WYcd9xCx14eNO73I9vB951UVnhLzERbJLmq7UxHPe83dGl iQKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L20WZDfB4Ry2n4XJgPN1jHb78hlwsc6RiwrnFa7B3l8=; b=qsJe1kQbuSRkaPAeUcBIjSYLsuABSYBBkkAFHemy/eTZMc9rMZ9GZnshOg5dGLg5fr MToAEpyGAFIAZyKzNAKpSQkexVNsvKOasIz+TyBPvIlvBKbo0t5p/qn4ayxm+FEiTWiX a4Cs7C6qz7OFrbZADENMwAUN6P1XI1xoLLZCgbrIH4b3934zoUbD6gilzzEOSHa1/0Yv 8nxBw3W3/UikdWzSbFrYvDVfCxOzEFOCZ7lShaBMFqiJ7JylVvnCW8a7JA3AMW0sxfKv RF+AGDwT6QP6inlOGobR24WvJHPKE75j37ysRo0k7/dx/ww3KUs4nJTH25mzo6p9NqZs FwFg== X-Gm-Message-State: ACrzQf1CTmEHDta7KE9FgwcehDDznWNbDxQN2CE8gb6Rnvx3nG4kR1K/ tXV98Hs6Zl+ZE7BTjZXqge05QTP6wikLT9I6emg= X-Google-Smtp-Source: AMsMyM5AarrbeV++fniByKtEg7T79sU7xpN3t7OCokfHeIAVTF2NddszH+lHi7AY22w1kclM/wF7Ng== X-Received: by 2002:a05:600c:33a5:b0:3cf:6fd1:d94b with SMTP id o37-20020a05600c33a500b003cf6fd1d94bmr34657965wmp.52.1667933060018; Tue, 08 Nov 2022 10:44:20 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:19 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:42 +0100 Subject: [PATCH v4 7/9] arm64: dts: mt8173: change node name MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-7-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1290; i=amergnat@baylibre.com; h=from:subject:message-id; bh=GBaNKrSWOOj3IIbimro7kSOdhFcUdE4vLaUrLB+TgIA=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN6jIHrLK5ba/9RboyYvb9OrGAYOnQPvqiWbBzU up+6X4SJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjegAKCRArRkmdfjHURRjvD/ 9UtpSjMXT2IvEQImHV2/Je0WrnfGK0wXBLP6+2wFX7Cm13Kz1MYbkybczKtN/pJEkMKc4Wpyt5WNuH W85VLgZ9dVoYeWP9jbas1EqFtF/1iuKRNiEM2Fy4PpZ3Qx35kqkdFGsOjGzWeX9e+wevdfdOCAfOCJ x+UDnQjULKhVTzyg4oTTIcas78RdGgiVyTKjCt5ZHfbAGkSk+wAjaR9igJ/6YR58lQLolRGekMbu94 irH5Y7fhDOqZ61gZXpMXBjYSbs7iRzNrBlYhmcPIC1WZMbrpQx7n/d8JiuY3eS+1bdBxi3TBuf9u43 7uYveEt/BKSarifYxJVE14YO4XMSC7R5mRcCYx32dYzWhur5g27wSN03f35EDjI+zdnlkfUFx1q/lZ vkOmirajHD3XiI4urH1wqBdpLUuoJm41YYtvCd2B6VAPEJ9md4r9Ko7IXkvR1BZ+3r7GRToX7YrRLt Sf2HdzPmmVXsLC1yt1F/UGwXWqKjLfWiT4FRaN/WTgqLYXTarDtLO5UT2ul1KbrLYvwtuc6OWhbXEc J565kVwabYoFdgVCCHmaPSoAUOYwRCshCzbc6cpLDfDKppLJKN1MWzcmsC9K8YLUieuUeJoVvT9KAe m5oP/cT9MvTgJjnnKg2Gg0hr/dX7fJ6JjvgG96BiUj+aTrYaei5RPPCnnwEA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org - Change the node name from "mt6397" to "pmic" to be consistent with mediatek,pwrap.yaml documentation. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index e21feb85d822..a8f5c48e1782 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -913,7 +913,7 @@ &pwm0 { }; &pwrap { - pmic: mt6397 { + pmic: pmic { compatible = "mediatek,mt6397"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 0b5f154007be..755df5694234 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -300,7 +300,7 @@ &pwrap { /* Only MT8173 E1 needs USB power domain */ power-domains = <&spm MT8173_POWER_DOMAIN_USB>; - pmic: mt6397 { + pmic: pmic { compatible = "mediatek,mt6397"; interrupt-parent = <&pio>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; From patchwork Tue Nov 8 18:43:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 622795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BD46C43217 for ; Tue, 8 Nov 2022 18:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234536AbiKHSpF (ORCPT ); Tue, 8 Nov 2022 13:45:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232996AbiKHSov (ORCPT ); Tue, 8 Nov 2022 13:44:51 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2451E5800D for ; Tue, 8 Nov 2022 10:44:23 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id m7-20020a05600c090700b003cf8a105d9eso9652664wmp.5 for ; Tue, 08 Nov 2022 10:44:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WD8OECtvZANLufee1Z8MXmgvWqbSudvErIpI5NaxR8Y=; b=JHaboBMpGP9Sjw0A64jgebBkyoB9eu8SYb4mJCSIgEZtFKJjJBqIZTzZaFt+EBNHNB 7DBTilb2neP6EeApdnhQrrfty5bUa6i3RirPzCa8OqFLGBnQ8Rs1r5HeLIX3wStNxNXO GRKEztCSLuHxwKDjDiCmaQ69a2dYA5JsH33r8syXWPWcrR7Yw3cmMWOEN5wMqWggQOLf VDVRNDiWgAQKz5a+sWbfmXFm1rmb4fMTyKtKa8nXAjfBDYcO8Sj3i8PFOZkTePC4V9WC aImatUAuYmZFTVCbFhcKxD1WY8FrNVst/ljh4PXWReDBi6nog1KLgZy3oFcmaV3WcwRk IlRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WD8OECtvZANLufee1Z8MXmgvWqbSudvErIpI5NaxR8Y=; b=BEJH0wW0Vntm0Eaktl52DzCRiUa+PMiffbJBM9vzVBvvxVupFi0c2kfebhqyVsuwR+ wU6uWOVt+w87zUEJWMY8e2xpI8n8AcF1qgJQ3qOLTZATUOG9mnay+JWkwv7dlyYPffLc m/xHuK9ybEaDaOLktqOV3aLMA8fY5UAgTiQX55Dq8RPBt8YurWU0g3TGKQci/TG32niT wF9Bq/hu6b4bWfVME3J/RdyF0pI7AlsvJ6QZeG85wwHCxG5Q8aPtXR2Ay2wvpXo1FaB7 gOhZgUULh0mCX0BYP0SiDbT6gS/YtT0vtNWar8vzrjQw3A9jf8Hm6uxTs0g7pP/og6XH 8aHg== X-Gm-Message-State: ACrzQf1N4HuLXQidCP973BtD1VHT5WnWqTfdKL9hkUOf16mVTOjsqSoc M2z1y23l9k9ceayPIo7YeKxIiCKfJ1M2jyiodtQ= X-Google-Smtp-Source: AMsMyM6Yxarq9N5ZGy6/lsCnB2E2r8WnDpe5o/opaPbwui+K/c8EjWp0lOK2fzoz2xEeOz4l9zL6aw== X-Received: by 2002:a05:600c:3184:b0:3cf:7173:bc35 with SMTP id s4-20020a05600c318400b003cf7173bc35mr33086410wmp.165.1667933061240; Tue, 08 Nov 2022 10:44:21 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:20 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:43 +0100 Subject: [PATCH v4 8/9] regulator: add mt6357 regulator MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-8-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=15569; i=amergnat@baylibre.com; h=from:subject:message-id; bh=y+Du5lFtm/T6TSCc8kfuVvBdv77zZwOX0ZLh5nmNKVM=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN7MrgFKwH9LkSRlee4kre847S371MyrZM/j9aY 8/KJe1qJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjewAKCRArRkmdfjHURWb/D/ 9LQtS6fodkT3K24Vu4j2acLDColsWL7nSAEsGd1K6Ro07TmiyBkdKePV+5x9m4E3SfYhgeZ+zQFtFb pODqWCRLDT1Y2R47/l9rXZ8+WhH5/SCNww76G0cfaGo/AMVjhMQJ1sUewWCJm/xwcrbXtZQOLJTXta jum1W6/LP4Lu9R3QeOTQtYQTAjVJQ6mBGnVUvcBpzQjTJdEGHx2oQuvxQzIr6lpkOX8r8icAcVrDwG mCe4rnyPpXZClq+HJ52jgsfX/vrkp4OcFkj2E0iwdCaw6kkHCqJqUUZpwxLIPBUcb2KcXrh8KDMHmT VoDsSepM0tVPbyieVEA+t7bMiT20YE4INGGI4lOs89z5hRq2r8H3Il/ghb+2NZl4MjVpKJS5fAYTz3 zoT6gDF7QBlK/KFq/GatN2P7WFfn0jYbu0v0Mgj6DK47RMR2O4GDdYo/L0ib+ydfB4dKp3U8akJRtX /sjk9lUgNvaOnMKok9gSPv08P5BE/0ph77MIBsQ0nSsLuQ+bezUxD9LAlJ2kuxZ7R3vrC7a9qDLEyk R/qQMkE/QZArABOLVUS5XmCvFh8hD4y53JBaEOhaqZ+7whtkxjQYmkOOWX+G/SnQrsv/sMPf+Mn3O8 Jbitngt1Zk4DwdjfcJzTqQ/dAE7kCMS7Di82xEgBCEN71/LQJDL5CVEyC6cg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org From: Fabien Parent Add regulator driver for the MT6357 PMIC. Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6357-regulator.c | 453 +++++++++++++++++++++++++++++ include/linux/regulator/mt6357-regulator.h | 51 ++++ 4 files changed, 514 insertions(+) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 070e4403c6c2..a659a57438f4 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -805,6 +805,15 @@ config REGULATOR_MT6332 This driver supports the control of different power rails of device through regulator interface +config REGULATOR_MT6357 + tristate "MediaTek MT6357 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6357 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6358 tristate "MediaTek MT6358 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 5962307e1130..e4d67b7b1af6 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o obj-$(CONFIG_REGULATOR_MT6331) += mt6331-regulator.o obj-$(CONFIG_REGULATOR_MT6332) += mt6332-regulator.o +obj-$(CONFIG_REGULATOR_MT6357) += mt6357-regulator.o obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o obj-$(CONFIG_REGULATOR_MT6359) += mt6359-regulator.o obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o diff --git a/drivers/regulator/mt6357-regulator.c b/drivers/regulator/mt6357-regulator.c new file mode 100644 index 000000000000..4e5aee47392c --- /dev/null +++ b/drivers/regulator/mt6357-regulator.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2022 MediaTek Inc. +// Copyright (c) 2022 BayLibre, SAS. +// Author: Chen Zhong +// Author: Fabien Parent +// Author: Alexandre Mergnat +// +// Based on mt6397-regulator.c +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * MT6357 regulators' information + * + * @desc: standard fields of regulator description. + * @da_vsel_reg: Monitor register for query buck's voltage. + * @da_vsel_mask: Mask for query buck's voltage. + */ +struct mt6357_regulator_info { + struct regulator_desc desc; + u32 da_vsel_reg; + u32 da_vsel_mask; +}; + +#define MT6357_BUCK(match, vreg, min, max, step, \ + volt_ranges, vosel_reg, vosel_mask, _da_vsel_mask) \ +[MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .regulators_node = "regulators", \ + .ops = &mt6357_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6357_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel_reg, \ + .vsel_mask = vosel_mask, \ + .enable_reg = MT6357_BUCK_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_BUCK_##vreg##_DBG0, \ + .da_vsel_mask = vosel_mask, \ +} + +#define MT6357_LDO(match, vreg, ldo_volt_table, \ + enreg, vosel, vosel_mask) \ +[MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .regulators_node = "regulators", \ + .ops = &mt6357_volt_table_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6357_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ +} + +#define MT6357_LDO1(match, vreg, min, max, step, volt_ranges, \ + enreg, vosel, vosel_mask) \ +[MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .regulators_node = "regulators", \ + .ops = &mt6357_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6357_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_LDO_##vreg##_DBG0, \ + .da_vsel_mask = 0x7f00, \ +} + +#define MT6357_REG_FIXED(match, vreg, volt) \ +[MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .regulators_node = "regulators", \ + .ops = &mt6357_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6357_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = MT6357_LDO_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + .min_uV = volt, \ + }, \ +} + +/** + * mt6357_get_buck_voltage_sel - get_voltage_sel for regmap users + * + * @rdev: regulator to operate on + * + * Regulators that use regmap for their register I/O can set the + * da_vsel_reg and da_vsel_mask fields in the info structure and + * then use this as their get_voltage_vsel operation. + */ +static int mt6357_get_buck_voltage_sel(struct regulator_dev *rdev) +{ + int ret, regval; + struct mt6357_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val); + if (ret != 0) { + dev_err(&rdev->dev, + "Failed to get mt6357 Buck %s vsel reg: %d\n", + info->desc.name, ret); + return ret; + } + + regval &= info->da_vsel_mask; + regval >>= ffs(info->da_vsel_mask) - 1; + + return regval; +} + +static const struct regulator_ops mt6357_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = mt6357_get_buck_voltage_sel, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, +}; + +static const struct regulator_ops mt6357_volt_table_ops = { + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, +}; + +static const struct regulator_ops mt6357_volt_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, +}; + +static const int vxo22_voltages[] = { + 2200000, + 0, + 2400000, +}; + +static const int vefuse_voltages[] = { + 1200000, + 1300000, + 1500000, + 0, + 1800000, + 0, + 0, + 0, + 0, + 2800000, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vcn33_voltages[] = { + 0, + 3300000, + 3400000, + 3500000, +}; + +static const int vcama_voltages[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2500000, + 0, + 0, + 2800000, +}; + +static const int vcamd_voltages[] = { + 0, + 0, + 0, + 0, + 1000000, + 1100000, + 1200000, + 1300000, + 0, + 1500000, + 0, + 0, + 1800000, +}; + +static const int vldo28_voltages[] = { + 0, + 2800000, + 0, + 3000000, +}; + +static const int vdram_voltages[] = { + 0, + 1100000, + 1200000, +}; + +static const int vsim_voltages[] = { + 0, + 0, + 0, + 1700000, + 1800000, + 0, + 0, + 0, + 2700000, + 0, + 0, + 3000000, + 3100000, +}; + +static const int vibr_voltages[] = { + 1200000, + 1300000, + 1500000, + 0, + 1800000, + 2000000, + 0, + 0, + 0, + 2800000, + 0, + 3000000, + 0, + 3300000, +}; + +static const int vmc_voltages[] = { + 0, + 0, + 0, + 0, + 1800000, + 0, + 0, + 0, + 0, + 0, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vmch_voltages[] = { + 0, + 0, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vemc_voltages[] = { + 0, + 0, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vusb_voltages[] = { + 0, + 0, + 0, + 3000000, + 3100000, +}; + +static const struct linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(518750, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct linear_range buck_volt_range4[] = { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 12500), +}; + +/* The array is indexed by id(MT6357_ID_XXX) */ +static struct mt6357_regulator_info mt6357_regulators[] = { + /* Bucks */ + MT6357_BUCK("buck-vcore", VCORE, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VCORE_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vproc", VPROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VPROC_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vmodem", VMODEM, 500000, 1293750, 6250, + buck_volt_range2, MT6357_BUCK_VMODEM_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vpa", VPA, 500000, 3650000, 50000, + buck_volt_range3, MT6357_BUCK_VPA_CON1, 0x3f, 0x3f), + MT6357_BUCK("buck-vs1", VS1, 1200000, 2787500, 12500, + buck_volt_range4, MT6357_BUCK_VS1_ELR0, 0x7f, 0x7f), + + /* LDOs */ + MT6357_LDO("ldo-vcama", VCAMA, vcama_voltages, + MT6357_LDO_VCAMA_CON0, MT6357_VCAMA_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vcamd", VCAMD, vcamd_voltages, + MT6357_LDO_VCAMD_CON0, MT6357_VCAMD_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vcn33-bt", VCN33_BT, vcn33_voltages, + MT6357_LDO_VCN33_CON0_0, MT6357_VCN33_ANA_CON0, 0x300), + MT6357_LDO("ldo-vcn33-wifi", VCN33_WIFI, vcn33_voltages, + MT6357_LDO_VCN33_CON0_1, MT6357_VCN33_ANA_CON0, 0x300), + MT6357_LDO("ldo-vdram", VDRAM, vdram_voltages, + MT6357_LDO_VDRAM_CON0, MT6357_VDRAM_ELR_2, 0x300), + MT6357_LDO("ldo-vefuse", VEFUSE, vefuse_voltages, + MT6357_LDO_VEFUSE_CON0, MT6357_VEFUSE_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vemc", VEMC, vemc_voltages, + MT6357_LDO_VEMC_CON0, MT6357_VEMC_ANA_CON0, 0x700), + MT6357_LDO("ldo-vibr", VIBR, vibr_voltages, + MT6357_LDO_VIBR_CON0, MT6357_VIBR_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vldo28", VLDO28, vldo28_voltages, + MT6357_LDO_VLDO28_CON0_0, MT6357_VLDO28_ANA_CON0, 0x300), + MT6357_LDO("ldo-vmc", VMC, vmc_voltages, + MT6357_LDO_VMC_CON0, MT6357_VMC_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vmch", VMCH, vmch_voltages, + MT6357_LDO_VMCH_CON0, MT6357_VMCH_ANA_CON0, 0x700), + MT6357_LDO("ldo-vsim1", VSIM1, vsim_voltages, + MT6357_LDO_VSIM1_CON0, MT6357_VSIM1_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vsim2", VSIM2, vsim_voltages, + MT6357_LDO_VSIM2_CON0, MT6357_VSIM2_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vusb33", VUSB33, vusb_voltages, + MT6357_LDO_VUSB33_CON0_0, MT6357_VUSB33_ANA_CON0, 0x700), + MT6357_LDO("ldo-vxo22", VXO22, vxo22_voltages, + MT6357_LDO_VXO22_CON0, MT6357_VXO22_ANA_CON0, 0x300), + + MT6357_LDO1("ldo-vsram-proc", VSRAM_PROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_PROC_CON0, + MT6357_LDO_VSRAM_CON0, 0x7f00), + MT6357_LDO1("ldo-vsram-others", VSRAM_OTHERS, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_OTHERS_CON0, + MT6357_LDO_VSRAM_CON1, 0x7f00), + + MT6357_REG_FIXED("ldo-vaud28", VAUD28, 2800000), + MT6357_REG_FIXED("ldo-vaux18", VAUX18, 1800000), + MT6357_REG_FIXED("ldo-vcamio18", VCAMIO, 1800000), + MT6357_REG_FIXED("ldo-vcn18", VCN18, 1800000), + MT6357_REG_FIXED("ldo-vcn28", VCN28, 2800000), + MT6357_REG_FIXED("ldo-vfe28", VFE28, 2800000), + MT6357_REG_FIXED("ldo-vio18", VIO18, 1800000), + MT6357_REG_FIXED("ldo-vio28", VIO28, 2800000), + MT6357_REG_FIXED("ldo-vrf12", VRF12, 1200000), + MT6357_REG_FIXED("ldo-vrf18", VRF18, 1800000), +}; + +static int mt6357_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6357 = dev_get_drvdata(pdev->dev.parent); + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; + + pdev->dev.of_node = pdev->dev.parent->of_node; + + for (i = 0; i < MT6357_MAX_REGULATOR; i++) { + config.dev = &pdev->dev; + config.driver_data = &mt6357_regulators[i]; + config.regmap = mt6357->regmap; + + rdev = devm_regulator_register(&pdev->dev, + &mt6357_regulators[i].desc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6357_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct platform_device_id mt6357_platform_ids[] = { + { "mt6357-regulator" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6357_platform_ids); + +static struct platform_driver mt6357_regulator_driver = { + .driver = { + .name = "mt6357-regulator", + }, + .probe = mt6357_regulator_probe, + .id_table = mt6357_platform_ids, +}; + +module_platform_driver(mt6357_regulator_driver); + +MODULE_AUTHOR("Fabien Parent "); +MODULE_AUTHOR("Alexandre Mergnat "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6357 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6357-regulator.h b/include/linux/regulator/mt6357-regulator.h new file mode 100644 index 000000000000..238b1ee77ea6 --- /dev/null +++ b/include/linux/regulator/mt6357-regulator.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __LINUX_REGULATOR_MT6357_H +#define __LINUX_REGULATOR_MT6357_H + +enum { + /* Bucks */ + MT6357_ID_VCORE, + MT6357_ID_VMODEM, + MT6357_ID_VPA, + MT6357_ID_VPROC, + MT6357_ID_VS1, + + /* LDOs */ + MT6357_ID_VAUX18, + MT6357_ID_VAUD28, + MT6357_ID_VCAMA, + MT6357_ID_VCAMD, + MT6357_ID_VCAMIO, + MT6357_ID_VCN18, + MT6357_ID_VCN28, + MT6357_ID_VCN33_BT, + MT6357_ID_VCN33_WIFI, + MT6357_ID_VDRAM, + MT6357_ID_VEFUSE, + MT6357_ID_VEMC, + MT6357_ID_VFE28, + MT6357_ID_VIBR, + MT6357_ID_VIO18, + MT6357_ID_VIO28, + MT6357_ID_VLDO28, + MT6357_ID_VMC, + MT6357_ID_VMCH, + MT6357_ID_VRF12, + MT6357_ID_VRF18, + MT6357_ID_VSIM1, + MT6357_ID_VSIM2, + MT6357_ID_VSRAM_OTHERS, + MT6357_ID_VSRAM_PROC, + MT6357_ID_VUSB33, + MT6357_ID_VXO22, + + MT6357_ID_RG_MAX, +}; + +#define MT6357_MAX_REGULATOR MT6357_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6357_H */ From patchwork Tue Nov 8 18:43:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 622796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24164C4167D for ; Tue, 8 Nov 2022 18:45:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234350AbiKHSpD (ORCPT ); Tue, 8 Nov 2022 13:45:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232866AbiKHSou (ORCPT ); Tue, 8 Nov 2022 13:44:50 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E39858010 for ; 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id m6-20020a05600c3b0600b003cf6c2f9513sm13564009wms.2.2022.11.08.10.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 10:44:21 -0800 (PST) From: Alexandre Mergnat Date: Tue, 08 Nov 2022 19:43:44 +0100 Subject: [PATCH v4 9/9] Input: mtk-pmic-keys: add MT6357 support MIME-Version: 1.0 Message-Id: <20221005-mt6357-support-v4-9-5d2bb58e6087@baylibre.com> References: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> In-Reply-To: <20221005-mt6357-support-v4-0-5d2bb58e6087@baylibre.com> To: Fabien Parent , Alexandre Belloni , Krzysztof Kozlowski , Sean Wang , Mark Brown , Matthias Brugger , Lee Jones , Chen Zhong , Alessandro Zummo , Pavel Machek , Rob Herring , Liam Girdwood , Dmitry Torokhov Cc: linux-leds@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org, AngeloGioacchino Del Regno , Fabien Parent , linux-rtc@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Mattijs Korpershoek X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2028; i=amergnat@baylibre.com; h=from:subject:message-id; bh=K2/LktiwnSqpYUY/NYDB7cyyBwW4Kzl5Gx1VcVhpHIg=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjaqN7eeGCzCyUi5InMw3eWnWYtPkXU1MgBrUAnShd 78BDjCeJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY2qjewAKCRArRkmdfjHURaYKEA Cr96MTTnXWtAIdf1TCkrHAL1LG6agzmHMlIDSss+hvEZXVgjdLetUSRXM2rPKGZajgqVMORqAqsKnF 1zKMvuG+4pSsS7v444elbnii1vzA51182pjRD2F0jkV4J92rP8zXvNi0RXD2Ml+LNGbkPz2ABTuJ+u MxxQ90HxFlzuMLoKZEbGOs7cPyOWbCXbPy5Gsf7McL+XUqAI7S79qvwts1qJCFM5gWrFLJZYYVpFVZ e0SBFefj/9iJTSUSh5VcLbY3W6k/Sp2EhShMB53fpmDn83gnHGr7dsJdOUHP+wChZxGyK2BllJ++vo U++aDKvTaRKpeBLgeJPEOF86OY3cTPjgqbJ4nGX7WFSvXfp/PecG6gNkIO6WUbBkLrUQpejlPyWaUe tZi3mXPjgOVm6I0U7VgK4TIjdUr/a+Apq+KpiGRERxsNkgue6sUTTqM/lgJ1az2r4EwXYnnm6paGvm xTV0HB/MOV88WbwM5aULpl1BUJ/5gxVt+ffAOlUe0eif1zjQatHreV/mEUMAofklktPfLm8EtnEOKF 1XMKXrUOgE7n3sHs33yNiRQ6qBBM2gh1F2FxT2TGfJrqPbxlagIKSgKnxrlNMWRaStJBHGE6gnEp4o ypEnkkZnfXiVLKTqgLA5KkpBIY7Jiioh2ocdw+dYFHt3jewLHNsPMtIJf3Mw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org From: Fabien Parent Add PMIC Keys support on MT6357 SoC. Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Mattijs Korpershoek Acked-by: Dmitry Torokhov Signed-off-by: Alexandre Mergnat --- drivers/input/keyboard/mtk-pmic-keys.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboard/mtk-pmic-keys.c index 9b34da0ec260..2a63e0718eb6 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -90,6 +91,19 @@ static const struct mtk_pmic_regs mt6331_regs = { .rst_lprst_mask = MTK_PMIC_MT6331_RST_DU_MASK, }; +static const struct mtk_pmic_regs mt6357_regs = { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS, + 0x2, MT6357_PSC_TOP_INT_CON0, 0x5, + MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS, + 0x8, MT6357_PSC_TOP_INT_CON0, 0xa, + MTK_PMIC_HOMEKEY_INDEX), + .pmic_rst_reg = MT6357_TOP_RST_MISC, + .rst_lprst_mask = MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6358_regs = { .keys_regs[MTK_PMIC_PWRKEY_INDEX] = MTK_PMIC_KEYS_REGS(MT6358_TOPSTATUS, @@ -276,6 +290,9 @@ static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = { }, { .compatible = "mediatek,mt6331-keys", .data = &mt6331_regs, + }, { + .compatible = "mediatek,mt6357-keys", + .data = &mt6357_regs, }, { .compatible = "mediatek,mt6358-keys", .data = &mt6358_regs,