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Thu, 26 Jan 2017 12:38:05 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH v2 1/3] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks Date: Thu, 26 Jan 2017 13:37:52 +0100 Message-id: <1485434274-6579-2-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNIsWRmVeSWpSXmKPExsWy7djP87pr33ZGGExda2GxccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI7isklJzcksSy3St0vg ynj99jNrwVqBitMnLrI2ME7l62Lk5JAQMJF48P0gK4QtJnHh3nq2LkYuDiGBpYwSF0+/gHI+ M0rs+nyCHabj94nd7BCJZYwSE/YtZIVwGpgk5hyczgxSxSZgKNH1tosNxBYRUJX43LYArINZ 4CmjxL3FLUwgCWGBSInDb1+CLWcBKuo7/gasmVfAXeJX2yU2iHVyEiePTQar4RTwkFj36RLY TRIC99kkZj3+ytLFyAHkyEpsOsAMUe8isfvMcShbWOLV8S1QZ8tIdHYcZIKw+xklmlq1IewZ jBLn3vJC2NYSh49fBNvFLMAnMWkbyDMg43klOtqEIEo8JM5OXcsIYTtKPDkymRni+dmMEmuP H2WfwCizgJFhFaNIamlxbnpqsalecWJucWleul5yfu4mRmCUnv53/OsOxqXHrA4xCnAwKvHw HtjRESHEmlhWXJl7iFGCg1lJhHfhy84IId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rx7FlwJFxJI TyxJzU5NLUgtgskycXBKNTCGr9NnnHbeITK1cd2inAsFiQkdduElGQvb9gc9e8t+sPP8wUAG r7cpk6Yt+aw+s9Sj5apX4t7HCofOZt/K/9B5PY7pqkrep6un2aQOObGViL/n6Jn8Ju5GR/QV j1hRN3bzh/Os9yrsnD29eEd8YIDGpW1R03vOvP4ZIFHFfGnq83u8VU8kmdKVWIozEg21mIuK EwFjps2IzgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrFLMWRmVeSWpSXmKPExsVy+t/xa7pv33ZGGMxYKGexccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI5ys8lITUxJLVJIzUvO T8nMS7dVCg1x07VQUshLzE21VYrQ9Q0JUlIoS8wpBfKMDNCAg3OAe7CSvl2CW8brt59ZC9YK VJw+cZG1gXEqXxcjJ4eEgInE7xO72SFsMYkL99azdTFycQgJLGGUOLF7NzOE08QkcW37PkaQ KjYBQ4mut11sILaIgKrE57YF7CBFzALPGSXe7+5nAUkIC0RKHH77khXEZgEq6jv+hhnE5hVw l/jVdokNYp2cxMljk8FqOAU8JNZ9AolzAG1zl9ixln8CI+8CRoZVjCKppcW56bnFhnrFibnF pXnpesn5uZsYgeG67djPzTsYL20MPsQowMGoxMN7YEdHhBBrYllxZe4hRgkOZiUR3oUvOyOE eFMSK6tSi/Lji0pzUosPMZoC3TSRWUo0OR8YS3kl8YYmhuaWhkbGFhbmRkZK4rwlH66ECwmk J5akZqemFqQWwfQxcXBKNTDKnQ09NrFE+b7uySVPklff1Qoqy3f+G64XcVPR1VivknH1q19F 70uYdvq9KKm80+szeUNNWcmdzAkSrrK3rn3Xu7Rw1UcuP1l9iYPiO+pZk164TL61uf+RYNHl eMusm2e5DUUaVQUkrjP9rJZdv5g1KVroVfGLe5bL0mKrn7ovvCSc+2nXWV4lluKMREMt5qLi RABG5kT2bQIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170126123805eucas1p2fd873698f59addae8aab7ac3ad0f6de4 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170126123805eucas1p2fd873698f59addae8aab7ac3ad0f6de4 X-RootMTR: 20170126123805eucas1p2fd873698f59addae8aab7ac3ad0f6de4 References: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- include/dt-bindings/clock/exynos5433.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 8fd7f6e88e3c..6ee91ae875c3 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -2559,8 +2559,10 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np) FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), /* PHY clocks from MIPI_DPHY0 */ - FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), - FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", + NULL, 0, 188000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", + NULL, 0, 100000000), /* PHY clocks from HDMI_PHY */ FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", NULL, 0, 300000000), diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 4fa6bb2136e3..be39d23e6a32 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -771,7 +771,10 @@ #define CLK_PCLK_DECON 113 -#define DISP_NR_CLK 114 +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 + +#define DISP_NR_CLK 116 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 From patchwork Thu Jan 26 12:37:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 92508 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp162419qgi; Thu, 26 Jan 2017 04:38:15 -0800 (PST) X-Received: by 10.99.49.132 with SMTP id x126mr2849597pgx.92.1485434295374; Thu, 26 Jan 2017 04:38:15 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Thu, 26 Jan 2017 12:38:05 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH v2 2/3] clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates Date: Thu, 26 Jan 2017 13:37:53 +0100 Message-id: <1485434274-6579-3-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRmVeSWpSXmKPExsWy7djPc7rr3nZGGNxeJWixccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI7isklJzcksSy3St0vg yuha0MlesISjovHgbqYGxu9sXYycHBICJhLXHx5mh7DFJC7cWw8U5+IQEljKKDH/8g8o5zOj xPrj51lgOh4t3ccMkVjGKLH2zk8op4FJYs7B6cwgVWwChhJdb7vAdogIqEp8blvADlLELPCU UeLe4hYmkISwQIzE2v4GRhCbBajo7IzTYHFeAXeJ2asfMUGsk5M4eWwyK4jNKeAhse7TJajD 77NJtH3n7mLkALJlJTYdYIYIu0js3HGaFcIWlnh1fAvUbzISnR0HoUb2M0o0tWpD2DMYJc69 5YWwrSUOH78I1ssswCcxaRvILyDjeSU62oQgSoAu2LiFEcJ2lFjSPxlsvJDAbEaJtjfmExhl FjAyrGIUSS0tzk1PLTbRK07MLS7NS9dLzs/dxAiM0NP/jn/Zwbj4mNUhRgEORiUe3gM7OiKE WBPLiitzDzFKcDArifAufNkZIcSbklhZlVqUH19UmpNafIhRmoNFSZx3z4Ir4UIC6Yklqdmp qQWpRTBZJg5OqQbGENGVcxPXq639u8ikvSnN2ui7yOf+X8JP/nrFsXGH28+cfWTxrE23Vt3N Pbwm0HM770mxl60tNdvk5UPTVvu8nd36cOJEZ5WDnoxiCvyLjF643LwWU7zjSGpF3GJDLc/r i9UrfbZ967kiI1loc63gq/F2Nr4Kn6AXXT9MLR4pWH0qPdO15YmfEktxRqKhFnNRcSIAJnS1 N8wCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrFLMWRmVeSWpSXmKPExsVy+t/xa7pv33ZGGFw9bWyxccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI5ys8lITUxJLVJIzUvO T8nMS7dVCg1x07VQUshLzE21VYrQ9Q0JUlIoS8wpBfKMDNCAg3OAe7CSvl2CW0bXgk72giUc FY0HdzM1MH5n62Lk5JAQMJF4tHQfM4QtJnHh3nqgOBeHkMASRonZ1y4yQzhNTBLXtu9jBKli EzCU6HrbBdYtIqAq8bltATtIEbPAc0aJ97v7WUASwgIxEmv7G8AaWICKzs44zQRi8wq4S8xe /YgJYp2cxMljk1lBbE4BD4l1ny4BDeUA2uYusWMt/wRG3gWMDKsYRVJLi3PTc4sN9YoTc4tL 89L1kvNzNzECw3XbsZ+bdzBe2hh8iFGAg1GJh/fAjo4IIdbEsuLK3EOMEhzMSiK8C192Rgjx piRWVqUW5ccXleakFh9iNAW6aSKzlGhyPjCW8kriDU0MzS0NjYwtLMyNjJTEeUs+XAkXEkhP LEnNTk0tSC2C6WPi4JRqYLTPe+YiWnlTqJLxWIofr0/MOufFm07xr9Csl47YMG9WwOSp6tKX X2r9/n9gZ5LSkZUnfR/v3mM04Quv23muFX/mRDmtsXpy9O5COUOX1XfPz3Y1qQ5sXRb101ll y6mq1sRfU6/nvLLSjZ2z7/7Be1O2X3+7vKMtdHHGEuVjs9v3Sb359jnOVV1PiaU4I9FQi7mo OBEAAJZxw20CAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc X-RootMTR: 20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc References: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clocks*' properties, parameters for those two additional rates are needed. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5433.c | 2 ++ 1 file changed, 2 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Chanwoo Choi diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 6ee91ae875c3..11343a597093 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -739,7 +739,9 @@ PLL_35XX_RATE(350000000U, 350, 6, 2), PLL_35XX_RATE(333000000U, 222, 4, 2), PLL_35XX_RATE(300000000U, 500, 5, 3), + PLL_35XX_RATE(278000000U, 556, 6, 3), PLL_35XX_RATE(266000000U, 532, 6, 3), + PLL_35XX_RATE(250000000U, 500, 6, 3), PLL_35XX_RATE(200000000U, 400, 6, 3), PLL_35XX_RATE(166000000U, 332, 6, 3), PLL_35XX_RATE(160000000U, 320, 6, 3), From patchwork Thu Jan 26 12:37:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 92511 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp162444qgi; Thu, 26 Jan 2017 04:38:19 -0800 (PST) X-Received: by 10.98.153.155 with SMTP id t27mr2911864pfk.48.1485434299865; Thu, 26 Jan 2017 04:38:19 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Thu, 26 Jan 2017 12:38:06 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e Date: Thu, 26 Jan 2017 13:37:54 +0100 Message-id: <1485434274-6579-4-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsWy7djP87ob33ZGGOzZqmGxccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI7isklJzcksSy3St0vg yji2R6vgu0bFz9P7GRsYbyp1MXJySAiYSMycdYwZwhaTuHBvPRuILSSwjFHizatwCPszo8T9 mxEw9S3r9zLC1ZzZnQphNzBJLDobAGKzCRhKdL3tApsjIqAq8bltAXsXIxcHs8BTRol7i1uY QBLCAikSZw63gi1mASp6+2kOO4jNK+Au8aPxMTvEMjmJk8cms4LYnAIeEus+XWIDGSQhcJ9N 4vzBd0BXcAA5shKbDkA94CLxYt9CNghbWOLV8S1Qc2QkLk/uZoGw+xklmlq1IewZjBLn3vJC 2NYSh49fBNvFLMAnMWnbdGaI8bwSHW1CECUeEouWvYEa4yix9sl5sHOEBGYzSjw53sM6gVFm ASPDKkaR1NLi3PTUYkO94sTc4tK8dL3k/NxNjMDYPP3v+PsdjE+bQw4xCnAwKvHwHtjRESHE mlhWXJl7iFGCg1lJhHfhy84IId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rx7F1wJFxJITyxJzU5N LUgtgskycXBKNTCGvY+71bVimZ+a1i7W3Rp2DlvtXpw52XiV/3ZQdRr3jSnZUuxb+w4uWZau Pfl9anT4WpcyvqcJy3weRKYdSzg414XdLoiZl33Nl5/LfSYKL+iffPtsaHtr9c4bnHGTDz47 EH3vXqzm5L7uBcxHXOU+qHQve7SEV2DqVg8uV3kl+bQb3gcT/2QqsRRnJBpqMRcVJwIAL4zQ A8kCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRmVeSWpSXmKPExsVy+t/xa7qr33ZGGHxo1rbYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEe52WSkJqakFimk5iXn p2TmpdsqhYa46VooKeQl5qbaKkXo+oYEKSmUJeaUAnlGBmjAwTnAPVhJ3y7BLePYHq2C7xoV P0/vZ2xgvKnUxcjJISFgItGyfi8jhC0mceHeerYuRi4OIYEljBILz6xkAkkICTQxSVxvMQGx 2QQMJbredrGB2CICqhKf2xawgzQwCzxnlHi/u58FJCEskCKx/t0rsCIWoKK3n+awg9i8Au4S Pxofs0Nsk5M4eWwyK4jNKeAhse7TJaB6DqBl7hI71vJPYORdwMiwilEktbQ4Nz232EivODG3 uDQvXS85P3cTIzBUtx37uWUHY9e74EOMAhyMSjy8Gds6IoRYE8uKK3MPMUpwMCuJ8C582Rkh xJuSWFmVWpQfX1Sak1p8iNEU6KaJzFKiyfnAOMoriTc0MTS3NDQytrAwNzJSEued+uFKuJBA emJJanZqakFqEUwfEwenVAPjPJsddldW7LQ/UDnrP6968tvFxbu38XduFT25ty6qe8n5f+K8 b5h8+L//Kr2TJyGjvmPeAuVq/3pDu+Q/Ff2WpjfPrPaObvhUdZalfSLrJ/k/SdMmPdJ6F9c4 ReB54cV9NTY+Mc/uu67h+Cx2j6FG7vyeU3PL288u2TjzxaGnfEkPbz18XGyjoMRSnJFoqMVc VJwIAJZshzhrAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb X-RootMTR: 20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb References: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add initial clock configuration for display subsystem for Exynos5433 based TM2/TM2e boards in device tree in order to avoid dependency on the configuration left by the bootloader. This initial configuration is also needed to ensure that display subsystem is operational if display power domain gets turned off before clock controller is probed and the inital clock configuration left by the bootloader saved. TM2 and TM2e uses different rate for DISP PLL clock, but for better maintainability all 'assigned-clocks-*' properties for DISP CMU are defines in each board dts instead of redefining the rates property. Signed-off-by: Marek Szyprowski --- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++ 3 files changed, 58 insertions(+), 12 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 5c207575ed0a..1c1c03142e6d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -217,18 +217,6 @@ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; }; -&cmu_disp { - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <0>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; - assigned-clock-rates = <0>, <400000000>; -}; - &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>, diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index ddba2f889326..b8bb053495af 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -18,6 +18,35 @@ compatible = "samsung,tm2", "samsung,exynos5433"; }; +&cmu_disp { + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <250000000>, <400000000>; +}; + &hsi2c_9 { status = "okay"; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts index d8bca75a1afe..c27500b7d8b5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts @@ -18,6 +18,35 @@ compatible = "samsung,tm2e", "samsung,exynos5433"; }; +&cmu_disp { + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <278000000>, <400000000>; +}; + &ldo31_reg { regulator-name = "TSP_VDD_1.8V_AP"; regulator-min-microvolt = <1800000>;