From patchwork Wed Nov 16 12:36:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 828E6C4332F for ; Wed, 16 Nov 2022 12:37:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233530AbiKPMhN (ORCPT ); Wed, 16 Nov 2022 07:37:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239082AbiKPMg5 (ORCPT ); Wed, 16 Nov 2022 07:36:57 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06842A183 for ; Wed, 16 Nov 2022 04:36:23 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id gv23so11002766ejb.3 for ; Wed, 16 Nov 2022 04:36:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=KZBT8P6Dv4DO8+VutzfmTjw2eFqXhFXatHTYor7MjsU=; b=hlQNk0rVp3sE85UQqVnwNbaSG3QuiVGpipf/JeuKhOANQCdtms+INmd4MyRonzImhL NUi2yie/KzREDVos/KrGeq2GPvdmgJgC9a8ZfgkMRp+sv1rBnlbOA9KM6d8L6j5xdhSZ Zoiy+q0RgUIABxqUTWbIwQWYMpLdjX1ovBvNpOU16Qlp7E3Fgr53z3/dKeZV+1dl8OUV qkyIq8K8QgVkJio3qrqhpamZpHL5EtnUrBDGplun79N2WJfkV/aFnzq2ZOoED1kDqqJE rUZZrWkwDp49YaVbf/sriTK4UqZackZ+IqOqi/MdbOz2vfEC4KD/GtiVt/beTThn4A5m PxKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=KZBT8P6Dv4DO8+VutzfmTjw2eFqXhFXatHTYor7MjsU=; b=7fkGaT9QxBdHIMPDShKckitp9snZz68Cc80Yr28r3VRu57cS7L2iJGw2Xi64KtN0NJ xDdro6y2Q03FjukQ6HsU5B4MeIkNoJKrhMZpaVgjGzLz2mtzRniVwSS1ANOgwTr6FLrK v6TAE1tXBi6We1ZOlCq7sStbtVDQG90c48cXhyIS0nYOasaQ+adNuOly64p1AWZyDa6r l4+1qEHDoTeFRFV4cclBtspB2rjpIogK8TueuSWCTiIBRpMoOiCjUyeX3n8YQiCMnQDq jeabaft8exjOwKo7G4yoIZSXQSI+1BxIAaEkaDElfFSY1PjrNpc0q+WEctJeY93W9iSe IVaA== X-Gm-Message-State: ANoB5plo4Eji0VTucrgDsgy2YMcmiuU4kkJqTf2SK8XkQDCDEXetRDJ+ ame3Yh6sK02lF8YA/qxsYHdS32NpBRt0csQ3 X-Google-Smtp-Source: AA0mqf4I/YjZAzS1pjS8ZmT2wdWov+a4rkd9ETVSHA0x7+nwD2F7Hmk5eG3SVjUQrmdM4onxSJs0/Q== X-Received: by 2002:a17:906:5f88:b0:7ad:92fa:589e with SMTP id a8-20020a1709065f8800b007ad92fa589emr16970948eju.668.1668602181186; Wed, 16 Nov 2022 04:36:21 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id cb13-20020a170906a44d00b007abafe43c3bsm6773346ejb.86.2022.11.16.04.36.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 16 Nov 2022 04:36:20 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: mmc: sdhci-msm: Document SM8350 SDHCI Date: Wed, 16 Nov 2022 13:36:09 +0100 Message-Id: <20221116123612.34302-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the SDHCI on SM8350. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Changes in v2: - pick up a-b Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 12def0f57e3e..31dfaff0048d 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -49,6 +49,7 @@ properties: - qcom,sm6375-sdhci - qcom,sm8150-sdhci - qcom,sm8250-sdhci + - qcom,sm8350-sdhci - qcom,sm8450-sdhci - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 From patchwork Wed Nov 16 12:36:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8352C433FE for ; Wed, 16 Nov 2022 12:37:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232099AbiKPMhP (ORCPT ); Wed, 16 Nov 2022 07:37:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239091AbiKPMg6 (ORCPT ); Wed, 16 Nov 2022 07:36:58 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B72591CFC9 for ; Wed, 16 Nov 2022 04:36:24 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id bj12so43649940ejb.13 for ; Wed, 16 Nov 2022 04:36:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wJ4LXLUuVrv6zFSflxxTlPtNIH6eGmu9CDdhaBfrfx0=; b=A7n6QEdSnW3L7+Ik5Q4uPU1+XXtD8goFQDsGeVGFQyK9sBClQKDr1r8+ceINCFzxq4 ZPdjxR86y7o6PECHIeKjo5SaRMfDmS2NQwIttaICi53RxavpcMhsaQxZgs9bOj/U5IIf EVq+j1QgCQhfLbJ2vJSOmlV66e22dPb9nt5fvdvZyd7qTDPlQOH9TbVIHdUaqI7V/Gsn fEwsj1sdujNCVEpQS8Q3trQxvolqWrad3Wn/8S3lii65hMjLmWije09J3QFhUtJI8LCq MDm8kPtT3x7nEA+E6SO8ci9yo38JtuRWiLKxhuQOM+Ai+D/8eNTsFlvZ/lKBCfop/s73 /HrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wJ4LXLUuVrv6zFSflxxTlPtNIH6eGmu9CDdhaBfrfx0=; b=4trL3ERgqjRAmIK0gSfU8MwEUMGKEJisb04ynAIOJUNPT/cEXOLhrV8Wa5EiBf2jte hrc/BvfK40UvN1gU47qtIgxgtbZUbqCTXmQe2HIbMnBWKxjBy/PpIKSCaqhwzT/FytAa cy5Xecb1+ph5muoRo8xRU89SQH5bH8JKTn144bwZDjqQ/OwMlhpd2+fL3Y4r/PfqatGv LRcRcoCs83iCrI5Tf8fFw9HRj6FrrboaiLyXrN5Id+rgf6M+l2JPH9bwav7cieqe6hUx GvaTQH618zGqKnP3yzcBeYT/3fKF1gu7apBPOVhVY/pcyht8zCoay8C/DVjZHC+/Jruf yA9w== X-Gm-Message-State: ANoB5pk4NsSiwaPhxE/0+rNPSkbkHAH1V8otazD6p80YzWaffDmSiGcS r/2sE5tcC+z9TcIEcVY51/wvfUQSUpHmUAxe X-Google-Smtp-Source: AA0mqf69fFJxYsqpCdCIH07Vnmsmmae/PINzR1v/fHy04rT9WpQycvoBe3mQcAgvzcFC8yDJB+tOsA== X-Received: by 2002:a17:907:76ec:b0:78d:5966:b093 with SMTP id kg12-20020a17090776ec00b0078d5966b093mr18665190ejc.343.1668602183064; Wed, 16 Nov 2022 04:36:23 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id cb13-20020a170906a44d00b007abafe43c3bsm6773346ejb.86.2022.11.16.04.36.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 16 Nov 2022 04:36:22 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH v2 2/4] arm64: dts: qcom: sm8350: Add SDHCI2 Date: Wed, 16 Nov 2022 13:36:10 +0100 Message-Id: <20221116123612.34302-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221116123612.34302-1-konrad.dybcio@linaro.org> References: <20221116123612.34302-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add and configure the SDHCI host responsible for (mostly) SD Card and its corresponding pins' sleep states. The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be broken). Signed-off-by: Konrad Dybcio --- No changes in v2. arch/arm64/boot/dts/qcom/sm8350.dtsi | 79 ++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 552c0da3c479..9a118112facb 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1761,6 +1761,46 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 204>; wakeup-parent = <&pdc>; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_uart3_default_state: qup-uart3-default-state { rx-pins { pins = "gpio18"; @@ -2329,6 +2369,45 @@ compute-cb@8 { }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4a0 0x0>; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8350-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; From patchwork Wed Nov 16 12:36:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88743C4321E for ; Wed, 16 Nov 2022 12:37:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229716AbiKPMhP (ORCPT ); Wed, 16 Nov 2022 07:37:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239093AbiKPMg6 (ORCPT ); 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Wed, 16 Nov 2022 04:36:24 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH v2 3/4] arm64: dts: qcom: sm8350-sagami: Add GPIO line names for TLMM Date: Wed, 16 Nov 2022 13:36:11 +0100 Message-Id: <20221116123612.34302-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221116123612.34302-1-konrad.dybcio@linaro.org> References: <20221116123612.34302-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Sagami-common / PDX215 DTSIs to better document the hardware. Diff between 215 and common: < "NC", < "NC", > "WLC_I2C_SDA", > "WLC_I2C_SCL", < "NC", > "WLC_INT_N", > "CAM_MCLK4", < "NC", < "NC", > "TOF_RST_N", < "NC", < "NC", < "NC", > "QLINK1_REQ", > "QLINK1_EN", > "QLINK1_WMSS_RESET_N", It's pretty logical as 1 III has WLC (WireLess Charging), and an additional 3D iToF sensor. As for QLINK, no idea. Signed-off-by: Konrad Dybcio --- No changes in v2. .../qcom/sm8350-sony-xperia-sagami-pdx215.dts | 206 ++++++++++++++++++ .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 203 +++++++++++++++++ 2 files changed, 409 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts index d21bbeb603a6..c74c973a69d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -11,3 +11,209 @@ / { model = "Sony Xperia 1 III"; compatible = "sony,pdx215-generic", "qcom,sm8350"; }; + +&tlmm { + gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */ + "APPS_I2C_0_SCL", + "UWIDEC_PWR_EN", + "HAP_RST_N", + "WLC_I2C_SDA", + "WLC_I2C_SCL", + "PM8008_1_RESET_N", + "WLC_INT_N", + "OIS_TELE_I2C_SDA", + "OIS_TELE_I2C_SCL", + "PM8350_OPTION", /* GPIO_10 */ + "NC", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "NC", + "CAM1_RESET_N", + "LEO_CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP_RESET_N", + "SW_SERVICE", + "DISP_ERR_FG", + "TX_GTR_THRES_IN", + "NC", + "NC", + "NC", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "SPK_AMP_INT_N", + "SPK_AMP_RESET_N", + "FP_INT_N", + "FP_RESET_N", + "NC", /* GPIO_40 */ + "NC", + "DEBUG_GPIO0", + "FORCE_USB_BOOT", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", /* GPIO_50 */ + "HAP_INT_N", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "SBU_SW_OE", + "SBU_SW_SEL", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HW_ID_0", + "HW_ID_1", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "HAP_I2C_SDA", + "HAP_I2C_SCL", + "RF_LCD_ID_EN", + "RF_ID_EXTENSION", + "NC", + "NC", + "NC", + "NC", + "HALL_INT_N", /* GPIO_80 */ + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_SOF_TELE", + "NFC_DWL_REQ", + "NFC_IRQ", + "WCD_RST_N", + "ALS_PROX_INT_N", + "NC", /* GPIO_90 */ + "NC", + "TRAY_DET", + "UDON_SWITCH_SEL", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "CAM_SOF", + "RF_ID_EXTENSION_2", + "RGBC_IR_INT", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CAM_MCLK4", + "NC", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "NC", + "PM8008_1_IRQ", + "CAM3_RESET_N", + "IMU1_INT", + "EXT_VD0_XVS", + "NC", /* GPIO_120 */ + "NC", + "NC", + "NC", + "NC", + "HAP_I2S_CLK", + "HAP_I2S_DOUT", + "HAP_TRG1", + "HAP_I2S_SYNC", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "NC", + "UIM2_DETECT_EN", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "TRAY_DET", /* GPIO_140 */ + "SM_RFFE0_CLK", + "SM_RFFE0_DATA", + "SM_RFFE1_CLK", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DISP_VDDR_EN", + "NC", + "NC", + "PA_INDICATOR_OR", + "TOF_RST_N", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "QLINK1_REQ", + "QLINK1_EN", + "QLINK1_WMSS_RESET_N", + "PM8008_2_IRQ", + "TELEC_PWR_EN", + "PM8008_2_RESET_N", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "SM_DMIC1_CLK", + "SM_DMIC1_DATA", + "SM_DMIC2_CLK", + "SM_DMIC2_DATA", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */ + "SPK_AMP_I2S_ASP_DOUT", + "WCD_SWR_TX_DATA2", + "NC", + "NC", + "NC", + "NC", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index dab5145358e7..a428ce31ab4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -571,6 +571,209 @@ &spi14 { &tlmm { gpio-reserved-ranges = <44 4>; + gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */ + "APPS_I2C_0_SCL", + "UWIDEC_PWR_EN", + "HAP_RST_N", + "NC", + "NC", + "PM8008_1_RESET_N", + "NC", + "OIS_TELE_I2C_SDA", + "OIS_TELE_I2C_SCL", + "PM8350_OPTION", /* GPIO_10 */ + "NC", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "NC", + "CAM1_RESET_N", + "LEO_CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP_RESET_N", + "SW_SERVICE", + "DISP_ERR_FG", + "TX_GTR_THRES_IN", + "NC", + "NC", + "NC", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "SPK_AMP_INT_N", + "SPK_AMP_RESET_N", + "FP_INT_N", + "FP_RESET_N", + "NC", /* GPIO_40 */ + "NC", + "DEBUG_GPIO0", + "FORCE_USB_BOOT", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", /* GPIO_50 */ + "HAP_INT_N", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "SBU_SW_OE", + "SBU_SW_SEL", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HW_ID_0", + "HW_ID_1", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "HAP_I2C_SDA", + "HAP_I2C_SCL", + "RF_LCD_ID_EN", + "RF_ID_EXTENSION", + "NC", + "NC", + "NC", + "NC", + "HALL_INT_N", /* GPIO_80 */ + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_SOF_TELE", + "NFC_DWL_REQ", + "NFC_IRQ", + "WCD_RST_N", + "ALS_PROX_INT_N", + "NC", /* GPIO_90 */ + "NC", + "TRAY_DET", + "UDON_SWITCH_SEL", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "CAM_SOF", + "RF_ID_EXTENSION_2", + "RGBC_IR_INT", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "NC", + "NC", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "NC", + "PM8008_1_IRQ", + "CAM3_RESET_N", + "IMU1_INT", + "EXT_VD0_XVS", + "NC", /* GPIO_120 */ + "NC", + "NC", + "NC", + "NC", + "HAP_I2S_CLK", + "HAP_I2S_DOUT", + "HAP_TRG1", + "HAP_I2S_SYNC", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "NC", + "UIM2_DETECT_EN", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "TRAY_DET", /* GPIO_140 */ + "SM_RFFE0_CLK", + "SM_RFFE0_DATA", + "SM_RFFE1_CLK", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DISP_VDDR_EN", + "NC", + "NC", + "PA_INDICATOR_OR", + "NC", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "PM8008_2_IRQ", + "TELEC_PWR_EN", + "PM8008_2_RESET_N", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "SM_DMIC1_CLK", + "SM_DMIC1_DATA", + "SM_DMIC2_CLK", + "SM_DMIC2_DATA", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */ + "SPK_AMP_I2S_ASP_DOUT", + "WCD_SWR_TX_DATA2", + "NC", + "NC", + "NC", + "NC", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; 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Wed, 16 Nov 2022 04:36:26 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH v2 4/4] arm64: dts: qcom: sm8350-sagami: Wire up SDHCI2 Date: Wed, 16 Nov 2022 13:36:12 +0100 Message-Id: <20221116123612.34302-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221116123612.34302-1-konrad.dybcio@linaro.org> References: <20221116123612.34302-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adjust regulators, add required pin setup and finally enable SDHCI2 to get the SD Card slot going on Sagami Xperias. Signed-off-by: Konrad Dybcio --- Changes in v2: - drop stray newline .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index a428ce31ab4e..6ae700e72d1e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -312,7 +312,8 @@ pm8350c_l8: ldo8 { pm8350c_l9: ldo9 { regulator-name = "pm8350c_l9"; regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <3008000>; + /* Originally max = 3008000 but SDHCI expects 2960000 */ + regulator-max-microvolt = <2960000>; regulator-initial-mode = ; }; @@ -558,6 +559,18 @@ &qupv3_id_2 { status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_active>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_sleep>; + vmmc-supply = <&pm8350c_l9>; + vqmmc-supply = <&pm8350c_l6>; + no-sdio; + no-mmc; + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/Sony/sagami/slpi.mbn"; @@ -782,6 +795,20 @@ ts_int_default: ts-int-default-state { bias-disable; input-enable; }; + + sdc2_card_det_active: sd-card-det-active-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_card_det_sleep: sd-card-det-sleep-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; /* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */