From patchwork Fri Dec 2 03:13:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB55CC3A5A7 for ; Fri, 2 Dec 2022 03:13:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231382AbiLBDNy (ORCPT ); Thu, 1 Dec 2022 22:13:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231281AbiLBDNy (ORCPT ); Thu, 1 Dec 2022 22:13:54 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA3F9A1C30 for ; Thu, 1 Dec 2022 19:13:52 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id r18so3314305pgr.12 for ; Thu, 01 Dec 2022 19:13:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tv1e03FO2qF987UL3rYSZkGVDWpL3dr4bIgnamkaz8k=; b=JV2o44TcICEeavKcKwTz5icwfqQZhgGRMR59dYqZw6edW2hmyWYnto69rzN58YgSCl YZ62t32NCd8NWbOCcRo+JJ1OVyWgaYyR7dUcc2X2d9aud1Z3KdnfVY5jdO6Hh1jgavP3 gQmn1d5BFULs30vR6Eo1cCyDnWFnV+bBJSDdw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tv1e03FO2qF987UL3rYSZkGVDWpL3dr4bIgnamkaz8k=; b=FfGPboHDd96rmPhEW+fWTzAStU5bOT3isHqCzegdFXmYwC4Z7XMA+ZNjQz57TNPG18 ODTN/RImaiAiXJmoKl2R0tFZSFjeit+wB7w1b96/elh0qFBydii64j3HY6sOLfs1TtOb FeY9cHnIwoW6QmLehwYM8ZMIl1oJlMp+io/GDfKxQCeVsUbpkJEW2R78FL/OMEBiDE2c qDnsZWWFtR39Phye+3C6TwGcRSmHQWTSRfX7ykNYOr+dqcWuWjoAUrvxkuWGiMGB2Pb3 aJtRTOF11Lvq3O0SyCVdp5oP1bDHW5Xef7kpYshm0jTPjDXhn74rFKRdhGlKtBxiT7jq fy0g== X-Gm-Message-State: ANoB5pm9YwUgmyC1lkUZIZwrwfBBf0v3oZzxtX8IDWwKgEa0vIG8bv/X qRBJmrS8S/sdulA+mDQNP4Yuig== X-Google-Smtp-Source: AA0mqf42Fi4K0GcfUowvvBL6IInOEw16/UgSJiR9E4D+8vzj/BiS6MQ9Yoo27zFnj4kwNRAn2Bq8DQ== X-Received: by 2002:a63:4f48:0:b0:477:4451:cf5 with SMTP id p8-20020a634f48000000b0047744510cf5mr43112803pgl.391.1669950832251; Thu, 01 Dec 2022 19:13:52 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:13:51 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 1/8] mmc: sdhci-pxav2: add initial support for PXA168 V1 controller Date: Thu, 1 Dec 2022 19:13:23 -0800 Message-Id: <20221202031330.94130-2-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a new compatible string for the version 1 controller used in the PXA168, along with necessary quirks. Use a separate ops struct in preparation for a silicon bug workaround only necessary on V1. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index f18906b5575f..2f9fa0ecbddd 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -101,6 +101,14 @@ static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); } +static const struct sdhci_ops pxav1_sdhci_ops = { + .set_clock = sdhci_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .set_bus_width = pxav2_mmc_set_bus_width, + .reset = pxav2_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + static const struct sdhci_ops pxav2_sdhci_ops = { .set_clock = sdhci_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, @@ -114,6 +122,9 @@ static const struct of_device_id sdhci_pxav2_of_match[] = { { .compatible = "mrvl,pxav2-mmc", }, + { + .compatible = "mrvl,pxav1-mmc", + }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); @@ -208,7 +219,12 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) host->mmc->pm_caps |= pdata->pm_caps; } - host->ops = &pxav2_sdhci_ops; + if (match && of_device_is_compatible(dev->of_node, "mrvl,pxav1-mmc")) { + host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE; + host->ops = &pxav1_sdhci_ops; + } else { + host->ops = &pxav2_sdhci_ops; + } ret = sdhci_add_host(host); if (ret) From patchwork Fri Dec 2 03:13:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72EB8C4332F for ; Fri, 2 Dec 2022 03:13:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231386AbiLBDN4 (ORCPT ); Thu, 1 Dec 2022 22:13:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231281AbiLBDNz (ORCPT ); Thu, 1 Dec 2022 22:13:55 -0500 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 042CBBDCD4 for ; Thu, 1 Dec 2022 19:13:55 -0800 (PST) Received: by mail-pf1-x434.google.com with SMTP id x66so3733865pfx.3 for ; Thu, 01 Dec 2022 19:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=10C9l5cM9Gx+6A1r6iqoMzAy/dFS6z3guP1T2Uf7DqQ=; b=GzFWbtk3S9t+0VjSG76aShbOV7wvNmi2SYZMEKPNNrTRGTuFIXP51tcs/kbn4fdkjo DanB1GiufsQDarHpUm64Ztphf9zHHPICk6zwyn9tU4Op3V9WYXHiHzP7lR6/I3IWBh/0 NttKDv9CXewheMn05Z/aFsl24LonisuV/Asto= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=10C9l5cM9Gx+6A1r6iqoMzAy/dFS6z3guP1T2Uf7DqQ=; b=ajRiOyzGDeu85BcAUu2dCXNDGe2gf9eooqbWhbhif1LzbTai6JOjz7fiKy8e7WY50+ v0vIM/mgfFFDMGOy+ls4ZyNNyyyHnutm3vqCrf8D3AFcAVFtfTinY+6CS0zZ3TjskTHK +3KAZk75xN0ozOXK2M3xE+I/D/dNk0hCtsZfzjhERBoXaLxcmitxCG+FWfVX2F4JSXLf soFqC1tCLrlRhsINOtTagRcUX9wwCw4Z9A66JbtHlmvXK6OLPtd7lkazgddyDyMaKaox oyyGLBkQONImKKNvZEweuwd7mDWPQAQfppNkLh9acxamVio9lXDq9wyYM9L6FNIIcaML PMAw== X-Gm-Message-State: ANoB5plWNA5hBQgjeDQzkrMP4zet1oBzVNkx3vYzqkJM8CrpPAhDVsX4 yix8jzMmA/IDra8v3vLXLtWNHw== X-Google-Smtp-Source: AA0mqf4o793oxYNk0FFPeFBWUTicJJXqgOj7ZiMm623X3fFZKUdWvG/U0vCNIQRUALcpLh8gH54DJw== X-Received: by 2002:a63:4d61:0:b0:477:b1a8:531e with SMTP id n33-20020a634d61000000b00477b1a8531emr41918713pgl.158.1669950834441; Thu, 01 Dec 2022 19:13:54 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:13:53 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 2/8] mmc: sdhci-pxav2: enable CONFIG_MMC_SDHCI_IO_ACCESSORS Date: Thu, 1 Dec 2022 19:13:24 -0800 Message-Id: <20221202031330.94130-3-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable CONFIG_MMC_SDHCI_IO_ACCESSORS for the pxav2 driver. The read_w callback is needed for a silicon bug workaround in the PXA168. Signed-off-by: Doug Brown --- drivers/mmc/host/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5e19a961c34d..b9e9185c86a6 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -360,6 +360,7 @@ config MMC_SDHCI_PXAV2 depends on MMC_SDHCI_PLTFM depends on ARCH_MMP || COMPILE_TEST default CPU_PXA910 + select MMC_SDHCI_IO_ACCESSORS help This selects the Marvell(R) PXAV2 SD Host Controller. If you have a PXA9XX platform with SD Host Controller From patchwork Fri Dec 2 03:13:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AA6FC3A5A7 for ; Fri, 2 Dec 2022 03:14:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231387AbiLBDOA (ORCPT ); Thu, 1 Dec 2022 22:14:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231299AbiLBDN6 (ORCPT ); Thu, 1 Dec 2022 22:13:58 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7266CA9CCE for ; Thu, 1 Dec 2022 19:13:57 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id o12so3693637pjo.4 for ; Thu, 01 Dec 2022 19:13:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ym9YTdhefXOHHkd3Jf4XxEyW1/V8EXozYna2j5niSpo=; b=PDjsxCWo+qZ79bbBq4qHpmcDxR9sR3rSO23hLyzgQHSTrzDIOvnMZBnQcYP00pnFuz 6Q0tJqxg+6Rd9XG3zv3fOj8ww1c99qYnNB3mGBO9T8IRGx4ZryIK9m3atpCrJxfBP99t w7M4y0AQzJTZF3yKEy7YbCubW3Td4Pv85SuxY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ym9YTdhefXOHHkd3Jf4XxEyW1/V8EXozYna2j5niSpo=; b=PDW5xmNStLSuEcDWJ4VDAQ9vNRvrcpg7iQol6LtlS1+79e6wx8u85lKAWez/3Hs7iw xU+daCItYuvTNDX0aYN1utAvSzLpKJy6SvQfGo0h5+t7L53Hw5a9/+YS+wq90amVqzUb 1BPS3If0ioJ2wcKbzUe7XpEfgoLYlIQZWCXZcxOzc0d3+QjpjmUp7k1UOa2cAyvIIxnT QLrQf3lijdeRvSHMN4hvCOTJp8MQx9LNZqNjQ6As/LmNdmo/lNB+GTugW7YXMEEBQ1wJ f5Reo8VbVW3wUfY9KXD5KnlAkVdAbtd1qxnZee5N/arhnQrRv5u1GduIEFzPRLpxIQD+ bqmA== X-Gm-Message-State: ANoB5pnRsT6uWitAeOTSFl26jEc0DbfEY0PTtfNw3gpva2kvEaRq54ZE rTD7JKBxQMrpEqfsDgazsC0HmQ== X-Google-Smtp-Source: AA0mqf5ZYpxHSgY7GvM3UxFAtjuVFa98HNtyC+pVpnUKJeJ++FHDcyWIP/eOqg/y+5EE3Fc0EqnAow== X-Received: by 2002:a17:902:dacd:b0:189:6889:c30a with SMTP id q13-20020a170902dacd00b001896889c30amr34384066plx.6.1669950836835; Thu, 01 Dec 2022 19:13:56 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:13:56 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 3/8] mmc: sdhci-pxav2: add register workaround for PXA168 silicon bug Date: Thu, 1 Dec 2022 19:13:25 -0800 Message-Id: <20221202031330.94130-4-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PXA168 has a documented silicon bug that results in a data abort exception when accessing the SDHCI_HOST_VERSION register on SDH2 and SDH4 through a 16-bit read. Implement the workaround described in the errata, which performs a 32-bit read from a lower address instead. This is safe to use on all four SDH peripherals. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 2f9fa0ecbddd..0a16098b963f 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -80,6 +80,15 @@ static void pxav2_reset(struct sdhci_host *host, u8 mask) } } +static u16 pxav1_readw(struct sdhci_host *host, int reg) +{ + /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */ + if (reg == SDHCI_HOST_VERSION) + return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16; + + return readw(host->ioaddr + reg); +} + static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) { u8 ctrl; @@ -102,6 +111,7 @@ static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) } static const struct sdhci_ops pxav1_sdhci_ops = { + .read_w = pxav1_readw, .set_clock = sdhci_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = pxav2_mmc_set_bus_width, From patchwork Fri Dec 2 03:13:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 357FCC4321E for ; Fri, 2 Dec 2022 03:14:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231281AbiLBDOC (ORCPT ); Thu, 1 Dec 2022 22:14:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231493AbiLBDOA (ORCPT ); Thu, 1 Dec 2022 22:14:00 -0500 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A03E8D49D2 for ; Thu, 1 Dec 2022 19:13:59 -0800 (PST) Received: by mail-pg1-x52c.google.com with SMTP id 62so3311736pgb.13 for ; Thu, 01 Dec 2022 19:13:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=agIvM+RESqFOi6zq2PfLhwbAmjFDfRo+ieTUEwufHOc=; b=eaVziJwbJ8GXqtHJD7dVAD9LkmXFaz+/poyw0LaBJDLiFpSyHR+1VRLe/nqkKbrDki zMFNro3K5/jF+5N2wM8g6zjqN/SUzk6j48iJrdU4dmje0CkvEX0Y8vgtCS8Zo2ChzbG1 5K1y6rNSZDThLxCrWlpCeWeEk3ZfnErSv3xZs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=agIvM+RESqFOi6zq2PfLhwbAmjFDfRo+ieTUEwufHOc=; b=KWcooYFuLgiLuBsPwIrGMsYNnnz7yYASSMQmDk090QgTuZhjLH6caliqVEduLvFQ+T xWOLpxDTmVElvj+zyf8j0jGl6ibPVHsg5/MOU6XODUNMLoya6OR7jiDeicSLl4PCny3O 86tZew5nC4atjuP7WLko2j2WXj95xvVSvgnthfMHAXXZ7MoGHtgwGydhVSVpwHAbm6qd WBjH4cCj7N0h3cjJrVjws5OEIeWtRtB+mWDJ+73qinGQN9kUdK4QvEgSCIQUUksEnh3t Ey5T/GzxWRnTpNkv2d/uNn9bfqUm4m53Vk5gtC3GFZECdC6JrpWfqnQb2HkOcCTV6tNt 9w/w== X-Gm-Message-State: ANoB5pkbj6nZDcd+xi+VYY72r0dasYiD4T3jBkXESHNGoqnKlVuX9rxE 01KSszSKvrRariHPs6s+VvXw9Q== X-Google-Smtp-Source: AA0mqf4K1NiC1zJPzjzp/rwODq9vS7RxKPAosQIViGm6J4QjknqA1LGCxbi/8+JFxVBqnV+XLQPZlA== X-Received: by 2002:a63:e510:0:b0:476:a862:53d2 with SMTP id r16-20020a63e510000000b00476a86253d2mr42354672pgh.163.1669950839021; Thu, 01 Dec 2022 19:13:59 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.13.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:13:58 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 4/8] mmc: sdhci-pxav2: change clock name to match DT bindings Date: Thu, 1 Dec 2022 19:13:26 -0800 Message-Id: <20221202031330.94130-5-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The devicetree bindings for this driver specify that the two allowed clock names are io and core. Change this driver to look for io, but allow any name if it fails for backwards compatibility. Follow the same pattern used in sdhci-pxav3. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 0a16098b963f..509ba5dd4a4a 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -189,7 +189,9 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); - clk = devm_clk_get(dev, "PXA-SDHCLK"); + clk = devm_clk_get(dev, "io"); + if (IS_ERR(clk)) + clk = devm_clk_get(dev, NULL); if (IS_ERR(clk)) { dev_err(dev, "failed to get io clock\n"); ret = PTR_ERR(clk); From patchwork Fri Dec 2 03:13:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F50CC4332F for ; Fri, 2 Dec 2022 03:14:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231583AbiLBDOG (ORCPT ); Thu, 1 Dec 2022 22:14:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231493AbiLBDOD (ORCPT ); Thu, 1 Dec 2022 22:14:03 -0500 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF1CBD49DF for ; Thu, 1 Dec 2022 19:14:01 -0800 (PST) Received: by mail-pf1-x430.google.com with SMTP id c7so339372pfc.12 for ; Thu, 01 Dec 2022 19:14:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y22VghNPhGNaubNRJ5w1ZU32tCEMhbhW0ElXOX2vO5Y=; b=YSOZoUj6dUY2q541u96Cd/bKtl0KdB811jY/M6Nd488IqnCelmEkJJTx9VKhUi6vw7 CVYM35cIqoOWwpQJq10e/CY27Bn0mk+0n6aPjv/LKi4jVUu0RkF750tm/Ofb5oEcGJin NKQLEzmePRJH5RZSQpPaIaszm3KY24aCCISnQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y22VghNPhGNaubNRJ5w1ZU32tCEMhbhW0ElXOX2vO5Y=; b=SHxji0MDw71ciOs57yPSYBtEiEXbSxyUu6GEC+tLBN8pxVv2aWuG+sPMG8mqweLRnk URtMSCVmB2+f8UOCldYBHfUx/VtpApuY4SKZ72izgpYE09joKdgXD2CJx3+rW1twexXo JIsoWH9UrJxiZFfPLxKbALQ0+ERIVDIxF2+c7BMA5OXKdRy/3NlreBu1syrQPR59JD0e jLOF0daJMBVVNKvTejb+Q9+UN84CqP8JJcupfTobbqVyiKW8wZ8C8VqWkcekE7BRZN/v qzvKm7KHXtDj6lZWrh24MqXiTPUqhoW8rCCaBeGO4hyQsXfmiXalOMVqPPwAKKQZEXLX EVkw== X-Gm-Message-State: ANoB5pmQhwTnK2t6jTGPw++bkwEa2bfk5yYwrYpB+4z/vDii29jgE1QR qyg54ZzOuXebgdrPa1B4FlqqzA== X-Google-Smtp-Source: AA0mqf50WxAzOBiAl90lZP0H57EBaa1OL/+5YTZY6Ox6TPRTIYzjNWEahEJlYdwknl4uBYMNHjpQ8g== X-Received: by 2002:a63:f201:0:b0:478:50c9:a6d with SMTP id v1-20020a63f201000000b0047850c90a6dmr12270928pgh.485.1669950841170; Thu, 01 Dec 2022 19:14:01 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.14.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:14:00 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 5/8] mmc: sdhci-pxav2: add optional core clock Date: Thu, 1 Dec 2022 19:13:27 -0800 Message-Id: <20221202031330.94130-6-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ability to have an optional core clock just like the pxav3 driver. The PXA168 needs this because its SDHC controllers have separate core and io clocks that both need to be enabled. This also correctly matches the documented devicetree bindings for this driver. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 40 ++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 509ba5dd4a4a..1f0c3028987a 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -41,6 +41,10 @@ #define MMC_CARD 0x1000 #define MMC_WIDTH 0x0100 +struct sdhci_pxav2_host { + struct clk *clk_core; +}; + static void pxav2_reset(struct sdhci_host *host, u8 mask) { struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); @@ -176,6 +180,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) { struct sdhci_pltfm_host *pltfm_host; struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; + struct sdhci_pxav2_host *pxav2_host; struct device *dev = &pdev->dev; struct sdhci_host *host = NULL; const struct of_device_id *match; @@ -183,11 +188,12 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) int ret; struct clk *clk; - host = sdhci_pltfm_init(pdev, NULL, 0); + host = sdhci_pltfm_init(pdev, NULL, sizeof(*pxav2_host)); if (IS_ERR(host)) return PTR_ERR(host); pltfm_host = sdhci_priv(host); + pxav2_host = sdhci_pltfm_priv(pltfm_host); clk = devm_clk_get(dev, "io"); if (IS_ERR(clk)) @@ -204,6 +210,15 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) goto free; } + pxav2_host->clk_core = devm_clk_get(dev, "core"); + if (!IS_ERR(pxav2_host->clk_core)) { + ret = clk_prepare_enable(pxav2_host->clk_core); + if (ret) { + dev_err(&pdev->dev, "failed to enable core clock\n"); + goto disable_io_clk; + } + } + host->quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; @@ -240,17 +255,34 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) ret = sdhci_add_host(host); if (ret) - goto disable_clk; + goto disable_core_clk; return 0; -disable_clk: +disable_core_clk: + if (!IS_ERR(pxav2_host->clk_core)) + clk_disable_unprepare(pxav2_host->clk_core); +disable_io_clk: clk_disable_unprepare(clk); free: sdhci_pltfm_free(pdev); return ret; } +static int sdhci_pxav2_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(pltfm_host); + + int ret = sdhci_pltfm_unregister(pdev); + + if (!IS_ERR(pxav2_host->clk_core)) + clk_disable_unprepare(pxav2_host->clk_core); + + return ret; +} + static struct platform_driver sdhci_pxav2_driver = { .driver = { .name = "sdhci-pxav2", @@ -259,7 +291,7 @@ static struct platform_driver sdhci_pxav2_driver = { .pm = &sdhci_pltfm_pmops, }, .probe = sdhci_pxav2_probe, - .remove = sdhci_pltfm_unregister, + .remove = sdhci_pxav2_remove, }; module_platform_driver(sdhci_pxav2_driver); From patchwork Fri Dec 2 03:13:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17CCBC4321E for ; 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([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.14.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:14:03 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 6/8] mmc: sdhci-pxav2: add SDIO card IRQ workaround for PXA168 V1 controller Date: Thu, 1 Dec 2022 19:13:28 -0800 Message-Id: <20221202031330.94130-7-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PXA168 has a documented silicon bug that causes SDIO card IRQs to be missed. Implement the first half of the suggested workaround, which involves resetting the data port logic and issuing a dummy CMD0 to restart the clock. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 1f0c3028987a..912b2aad9f2e 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -43,6 +45,7 @@ struct sdhci_pxav2_host { struct clk *clk_core; + struct mmc_request *sdio_mrq; }; static void pxav2_reset(struct sdhci_host *host, u8 mask) @@ -93,6 +96,50 @@ static u16 pxav1_readw(struct sdhci_host *host, int reg) return readw(host->ioaddr + reg); } +static u32 pxav1_irq(struct sdhci_host *host, u32 intmask) +{ + struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); + + if (pxav2_host->sdio_mrq && (intmask & SDHCI_INT_CMD_MASK)) { + /* The dummy CMD0 for the SDIO workaround just completed */ + sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); + intmask &= ~SDHCI_INT_CMD_MASK; + mmc_request_done(host->mmc, pxav2_host->sdio_mrq); + pxav2_host->sdio_mrq = NULL; + } + + return intmask; +} + +static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq) +{ + u16 tmp; + struct sdhci_pxav2_host *pxav2_host; + + /* If this is an SDIO command, perform errata workaround for silicon bug */ + if (mrq->cmd && !mrq->cmd->error && + (mrq->cmd->opcode == SD_IO_RW_DIRECT || + mrq->cmd->opcode == SD_IO_RW_EXTENDED)) { + /* Reset data port */ + tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL); + tmp |= 0x400; + writew(tmp, host->ioaddr + SDHCI_TIMEOUT_CONTROL); + + /* Clock is now stopped, so restart it by sending a dummy CMD0 */ + pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); + pxav2_host->sdio_mrq = mrq; + sdhci_writel(host, 0, SDHCI_ARGUMENT); + sdhci_writew(host, 0, SDHCI_TRANSFER_MODE); + sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE), + SDHCI_COMMAND); + + /* Don't finish this request until the dummy CMD0 finishes */ + return; + } + + mmc_request_done(host->mmc, mrq); +} + static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) { u8 ctrl; @@ -117,10 +164,12 @@ static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) static const struct sdhci_ops pxav1_sdhci_ops = { .read_w = pxav1_readw, .set_clock = sdhci_set_clock, + .irq = pxav1_irq, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = pxav2_mmc_set_bus_width, .reset = pxav2_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, + .request_done = pxav1_request_done, }; static const struct sdhci_ops pxav2_sdhci_ops = { From patchwork Fri Dec 2 03:13:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B8FEC4332F for ; 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([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:14:05 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 7/8] mmc: sdhci-pxav2: add optional pinctrl for SDIO IRQ workaround Date: Thu, 1 Dec 2022 19:13:29 -0800 Message-Id: <20221202031330.94130-8-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PXA168 errata recommends that the CMD signal should be detached from the SD bus while performing the dummy CMD0 to restart the clock. Implement this using pinctrl states. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 912b2aad9f2e..88927549b425 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -46,6 +47,9 @@ struct sdhci_pxav2_host { struct clk *clk_core; struct mmc_request *sdio_mrq; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_cmd_gpio; }; static void pxav2_reset(struct sdhci_host *host, u8 mask) @@ -104,6 +108,11 @@ static u32 pxav1_irq(struct sdhci_host *host, u32 intmask) /* The dummy CMD0 for the SDIO workaround just completed */ sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); intmask &= ~SDHCI_INT_CMD_MASK; + + /* Restore MMC function to CMD pin */ + if (pxav2_host->pinctrl && pxav2_host->pins_default) + pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_default); + mmc_request_done(host->mmc, pxav2_host->sdio_mrq); pxav2_host->sdio_mrq = NULL; } @@ -128,6 +137,11 @@ static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq) /* Clock is now stopped, so restart it by sending a dummy CMD0 */ pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); pxav2_host->sdio_mrq = mrq; + + /* Set CMD as high output rather than MMC function while we do CMD0 */ + if (pxav2_host->pinctrl && pxav2_host->pins_cmd_gpio) + pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_cmd_gpio); + sdhci_writel(host, 0, SDHCI_ARGUMENT); sdhci_writew(host, 0, SDHCI_TRANSFER_MODE); sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE), @@ -298,6 +312,21 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) if (match && of_device_is_compatible(dev->of_node, "mrvl,pxav1-mmc")) { host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE; host->ops = &pxav1_sdhci_ops; + + /* Set up optional pinctrl for PXA168 SDIO IRQ fix */ + pxav2_host->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!IS_ERR(pxav2_host->pinctrl)) { + pxav2_host->pins_cmd_gpio = pinctrl_lookup_state(pxav2_host->pinctrl, + "state_cmd_gpio"); + if (IS_ERR(pxav2_host->pins_cmd_gpio)) + pxav2_host->pins_cmd_gpio = NULL; + pxav2_host->pins_default = pinctrl_lookup_state(pxav2_host->pinctrl, + "default"); + if (IS_ERR(pxav2_host->pins_default)) + pxav2_host->pins_default = NULL; + } else { + pxav2_host->pinctrl = NULL; + } } else { host->ops = &pxav2_sdhci_ops; } From patchwork Fri Dec 2 03:13:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24AA4C4321E for ; Fri, 2 Dec 2022 03:14:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231395AbiLBDOL (ORCPT ); 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([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:14:07 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 8/8] dt-bindings: mmc: sdhci-pxa: add pxav1 Date: Thu, 1 Dec 2022 19:13:30 -0800 Message-Id: <20221202031330.94130-9-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202031330.94130-1-doug@schmorgal.com> References: <20221202031330.94130-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a compatible for the pxav1 controller in the PXA168, along with optional pinctrl properties to use for an errata workaround. Signed-off-by: Doug Brown --- .../devicetree/bindings/mmc/sdhci-pxa.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index 1c87f4218e18..8bb0eca506e5 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell PXA SDHCI v2/v3 bindings +title: Marvell PXA SDHCI v1/v2/v3 bindings maintainers: - Ulf Hansson @@ -34,6 +34,7 @@ allOf: properties: compatible: enum: + - mrvl,pxav1-mmc - mrvl,pxav2-mmc - mrvl,pxav3-mmc - marvell,armada-380-sdhci @@ -61,6 +62,22 @@ properties: - const: io - const: core + pinctrl-names: + description: + Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between SDIO CMD and + GPIO mode. + items: + - const: default + - const: state_cmd_gpio + + pinctrl-0: + description: + Should contain default pinctrl. + + pinctrl-1: + description: + Should switch CMD pin to GPIO mode as a high output. + mrvl,clk-delay-cycles: description: Specify a number of cycles to delay for tuning. $ref: /schemas/types.yaml#/definitions/uint32