From patchwork Mon Mar 25 08:08:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161021 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3675403jan; Mon, 25 Mar 2019 01:09:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqwfASlmYYrtSDAkgKUAt0U8OVspH4mbfNhAtVOGAAEce/mHkjZTQsZ/kCsRN7NU9kxCZaGq X-Received: by 2002:a17:902:8c81:: with SMTP id t1mr24172627plo.309.1553501363141; Mon, 25 Mar 2019 01:09:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553501363; cv=none; d=google.com; s=arc-20160816; b=Kg2u1RtcJGul1L39S+UqX9Nag7PcE79+TDpEnhuqJeNRppLzs1xbhu27CpDzAdcg3P UzCFFHY25+fTHVpyQWhjtqLShqUwHemOEowrQu72XtI6ZWD+EnupqnSiA+Rmh7AyoiEy SuFn87RixuKINVMCNve2L51IHun9eEty4irx9Zt6Cge7CjxXSs8Ihw+HOLY+i0fHqBh6 lUA+ErXAtAeuMWynlY9K9pLoNnAWnBU8RbPHK3uMd5pSjQ7isBmzaSlNp9AJ+2eNCbIa 4fpQz7LI2eTMtILeHwypyqQv/vGEKHv2QNjH25uMf4+3jPoGbQ5HKpzo7DZbTPUXHImA cC0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=uf3kjAaOPFCPxUbTLMm7tK0cexSLaZI+4gMmasE/zBA=; b=LoER4IrNYNaUjOxxjT8gD/OnF617Qc2O2TAACGxULREZpF9UWJj7Divlaq6YeRMVHo cwAalQQxLnwW+fJHrsAyruET+wMMrFSe7WnNfUv2NVYfdYfIB2JY7QNaEUH+6y+SnYiC Oi8WRKLs+9TjpSsc+efs+CmNB0SBKWTxnj6uSHAXh0A5Fxz5/eWr7nYlsbE7PbVJVXUL oXMXR1a5qrgbaZ862pG3ODsJDs3TvPjXHc9XmgzzGs3ForaBfu5hIxXZsFYmmoHcVbez r7thEE8H8U3So7TIoOy7IGnEgIF5GGuTqvmndCAt+Uw+N+UVcdYvh0NSw8gOuDlhSe9V 5++A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kIk7vXj7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e18si12873874pfn.164.2019.03.25.01.09.22; Mon, 25 Mar 2019 01:09:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kIk7vXj7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730019AbfCYIJV (ORCPT + 31 others); Mon, 25 Mar 2019 04:09:21 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:47934 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729812AbfCYIJR (ORCPT ); Mon, 25 Mar 2019 04:09:17 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P89FRU091487; Mon, 25 Mar 2019 03:09:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553501355; bh=uf3kjAaOPFCPxUbTLMm7tK0cexSLaZI+4gMmasE/zBA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kIk7vXj7bFQRnf4zxkZhKmUqlmpKly/I82wFOBloMUZZSZ4XUibzXwMsBaNuxW7j/ l26yGJGVpq6HhMvb968h7omh5LA4vtZXTYVCUYIcOS6Aex4Aq+3cERV3eIVPldQ4xJ bo6hByKqwjzNlHNT9onvt6XFVE4SxfTaKTAQ08bw= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P89FiU053857 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:09:15 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:09:14 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:09:15 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P89AkX019470; Mon, 25 Mar 2019 03:09:13 -0500 From: Kishon Vijay Abraham I To: Rob Herring , Roger Quadros , Kishon Vijay Abraham I CC: , Subject: [PATCH v3 1/5] phy: core: Add *release* phy_ops invoked when the consumer relinquishes PHY Date: Mon, 25 Mar 2019 13:38:11 +0530 Message-ID: <20190325080815.6056-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325080815.6056-1-kishon@ti.com> References: <20190325080815.6056-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new phy_ops *release* invoked when the consumer relinquishes the PHY using phy_put/devm_phy_put. The initializations done by the PHY driver in of_xlate call back can be can be cleaned up here. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-core.c | 5 +++++ include/linux/phy/phy.h | 2 ++ 2 files changed, 7 insertions(+) -- 2.17.1 diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index cb38f6e8614c..b9a4ebf35dd3 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -564,6 +564,11 @@ void phy_put(struct phy *phy) if (!phy || IS_ERR(phy)) return; + mutex_lock(&phy->mutex); + if (phy->ops->release) + phy->ops->release(phy); + mutex_unlock(&phy->mutex); + module_put(phy->ops->owner); put_device(&phy->dev); } diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 3f350e2749fe..ef13aea1d370 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -64,6 +64,7 @@ union phy_configure_opts { * @set_mode: set the mode of the phy * @reset: resetting the phy * @calibrate: calibrate the phy + * @release: ops to be performed while the consumer relinquishes the PHY * @owner: the module owner containing the ops */ struct phy_ops { @@ -105,6 +106,7 @@ struct phy_ops { union phy_configure_opts *opts); int (*reset)(struct phy *phy); int (*calibrate)(struct phy *phy); + void (*release)(struct phy *phy); struct module *owner; }; From patchwork Mon Mar 25 08:08:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161025 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3675700jan; Mon, 25 Mar 2019 01:09:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzkYCC9IsN2RWW11EQRazan0C4v8csF1MBa4l3CBuQ1B9A3DBtexBvYouDhObxX9aG2U4am X-Received: by 2002:a65:4bcc:: with SMTP id p12mr22163495pgr.187.1553501382560; Mon, 25 Mar 2019 01:09:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553501382; cv=none; d=google.com; s=arc-20160816; b=iixqKoPKcKBoRwU1o4k0F9r4h9rBTzb33xCfi5uN6ysGqJwKKucIA/bTkt5zXGqtSs IgZ4MM6rbAGLBNW9xWdI5r7uHfOjkXGHcnnbhZ+2IOKX3CC2Zu/1XU3SWVG8puSp1g4w hd0VWKkOcih2LzUz3xx85RCSeZw4sOBTfXpDjmnOjTzTiyQn8fqrD6ZFpfpITS65znRU 7gDqTzrjY+avsLM/Aq7K5hQSFQVG+Z3p+oE4mo4kOWsls+8GrjWlZngc4i+M/hVfnhc4 1KXaOFtMJ8L+XbMRyY+2jxruEiIQpA2JnFMY683Ne4GLoEaRgAiINXcO5V5uZVsEvSrD BI/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=/QInjG/03abJVlZotne87DnL13Y9btTLzIL3PeoAEIk=; b=pACPYuNwIjWwDjfpv+VGAzt/0w44j1FdQOI9tvv4I4Mv4rA3opkhRb69S5pf9YDjnJ t3S2DQeHv8i6bNHyz9GCxs+SXW1A7jSsEV1lDzXW3jgtod44RNFoRThsmtleNTFLJMW/ GD3x/V0TaiZkRUebmR3ObOVQbmkr4PIPD6lUOcuUARqG/p+7fsv4qRY8/2/CMThLJYIU nVYKsIFFGYVXz/DI/ypFVRQZjWNG3AF+ZSQjMNA5p+l5+juonMj+pSdynfJgEJ2Lw/iI hafq4IMjqRrCsWDGIINY0CIa0XQUhDLp6lyQOiQZxdWc8pxPfa+/G3moNTeBJtl0PzGB Ip2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lrihuwEl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d8si13468702plo.41.2019.03.25.01.09.42; Mon, 25 Mar 2019 01:09:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lrihuwEl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730003AbfCYIJV (ORCPT + 31 others); Mon, 25 Mar 2019 04:09:21 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:57316 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729946AbfCYIJT (ORCPT ); Mon, 25 Mar 2019 04:09:19 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P89HxJ015494; Mon, 25 Mar 2019 03:09:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553501357; bh=/QInjG/03abJVlZotne87DnL13Y9btTLzIL3PeoAEIk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lrihuwEl22andwhovLQ3v3aELCu7Z7mJH/bw8JrIRm+GvrDJUUxaxPFUSh7SJCnzM LmlxlLSNRBX/8zO8fC281/9wiJCUmhdSgDnNb9lyurLXNFkMwUFkWZDT21GeUfupYl SNwiWSD+UQyqJhq4kW5+I+RNidf0nrP1z640uIwQ= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P89HFZ051420 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:09:17 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:09:16 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:09:16 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P89AkY019470; Mon, 25 Mar 2019 03:09:15 -0500 From: Kishon Vijay Abraham I To: Rob Herring , Roger Quadros , Kishon Vijay Abraham I CC: , Subject: [PATCH v3 2/5] phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset callback Date: Mon, 25 Mar 2019 13:38:12 +0530 Message-ID: <20190325080815.6056-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325080815.6056-1-kishon@ti.com> References: <20190325080815.6056-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PHY drivers may try to access PHY registers in the ->reset() callback. Invoke phy_pm_runtime_get_sync() before invoking the ->reset() callback so that the PHY drivers don't have to enable clocks by themselves before accessing PHY registers. Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-core.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index b9a4ebf35dd3..c147ba843f0b 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -384,10 +384,16 @@ int phy_reset(struct phy *phy) if (!phy || !phy->ops->reset) return 0; + ret = phy_pm_runtime_get_sync(phy); + if (ret < 0 && ret != -ENOTSUPP) + return ret; + mutex_lock(&phy->mutex); ret = phy->ops->reset(phy); mutex_unlock(&phy->mutex); + phy_pm_runtime_put(phy); + return ret; } EXPORT_SYMBOL_GPL(phy_reset); From patchwork Mon Mar 25 08:08:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161024 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3675587jan; Mon, 25 Mar 2019 01:09:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqyZ2krb1R61MVdkz4ZDkHb+0yWvkrea1HR54ZvOhCtOlZAGjKNu2KI8UkiLoWfjJLUFmOVB X-Received: by 2002:a62:3849:: with SMTP id f70mr19647673pfa.46.1553501376404; Mon, 25 Mar 2019 01:09:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553501376; cv=none; d=google.com; s=arc-20160816; b=R09+OGoaeGseQKZ1+lXFFDNUciOyniRX8ZljELg1yk13tnBJIC8xONdxqO9tYC80pp D91H9uCxABkONbiahkPTWUpD2aih8dhv5yAHU9WO2mf3FVAioZ33lAxeeOF04FbjXamx 6FZItui+OyUnuBcMRxCxiqNkGvNBZjh8SpChL1v0qQxnNlD+M1Stf9XoouxCM6EosAmz oxP67zYDpZ/aXYYAetrFPOdMhOaouvjAwVxhMNoEYuFZP3yUo2OL+lnnHdKSjDwdbUMQ uTldhNrf1+OAHmY7Wh88lwW8Rc9hzZNGnsdMkn3Ioqc62bbrbb8RfZJ4kEVdr6wJObTe QkRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8yZACXx3zQ5PlcI3+3uGL1g1pNCyWUs2yA7H0kvr23g=; b=o9EzDmxx68HNueXua7IkiApb4EZOa2LxJI5F7QGw7tJBW8lm2v23TivmnUvOoFhXT3 yOTy3vjqsXdc9oQw2dOxat/0zDvnS+D7OA5YtC+4B25XfU8rL9vEuIUsciVvqMxmXcEl AYC2aK1V3cYxfg6r91n6a7G3m0S5NtKEEGP8WOnbiewKjlG+f98pF1u7HJeGTxulDTYd Duvw9sjK9diJFylTKtCTuSrG4B1lYUIrEqKJdU9U7toeZYG3CN1SSEbR05HvN6WR1JXL v1fVd3/UTkbIYaQVg1N/WjudF5i+tp1VJJHcQG6j/TOQcU+P7FecLd2tolvBeg3Fb8CS GJng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wmzI1eQb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p24si11653502pfd.288.2019.03.25.01.09.35; Mon, 25 Mar 2019 01:09:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wmzI1eQb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730035AbfCYIJX (ORCPT + 31 others); Mon, 25 Mar 2019 04:09:23 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:60496 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729947AbfCYIJV (ORCPT ); Mon, 25 Mar 2019 04:09:21 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P89JV9024648; Mon, 25 Mar 2019 03:09:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553501359; bh=8yZACXx3zQ5PlcI3+3uGL1g1pNCyWUs2yA7H0kvr23g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wmzI1eQbVimXM6wYVFODQwo1AdN84WmC4Nz5q+OnFwd46yoq1Ch9WPjBp6EInLnWD 3E+oEl6B/cz8bRVyZ5TvbM5dZvYlQH+QJR+Qhziq5cn8c88IleIdyK+zynrvrHs8dn TaQYJwnU3uFZPQR44Agwu4nek7FDnRUBg+5258cQ= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P89JQs108773 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:09:19 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:09:18 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:09:18 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P89AkZ019470; Mon, 25 Mar 2019 03:09:17 -0500 From: Kishon Vijay Abraham I To: Rob Herring , Roger Quadros , Kishon Vijay Abraham I CC: , Subject: [PATCH v3 3/5] dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC Date: Mon, 25 Mar 2019 13:38:13 +0530 Message-ID: <20190325080815.6056-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325080815.6056-1-kishon@ti.com> References: <20190325080815.6056-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/ti,phy-am654-serdes.txt | 81 +++++++++++++++++++ include/dt-bindings/phy/phy-am654-serdes.h | 13 +++ 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.txt create mode 100644 include/dt-bindings/phy/phy-am654-serdes.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.txt b/Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.txt new file mode 100644 index 000000000000..25a9206147ad --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.txt @@ -0,0 +1,81 @@ +TI AM654 SERDES + +Required properties: + - compatible: Should be "ti,phy-am654-serdes" + - reg : Address and length of the register set for the device. + - reg-names: Should be "serdes" which corresponds to the register space + populated in "reg". + - #phy-cells: determine the number of cells that should be given in the + phandle while referencing this phy. Should be "2". The 1st cell + corresponds to the phy type (should be one of the types specified in + include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes + lane function. + If SERDES0 is referenced 2nd cell should be: + 0 - USB3 + 1 - PCIe0 Lane0 + 2 - ICSS2 SGMII Lane0 + If SERDES1 is referenced 2nd cell should be: + 0 - PCIe1 Lane0 + 1 - PCIe0 Lane1 + 2 - ICSS2 SGMII Lane1 + - clocks: List of clock-specifiers representing the input to the SERDES. + Should have 3 items representing the left input clock, external + reference clock and right input clock in that order. + - clock-output-names: List of clock names for each of the clock outputs of + SERDES. Should have 3 items for CMU reference clock, + left output clock and right output clock in that order. + - assigned-clocks: As defined in + Documentation/devicetree/bindings/clock/clock-bindings.txt + - assigned-clock-parents: As defined in + Documentation/devicetree/bindings/clock/clock-bindings.txt + - #clock-cells: Should be <1> to choose between the 3 output clocks. + Defined in Documentation/devicetree/bindings/clock/clock-bindings.txt + + The following macros are defined in dt-bindings/phy/phy-am654-serdes.h + for selecting the correct reference clock. This can be used while + specifying the clocks created by SERDES. + => AM654_SERDES_CMU_REFCLK + => AM654_SERDES_LO_REFCLK + => AM654_SERDES_RO_REFCLK + + - mux-controls: phandle to the multiplexer + +Example: + +Example for SERDES0 is given below. It has 3 clock inputs; +left input reference clock as indicated by <&k3_clks 153 4>, external +reference clock as indicated by <&k3_clks 153 1> and right input +reference clock as indicated by <&serdes1 AM654_SERDES_LO_REFCLK>. (The +right input of SERDES0 is connected to the left output of SERDES1). + +SERDES0 registers 3 clock outputs as indicated in clock-output-names. The +first refers to the CMU reference clock, second refers to the left output +reference clock and the third refers to the right output reference clock. + +The assigned-clocks and assigned-clock-parents is used here to set the +parent of left input reference clock to MAINHSDIV_CLKOUT4 and parent of +CMU reference clock to left input reference clock. + +serdes0: serdes@900000 { + compatible = "ti,phy-am654-serdes"; + reg = <0x0 0x900000 0x0 0x2000>; + reg-names = "serdes"; + #phy-cells = <2>; + power-domains = <&k3_pds 153>; + clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, + <&serdes1 AM654_SERDES_LO_REFCLK>; + clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", + "serdes0_ro_refclk"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; + ti,serdes-clk = <&serdes0_clk>; + mux-controls = <&serdes_mux 0>; + #clock-cells = <1>; +}; + +Example for PCIe consumer node using the SERDES PHY specifier is given below. +&pcie0_rc { + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h new file mode 100644 index 000000000000..e8d901729ed9 --- /dev/null +++ b/include/dt-bindings/phy/phy-am654-serdes.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for AM654 SERDES. + */ + +#ifndef _DT_BINDINGS_AM654_SERDES +#define _DT_BINDINGS_AM654_SERDES + +#define AM654_SERDES_CMU_REFCLK 0 +#define AM654_SERDES_LO_REFCLK 1 +#define AM654_SERDES_RO_REFCLK 2 + +#endif /* _DT_BINDINGS_AM654_SERDES */ From patchwork Mon Mar 25 08:08:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161022 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3675463jan; Mon, 25 Mar 2019 01:09:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3C/8g2BoiWCYysRkLu5JqB5shRiOGbIH+DouvjqjcDeb1d/a2+i/q8LgNLO7ZPraKyzhR X-Received: by 2002:a62:e518:: with SMTP id n24mr4413596pff.174.1553501367626; Mon, 25 Mar 2019 01:09:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553501367; cv=none; d=google.com; s=arc-20160816; b=FwEzLFZA2sWvRBNvwSxlneNW3EwSmzmSWUR/ti4Y0/DqipgFpf7CQ4pkyWr9CmFC5c BfZ/c8lEsavojx24MxLpAVflEsms/1/FWcxtaLQ0a9MzJG0d3v6dQV1rwVWY0GSl1GwN 9ob2lw8cKTb4aoj/8nfANbU7SFdncSniva4he1QenfX9RRiJUqefmrzTbr2hxukpU2j/ PVw6miaC/1Y1mnVbpWlexxxKFr2XfP+K3DDj+U7/yTG1hPkxLXQATANvxl5Fc94FCtMT nzoTtobahXHkeHodGHZi18O+O1FKXY/2BWIUWSX7e9Lrn3Y99lpzEoebrTXgy/KGEfdH Pp8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=rOI7mLJridAFOKzDa6rVOyMwDmJYT9+QBT/s2gkAXKY=; b=P3eDLYg9mun8czo2tlK1P1F2mor99zbDb24feHbpsPEqAJu+RmWTssoSvJfE2zgm2a G0JgDxPBXJuiCmlzREUPbpEpKAbhVpANRYu1nZnJsK7ICQhhJGYj2d9O8bEToQBDBIgw dkEPT6zXXlQaIRxEc+XIzytjQtcr+bF358Cdj9ba7aXjExykjpeN2RT7HcIBFYaCMgZi wWLvSuNkXx+lo5HeFmaul6FWwaUt+4IdLD6v7cUErGQF59QXBGP8P8Iv5N4VhygfLsfl +riEtmeUQQUh+jRYSJfbYyqhoYEfui1NQllb5dqgtuEAzk5Om2n2xTWZUlQPeprp6bNx k+8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="jGhvy/wZ"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p6si110233pgp.459.2019.03.25.01.09.27; Mon, 25 Mar 2019 01:09:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="jGhvy/wZ"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730048AbfCYIJZ (ORCPT + 31 others); Mon, 25 Mar 2019 04:09:25 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:47942 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730023AbfCYIJX (ORCPT ); Mon, 25 Mar 2019 04:09:23 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P89LlB091528; Mon, 25 Mar 2019 03:09:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553501361; bh=rOI7mLJridAFOKzDa6rVOyMwDmJYT9+QBT/s2gkAXKY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jGhvy/wZhVBNx/3JPvvitDh3Vz0RRSLFORHlrvEOav+SLTRS+jHpnLjBtDIUZjnF2 0cgHEU76Lqq+6NV6+47JzRIUy4vAQB8l7soUMjyAyQQbmLyOUY+ak841DBpCu4YQS7 fKVtcLctqJYP1v0HtOa1+mCO2QwhEII8tNDbLcnM= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P89LWS014461 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:09:21 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:09:20 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:09:21 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P89Aka019470; Mon, 25 Mar 2019 03:09:19 -0500 From: Kishon Vijay Abraham I To: Rob Herring , Roger Quadros , Kishon Vijay Abraham I CC: , Subject: [PATCH v3 4/5] phy: ti: Add a new SERDES driver for TI's AM654x SoC Date: Mon, 25 Mar 2019 13:38:14 +0530 Message-ID: <20190325080815.6056-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325080815.6056-1-kishon@ti.com> References: <20190325080815.6056-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 will be added later. SERDES in am654x has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. [rogerq@ti.com: Fix boot lockup caused by accessing a structure member (hw->init) allocated in stack of probe() and accessed in get_parent] [rogerq@ti.com: Fix "Failed to find the parent" warnings] Signed-off-by: Roger Quadros Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/Kconfig | 12 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-am654-serdes.c | 539 ++++++++++++++++++++++++++++++ 3 files changed, 552 insertions(+) create mode 100644 drivers/phy/ti/phy-am654-serdes.c -- 2.17.1 diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 7cdc35f8c862..6931c87235b9 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -20,6 +20,18 @@ config PHY_DM816X_USB help Enable this for dm816x USB to work. +config PHY_AM654_SERDES + tristate "TI AM654 SERDES support" + depends on OF && ARCH_K3 || COMPILE_TEST + depends on COMMON_CLK + select GENERIC_PHY + select MULTIPLEXER + select REGMAP_MMIO + select MUX_MMIO + help + This option enables support for TI AM654 SerDes PHY used for + PCIe. + config OMAP_CONTROL_PHY tristate "OMAP CONTROL PHY Driver" depends on ARCH_OMAP2PLUS || COMPILE_TEST diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile index 368de8e1548d..601bbd88f35e 100644 --- a/drivers/phy/ti/Makefile +++ b/drivers/phy/ti/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o obj-$(CONFIG_PHY_TI_GMII_SEL) += phy-gmii-sel.o obj-$(CONFIG_PHY_TI_KEYSTONE_SERDES) += phy-keystone-serdes.o diff --git a/drivers/phy/ti/phy-am654-serdes.c b/drivers/phy/ti/phy-am654-serdes.c new file mode 100644 index 000000000000..dfbd2d48503d --- /dev/null +++ b/drivers/phy/ti/phy-am654-serdes.c @@ -0,0 +1,539 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * PCIe SERDES driver for AM654x SoC + * + * Copyright (C) 2018 Texas Instruments + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CMU_R07C 0x7c +#define CMU_MASTER_CDN_O BIT(24) + +#define COMLANE_R138 0xb38 +#define CONFIG_VERSION_REG_MASK GENMASK(23, 16) +#define CONFIG_VERSION_REG_SHIFT 16 +#define VERSION 0x70 + +#define COMLANE_R190 0xb90 +#define L1_MASTER_CDN_O BIT(9) + +#define COMLANE_R194 0xb94 +#define CMU_OK_I_0 BIT(19) + +#define SERDES_CTRL 0x1fd0 +#define POR_EN BIT(29) + +#define WIZ_LANEXCTL_STS 0x1fe0 +#define TX0_ENABLE_OVL BIT(31) +#define TX0_ENABLE_MASK GENMASK(30, 29) +#define TX0_ENABLE_SHIFT 29 +#define TX0_DISABLE_STATE 0x0 +#define TX0_SLEEP_STATE 0x1 +#define TX0_SNOOZE_STATE 0x2 +#define TX0_ENABLE_STATE 0x3 +#define RX0_ENABLE_OVL BIT(15) +#define RX0_ENABLE_MASK GENMASK(14, 13) +#define RX0_ENABLE_SHIFT 13 +#define RX0_DISABLE_STATE 0x0 +#define RX0_SLEEP_STATE 0x1 +#define RX0_SNOOZE_STATE 0x2 +#define RX0_ENABLE_STATE 0x3 + +#define WIZ_PLL_CTRL 0x1ff4 +#define PLL_ENABLE_OVL BIT(31) +#define PLL_ENABLE_MASK GENMASK(30, 29) +#define PLL_ENABLE_SHIFT 29 +#define PLL_DISABLE_STATE 0x0 +#define PLL_SLEEP_STATE 0x1 +#define PLL_SNOOZE_STATE 0x2 +#define PLL_ENABLE_STATE 0x3 +#define PLL_OK BIT(28) + +#define PLL_LOCK_TIME 100000 /* in microseconds */ +#define SLEEP_TIME 100 /* in microseconds */ + +#define LANE_USB3 0x0 +#define LANE_PCIE0_LANE0 0x1 + +#define LANE_PCIE1_LANE0 0x0 +#define LANE_PCIE0_LANE1 0x1 + +#define SERDES_NUM_CLOCKS 3 + +struct serdes_am654_clk_mux { + struct clk_hw hw; + struct regmap *regmap; + unsigned int reg; + int *table; + u32 mask; + u8 shift; + struct clk_init_data clk_data; +}; + +#define to_serdes_am654_clk_mux(_hw) \ + container_of(_hw, struct serdes_am654_clk_mux, hw) + +static struct regmap_config serdes_am654_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +struct serdes_am654 { + struct regmap *regmap; + struct device *dev; + struct mux_control *control; + bool busy; + u32 type; + struct device_node *of_node; + struct clk_onecell_data clk_data; + struct clk *clks[SERDES_NUM_CLOCKS]; +}; + +static int serdes_am654_enable_pll(struct serdes_am654 *phy) +{ + u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK; + u32 val = PLL_ENABLE_OVL | (PLL_ENABLE_STATE << PLL_ENABLE_SHIFT); + + regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, val); + + return regmap_read_poll_timeout(phy->regmap, WIZ_PLL_CTRL, val, + val & PLL_OK, 1000, PLL_LOCK_TIME); +} + +static void serdes_am654_disable_pll(struct serdes_am654 *phy) +{ + u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK; + + regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, PLL_ENABLE_OVL); +} + +static int serdes_am654_enable_txrx(struct serdes_am654 *phy) +{ + u32 mask; + u32 val; + + /* Enable TX */ + mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK; + val = TX0_ENABLE_OVL | (TX0_ENABLE_STATE << TX0_ENABLE_SHIFT); + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val); + + /* Enable RX */ + mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK; + val = RX0_ENABLE_OVL | (RX0_ENABLE_STATE << RX0_ENABLE_SHIFT); + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val); + + return 0; +} + +static int serdes_am654_disable_txrx(struct serdes_am654 *phy) +{ + u32 mask; + + /* Disable TX */ + mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK; + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, TX0_ENABLE_OVL); + + /* Disable RX */ + mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK; + regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, RX0_ENABLE_OVL); + + return 0; +} + +static int serdes_am654_power_on(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + struct device *dev = phy->dev; + int ret; + u32 val; + + ret = serdes_am654_enable_pll(phy); + if (ret) { + dev_err(dev, "Failed to enable PLL\n"); + return ret; + } + + ret = serdes_am654_enable_txrx(phy); + if (ret) { + dev_err(dev, "Failed to enable TX RX\n"); + return ret; + } + + return regmap_read_poll_timeout(phy->regmap, COMLANE_R194, val, + val & CMU_OK_I_0, SLEEP_TIME, + PLL_LOCK_TIME); +} + +static int serdes_am654_power_off(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + + serdes_am654_disable_txrx(phy); + serdes_am654_disable_pll(phy); + + return 0; +} + +static int serdes_am654_init(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + u32 mask; + u32 val; + + mask = CONFIG_VERSION_REG_MASK; + val = VERSION << CONFIG_VERSION_REG_SHIFT; + regmap_update_bits(phy->regmap, COMLANE_R138, mask, val); + + val = CMU_MASTER_CDN_O; + regmap_update_bits(phy->regmap, CMU_R07C, val, val); + + val = L1_MASTER_CDN_O; + regmap_update_bits(phy->regmap, COMLANE_R190, val, val); + + return 0; +} + +static int serdes_am654_reset(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + u32 val; + + val = POR_EN; + regmap_update_bits(phy->regmap, SERDES_CTRL, val, val); + mdelay(1); + regmap_update_bits(phy->regmap, SERDES_CTRL, val, 0); + + return 0; +} + +static void serdes_am654_release(struct phy *x) +{ + struct serdes_am654 *phy = phy_get_drvdata(x); + + phy->type = PHY_NONE; + phy->busy = false; + mux_control_deselect(phy->control); +} + +struct phy *serdes_am654_xlate(struct device *dev, struct of_phandle_args + *args) +{ + struct serdes_am654 *am654_phy; + struct phy *phy; + int ret; + + phy = of_phy_simple_xlate(dev, args); + if (IS_ERR(phy)) + return phy; + + am654_phy = phy_get_drvdata(phy); + if (am654_phy->busy) + return ERR_PTR(-EBUSY); + + ret = mux_control_select(am654_phy->control, args->args[1]); + if (ret) { + dev_err(dev, "Failed to select SERDES Lane Function\n"); + return ERR_PTR(ret); + } + + am654_phy->busy = true; + am654_phy->type = args->args[0]; + + return phy; +} + +static const struct phy_ops ops = { + .reset = serdes_am654_reset, + .init = serdes_am654_init, + .power_on = serdes_am654_power_on, + .power_off = serdes_am654_power_off, + .release = serdes_am654_release, + .owner = THIS_MODULE, +}; + +static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw) +{ + struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); + unsigned int num_parents = clk_hw_get_num_parents(hw); + struct regmap *regmap = mux->regmap; + unsigned int reg = mux->reg; + unsigned int val; + int i; + + regmap_read(regmap, reg, &val); + val >>= mux->shift; + val &= mux->mask; + + for (i = 0; i < num_parents; i++) + if (mux->table[i] == val) + return i; + + /* + * No parent? This should never happen! + * Verify if we set a valid parent in serdes_am654_clk_register() + */ + WARN(1, "Failed to find the parent of %s clock\n", hw->init->name); + + /* Make the parent lookup to fail */ + return num_parents; +} + +static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); + struct regmap *regmap = mux->regmap; + unsigned int reg = mux->reg; + int val; + int ret; + + val = mux->table[index]; + + if (val == -1) + return -EINVAL; + + val <<= mux->shift; + ret = regmap_update_bits(regmap, reg, mux->mask << mux->shift, val); + + return ret; +} + +static const struct clk_ops serdes_am654_clk_mux_ops = { + .set_parent = serdes_am654_clk_mux_set_parent, + .get_parent = serdes_am654_clk_mux_get_parent, +}; + +static int mux_table[SERDES_NUM_CLOCKS][3] = { + /* + * The entries represent values for selecting between + * {left input, external reference clock, right input} + * Only one of Left Output or Right Output should be used since + * both left and right output clock uses the same bits and modifying + * one clock will impact the other. + */ + { BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */ + { -1, BIT(3), BIT(1) }, /* Mux of Left Output */ + { BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */ +}; + +static int mux_mask[SERDES_NUM_CLOCKS] = { 0x5, 0xa, 0xa }; + +static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, + const char *clock_name, int clock_num) +{ + struct device_node *node = am654_phy->of_node; + struct device *dev = am654_phy->dev; + struct serdes_am654_clk_mux *mux; + struct device_node *regmap_node; + const char **parent_names; + struct clk_init_data *init; + unsigned int num_parents; + struct regmap *regmap; + const __be32 *addr; + unsigned int reg; + struct clk *clk; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + init = &mux->clk_data; + + regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0); + of_node_put(regmap_node); + if (!regmap_node) { + dev_err(dev, "Fail to get serdes-clk node\n"); + return -ENODEV; + } + + regmap = syscon_node_to_regmap(regmap_node->parent); + if (IS_ERR(regmap)) { + dev_err(dev, "Fail to get Syscon regmap\n"); + return PTR_ERR(regmap); + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "SERDES clock must have parents\n"); + return -EINVAL; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + of_clk_parent_fill(node, parent_names, num_parents); + + addr = of_get_address(regmap_node, 0, NULL, NULL); + if (!addr) + return -EINVAL; + + reg = be32_to_cpu(*addr); + + init->ops = &serdes_am654_clk_mux_ops; + init->flags = CLK_SET_RATE_NO_REPARENT; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clock_name; + + mux->table = mux_table[clock_num]; + mux->regmap = regmap; + mux->reg = reg; + mux->shift = 4; + mux->mask = mux_mask[clock_num]; + mux->hw.init = init; + + /* + * setup a sane default so get_parent() call evaluates + * to a valid parent. Index 1 is the safest choice as + * the default as it is valid value for all of serdes's + * output clocks. + */ + serdes_am654_clk_mux_set_parent(&mux->hw, 1); + clk = devm_clk_register(dev, &mux->hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + am654_phy->clks[clock_num] = clk; + + return 0; +} + +static const struct of_device_id serdes_am654_id_table[] = { + { + .compatible = "ti,phy-am654-serdes", + }, + {} +}; +MODULE_DEVICE_TABLE(of, serdes_am654_id_table); + +static int serdes_am654_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct clk_onecell_data *clk_data; + struct serdes_am654 *am654_phy; + struct mux_control *control; + const char *clock_name; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + struct phy *phy; + int ret; + int i; + + am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL); + if (!am654_phy) + return -ENOMEM; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "serdes"); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to initialize regmap\n"); + return PTR_ERR(regmap); + } + + control = devm_mux_control_get(dev, NULL); + if (IS_ERR(control)) + return PTR_ERR(control); + + am654_phy->dev = dev; + am654_phy->of_node = node; + am654_phy->regmap = regmap; + am654_phy->control = control; + am654_phy->type = PHY_NONE; + + platform_set_drvdata(pdev, am654_phy); + + for (i = 0; i < SERDES_NUM_CLOCKS; i++) { + ret = of_property_read_string_index(node, "clock-output-names", + i, &clock_name); + if (ret) { + dev_err(dev, "Failed to get clock name\n"); + return ret; + } + + ret = serdes_am654_clk_register(am654_phy, clock_name, i); + if (ret) { + dev_err(dev, "Failed to initialize clock %s\n", + clock_name); + return ret; + } + } + + clk_data = &am654_phy->clk_data; + clk_data->clks = am654_phy->clks; + clk_data->clk_num = SERDES_NUM_CLOCKS; + ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (ret) + return ret; + + pm_runtime_enable(dev); + + phy = devm_phy_create(dev, NULL, &ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, am654_phy); + phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate); + if (IS_ERR(phy_provider)) { + ret = PTR_ERR(phy_provider); + goto clk_err; + } + + return 0; + +clk_err: + of_clk_del_provider(node); + + return ret; +} + +static int serdes_am654_remove(struct platform_device *pdev) +{ + struct serdes_am654 *am654_phy = platform_get_drvdata(pdev); + struct device_node *node = am654_phy->of_node; + + pm_runtime_disable(&pdev->dev); + of_clk_del_provider(node); + + return 0; +} + +static struct platform_driver serdes_am654_driver = { + .probe = serdes_am654_probe, + .remove = serdes_am654_remove, + .driver = { + .name = "phy-am654", + .of_match_table = serdes_am654_id_table, + }, +}; +module_platform_driver(serdes_am654_driver); + +MODULE_ALIAS("platform:phy-am654"); +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TI AM654x SERDES driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon Mar 25 08:08:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161023 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3675514jan; Mon, 25 Mar 2019 01:09:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqxrlS/CLTkdwsnAGz7JrnZV8QeWjdnCeujciDJOWqTRrgpMR2PxsCekaUYIHTFXVJEtD1Fn X-Received: by 2002:a62:b602:: with SMTP id j2mr9841855pff.68.1553501371033; Mon, 25 Mar 2019 01:09:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553501371; cv=none; d=google.com; s=arc-20160816; b=pq4+7XZn3HR6UQhbGBIP/wCGS4wlldQtcaOmrz367z7Pi7DBgHv2tL8abiVLBJZeCj +Pnl9cZzEfRk2NKBlLvI9TS+TuFUma1AWSfUXIqYrUUO3YUrXiw3/qUfS6luJPfgpe3m J/UDsnf8/2Itus7oup+0Bw0rzoU6tbH/ONCUcUUfLM1TlWYPhdpeOiJ+DhHi0rl0S5eA 8HtMlrEqs0jnrd51spqLKrlgE17KDWnTy70F+/VCNpWghW3LuaVsMI3MLa5e375u0grH Z7M97jNF44+JvH9OeuxaiaVwUWj3Qzu8ksxUcDmRlhhAgePUolx27dhsK55xV5XzgEqh ++6Q== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id p6si110233pgp.459.2019.03.25.01.09.30; Mon, 25 Mar 2019 01:09:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VeadLbkH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730061AbfCYIJ3 (ORCPT + 31 others); Mon, 25 Mar 2019 04:09:29 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:47950 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730038AbfCYIJY (ORCPT ); Mon, 25 Mar 2019 04:09:24 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P89NtE091548; Mon, 25 Mar 2019 03:09:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553501363; bh=9EQi3vlM0iUSThf0vyQ588m5f8DN1b6p1f6u7YdBdQ4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VeadLbkHsoDHzDSAoDsFxJKSNIDcbTZVbbNsy5kO5OSt53nUzm5q8DsYgviAAreqR sgN4KuOITwPM1FoDbeKN+HXiZLNKgBxdBEyK7HWx/R/NQ9WCMs60/XqVbICatXdoUe fNMxZWDaWgdA+Km8AK4sdZJxefPbUZOxlUzXAfrA= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P89N5Z014488 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:09:23 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:09:22 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:09:22 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P89Akb019470; Mon, 25 Mar 2019 03:09:21 -0500 From: Kishon Vijay Abraham I To: Rob Herring , Roger Quadros , Kishon Vijay Abraham I CC: , Subject: [PATCH v3 5/5] phy: ti: am654-serdes: Support all clksel values Date: Mon, 25 Mar 2019 13:38:15 +0530 Message-ID: <20190325080815.6056-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325080815.6056-1-kishon@ti.com> References: <20190325080815.6056-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Roger Quadros Add support to select all 16 CLKSEL combinations that are shown in "SerDes Reference Clock Distribution" in AM65 TRM. Signed-off-by: Roger Quadros Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-am654-serdes.c | 134 +++++++++++++++++++----------- 1 file changed, 84 insertions(+), 50 deletions(-) -- 2.17.1 diff --git a/drivers/phy/ti/phy-am654-serdes.c b/drivers/phy/ti/phy-am654-serdes.c index dfbd2d48503d..f2d8d9b043cb 100644 --- a/drivers/phy/ti/phy-am654-serdes.c +++ b/drivers/phy/ti/phy-am654-serdes.c @@ -2,7 +2,7 @@ /** * PCIe SERDES driver for AM654x SoC * - * Copyright (C) 2018 Texas Instruments + * Copyright (C) 2018 - 2019 Texas Instruments * Author: Kishon Vijay Abraham I */ @@ -76,13 +76,14 @@ #define SERDES_NUM_CLOCKS 3 +#define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4) +#define AM654_SERDES_CTRL_CLKSEL_SHIFT 4 + struct serdes_am654_clk_mux { struct clk_hw hw; struct regmap *regmap; unsigned int reg; - int *table; - u32 mask; - u8 shift; + int clk_id; struct clk_init_data clk_data; }; @@ -269,31 +270,52 @@ static const struct phy_ops ops = { .owner = THIS_MODULE, }; +#define SERDES_NUM_MUX_COMBINATIONS 16 + +#define LICLK 0 +#define EXT_REFCLK 1 +#define RICLK 2 + +static const int +serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = { + /* + * Each combination maps to one of + * "Figure 12-1986. SerDes Reference Clock Distribution" + * in TRM. + */ + /* Parent of CMU refclk, Left output, Right output + * either of EXT_REFCLK, LICLK, RICLK + */ + { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */ + { RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */ + { EXT_REFCLK, RICLK, LICLK }, /* 0010 */ + { RICLK, RICLK, EXT_REFCLK }, /* 0011 */ + { LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */ + { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */ + { LICLK, RICLK, LICLK }, /* 0110 */ + { EXT_REFCLK, RICLK, LICLK }, /* 0111 */ + { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */ + { RICLK, EXT_REFCLK, LICLK }, /* 1001 */ + { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */ + { RICLK, RICLK, EXT_REFCLK }, /* 1011 */ + { LICLK, EXT_REFCLK, LICLK }, /* 1100 */ + { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */ + { LICLK, RICLK, EXT_REFCLK }, /* 1110 */ + { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */ +}; + static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw) { struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); - unsigned int num_parents = clk_hw_get_num_parents(hw); struct regmap *regmap = mux->regmap; unsigned int reg = mux->reg; unsigned int val; - int i; regmap_read(regmap, reg, &val); - val >>= mux->shift; - val &= mux->mask; - - for (i = 0; i < num_parents; i++) - if (mux->table[i] == val) - return i; - - /* - * No parent? This should never happen! - * Verify if we set a valid parent in serdes_am654_clk_register() - */ - WARN(1, "Failed to find the parent of %s clock\n", hw->init->name); + val &= AM654_SERDES_CTRL_CLKSEL_MASK; + val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT; - /* Make the parent lookup to fail */ - return num_parents; + return serdes_am654_mux_table[val][mux->clk_id]; } static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index) @@ -301,16 +323,52 @@ static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index) struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); struct regmap *regmap = mux->regmap; unsigned int reg = mux->reg; - int val; + int clk_id = mux->clk_id; + int parents[SERDES_NUM_CLOCKS]; + const int *p; + u32 val; + int found, i; int ret; - val = mux->table[index]; + /* get existing setting */ + regmap_read(regmap, reg, &val); + val &= AM654_SERDES_CTRL_CLKSEL_MASK; + val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT; + + for (i = 0; i < SERDES_NUM_CLOCKS; i++) + parents[i] = serdes_am654_mux_table[val][i]; + + /* change parent of this clock. others left intact */ + parents[clk_id] = index; + + /* Find the match */ + for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) { + p = serdes_am654_mux_table[val]; + found = 1; + for (i = 0; i < SERDES_NUM_CLOCKS; i++) { + if (parents[i] != p[i]) { + found = 0; + break; + } + } + + if (found) + break; + } - if (val == -1) + if (!found) { + /* + * This can never happen, unless we missed + * a valid combination in serdes_am654_mux_table. + */ + WARN(1, "Failed to find the parent of %s clock\n", + hw->init->name); return -EINVAL; + } - val <<= mux->shift; - ret = regmap_update_bits(regmap, reg, mux->mask << mux->shift, val); + val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT; + ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK, + val); return ret; } @@ -320,21 +378,6 @@ static const struct clk_ops serdes_am654_clk_mux_ops = { .get_parent = serdes_am654_clk_mux_get_parent, }; -static int mux_table[SERDES_NUM_CLOCKS][3] = { - /* - * The entries represent values for selecting between - * {left input, external reference clock, right input} - * Only one of Left Output or Right Output should be used since - * both left and right output clock uses the same bits and modifying - * one clock will impact the other. - */ - { BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */ - { -1, BIT(3), BIT(1) }, /* Mux of Left Output */ - { BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */ -}; - -static int mux_mask[SERDES_NUM_CLOCKS] = { 0x5, 0xa, 0xa }; - static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, const char *clock_name, int clock_num) { @@ -394,20 +437,11 @@ static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, init->num_parents = num_parents; init->name = clock_name; - mux->table = mux_table[clock_num]; mux->regmap = regmap; mux->reg = reg; - mux->shift = 4; - mux->mask = mux_mask[clock_num]; + mux->clk_id = clock_num; mux->hw.init = init; - /* - * setup a sane default so get_parent() call evaluates - * to a valid parent. Index 1 is the safest choice as - * the default as it is valid value for all of serdes's - * output clocks. - */ - serdes_am654_clk_mux_set_parent(&mux->hw, 1); clk = devm_clk_register(dev, &mux->hw); if (IS_ERR(clk)) return PTR_ERR(clk);