From patchwork Tue Dec 6 19:20:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Stockhausen X-Patchwork-Id: 632962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50F9AC352A1 for ; Tue, 6 Dec 2022 19:20:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229703AbiLFTUp (ORCPT ); Tue, 6 Dec 2022 14:20:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbiLFTUo (ORCPT ); Tue, 6 Dec 2022 14:20:44 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92DA83FB9B for ; Tue, 6 Dec 2022 11:20:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.de; s=s31663417; t=1670354440; bh=cIeb2Skz/eLJWJKhaChZ1ch4MjYnY8RqfezZZNFM214=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=tOBHQxyqdkU67rkmyVoHI9FP3V3Oap453tY7wQLr7mo3gCniiM9rPG4qPQrt1m9+8 zoh42fhx7V+ZRgPD2ltVZ9eR+BkwxRQyHvOG+2ksC4uiVck66eDXfmJZ/vlFvUstmG mVgrXZaaZj7QCUqk17yfZzRhJiik6FtSW82KfSp+RVn5MVQbvOPjQ2CXnRN6HC+5OT 6Vjvjknn4tcpIljhCTwSgH19R8meKn74xk6xQGmXvdgOL+USNlNAolZ6D1k4uMJK+H eG2N2zzQRYlPnaVERfGDU+2NyY1O387UrMPwg7PPI+E2Xd/YEifn3Om2w3UmAweNbu eEJ9kWGMlHetg== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from fedora.willemsstb.de ([94.31.87.22]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1MGz1V-1pF1hr2yHr-00E7yw; Tue, 06 Dec 2022 20:20:40 +0100 From: Markus Stockhausen To: linux-crypto@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH v2 1/6] crypto/realtek: header definitions Date: Tue, 6 Dec 2022 20:20:32 +0100 Message-Id: <20221206192037.608808-2-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206192037.608808-1-markus.stockhausen@gmx.de> References: <20221206192037.608808-1-markus.stockhausen@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:kfoYz9HCN3eVEx3Fyv/+SQyAgsbhdkJzocJMYKGNoJamUIpUBTJ Mc4THQ4s3+DKPx4A5dGNAxR7sK8dkT8wrjk3auTxJZN9CwZ7hP/LLFcnGmPF3z151kBgMJm 0r8GVow9E/99SeE/gQcXzofib0bXVuGKBSadX/a/hOE75nPGq+6zcXwE6bvBaHxO8sf5vE+ q4NyBzZsbuetcw+5iH6kA== UI-OutboundReport: notjunk:1;M01:P0:SYM8JzqEB5Y=;cI4SuSSvEW+Yhkf7onFlktuUsR1 5h+3WqtGU5vqLJU6U9E7WAjoHIF9UINFsB3pgnu/mJZLo+w5aNQ9h2hA8S++rJRlB4tghL1Tr WwHIoAhvMWsQMprTwu9vO86VxgBWzxMZZpToNFHsPWq3V2b1nVrCQWpxuSC0MT3M7lZYnufel g6fA0kE7G6PAMlZ/SLEdenf0qo3WeBF27Zk+4Xzmi7q85o+qKxA7l1AHmEPghvkSKcRJ4JwyJ hlko9ns7pkFgH72Xlf1VYcvakw6c2bRPAnWSxA/QfeQXh9+UmSr/9aijVqG7VFtwbzH6LoDab pzrVyl0mGbBKbZBe93LSINlKoGi/pKjUO7bAIxoVbcKUUi9vPltXK7VLqntgJgvs+D2ZQ7n37 ncchv8EMQaMnW5qx+KOeCIxvss6VP1WF7rwkzFsXOkUBtsuswP8kNW9SRyz/6NDdmi5gpUmzM H+isUV4qoMdmCiDksOCPEE5cafN/G4NE9Nh1Nmhzzx0lF2n7R+MlMLfXzBkkVrQ3uyoM40vAA oxezhYg1EPsciKO0i0ihofK/T5I52qGA20JyJmqZuBc6lRYgvF55jmDreQUeAHya/qk+LjU8J /uhRqGKhl6kgJiFpGESSStONNOG93+FHns2IY1D7vY2HYWcOY4D0zrQfOZ8Q2b5u5Lik0ujuz yFyANG9zd/jiD90iu4u3esxEJxqRegd3BzMvEgBxjFQVGX1r4yiz6VmGog7m0BI9y1k9Fjhju FiLAWjqv1nnaDZ79xvnq+jc05V+ZR8J0RVOhk0cn24C/GJD289cJ/BbmKS876EAj8dXYqMf6V FNhqmMowYjc7qmASiiuizyAxBv0YnzSUnBrAsgSAXfCsyz/5Bh0eRn7WV2dmWeFO/BW+OnrsD P2ETHqMReWk3TeqGyUJHSE+/DwRhmR+jYO2eMiy3BT/5r+MnbElEWMn/6sTJifkAl3TJ34OT+ cc6KgHAOQPMEOuqo3qO98OlzXnA= Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add header definitions for new Realtek crypto device. Signed-off-by: Markus Stockhausen --- drivers/crypto/realtek/realtek_crypto.h | 325 ++++++++++++++++++++++++ 1 file changed, 325 insertions(+) create mode 100644 drivers/crypto/realtek/realtek_crypto.h -- 2.38.1 diff --git a/drivers/crypto/realtek/realtek_crypto.h b/drivers/crypto/realtek/realtek_crypto.h new file mode 100644 index 000000000000..35d9de5eca7a --- /dev/null +++ b/drivers/crypto/realtek/realtek_crypto.h @@ -0,0 +1,325 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Crypto acceleration support for Realtek crypto engine. Based on ideas from + * Rockchip & SafeXcel driver plus Realtek OpenWrt RTK. + * + * Copyright (c) 2022, Markus Stockhausen + */ + +#ifndef __REALTEK_CRYPTO_H__ +#define __REALTEK_CRYPTO_H__ + +#include +#include +#include +#include +#include +#include + +/* + * The four engine registers for instrumentation of the hardware. + */ +#define RTCR_REG_SRC 0x0 /* Source descriptor starting address */ +#define RTCR_REG_DST 0x4 /* Destination Descriptor starting address */ +#define RTCR_REG_CMD 0x8 /* Command/Status Register */ +#define RTCR_REG_CTR 0xC /* Control Register */ +/* + * Engine Command/Status Register. + */ +#define RTCR_CMD_SDUEIP BIT(15) /* Src desc unavail error interrupt pending */ +#define RTCR_CMD_SDLEIP BIT(14) /* Src desc length error interrupt pending */ +#define RTCR_CMD_DDUEIP BIT(13) /* Dst desc unavail error interrupt pending */ +#define RTCR_CMD_DDOKIP BIT(12) /* Dst dsec ok interrupt pending */ +#define RTCR_CMD_DABFIP BIT(11) /* Data address buffer interrupt pending */ +#define RTCR_CMD_POLL BIT(1) /* Descriptor polling. Set to kick engine */ +#define RTCR_CMD_SRST BIT(0) /* Software reset, write 1 to reset */ +/* + * Engine Control Register + */ +#define RTCR_CTR_SDUEIE BIT(15) /* Src desc unavail error interrupt enable */ +#define RTCR_CTR_SDLEIE BIT(14) /* Src desc length error interrupt enable */ +#define RTCR_CTR_DDUEIE BIT(13) /* Dst desc unavail error interrupt enable */ +#define RTCR_CTR_DDOKIE BIT(12) /* Dst desc ok interrupt enable */ +#define RTCR_CTR_DABFIE BIT(11) /* Data address buffer interrupt enable */ +#define RTCR_CTR_LBKM BIT(8) /* Loopback mode enable */ +#define RTCR_CTR_SAWB BIT(7) /* Source address write back = work inplace */ +#define RTCR_CTR_CKE BIT(6) /* Clock enable */ +#define RTCR_CTR_DDMMSK 0x38 /* Destination DMA max burst size mask */ +#define RTCR_CTR_DDM16 0x00 /* Destination DMA max burst size 16 bytes */ +#define RTCR_CTR_DDM32 0x08 /* Destination DMA max burst size 32 bytes */ +#define RTCR_CTR_DDM64 0x10 /* Destination DMA max burst size 64 bytes */ +#define RTCR_CTR_DDM128 0x18 /* Destination DMA max burst size 128 bytes */ +#define RTCR_CTR_SDMMSK 0x07 /* Source DMA max burst size mask */ +#define RTCR_CTR_SDM16 0x00 /* Source DMA max burst size 16 bytes */ +#define RTCR_CTR_SDM32 0x01 /* Source DMA max burst size 32 bytes */ +#define RTCR_CTR_SDM64 0x02 /* Source DMA max burst size 64 bytes */ +#define RTCR_CTR_SDM128 0x03 /* Source DMA max burst size 128 bytes */ + +/* + * Module settings and constants. Some of the limiter values have been chosen + * based on testing (e.g. ring sizes). Others are based on real hardware + * limits (e.g. scatter, request size, hash size). + */ +#define RTCR_SRC_RING_SIZE 64 +#define RTCR_DST_RING_SIZE 16 +#define RTCR_BUF_RING_SIZE 32768 +#define RTCR_MAX_REQ_SIZE 8192 +#define RTCR_MAX_SG 8 +#define RTCR_MAX_SG_AHASH (RTCR_MAX_SG - 1) +#define RTCR_MAX_SG_SKCIPHER (RTCR_MAX_SG - 3) +#define RTCR_HASH_VECTOR_SIZE SHA1_DIGEST_SIZE + +#define RTCR_ALG_AHASH 0 +#define RTCR_ALG_SKCIPHER 1 + +#define RTCR_HASH_UPDATE BIT(0) +#define RTCR_HASH_FINAL BIT(1) +#define RTCR_HASH_BUF_SIZE SHA1_BLOCK_SIZE +#define RTCR_HASH_PAD_SIZE ((SHA1_BLOCK_SIZE + 8) / sizeof(u64)) + +#define RTCR_REQ_SG_MASK 0xff +#define RTCR_REQ_MD5 BIT(8) +#define RTCR_REQ_SHA1 BIT(9) +#define RTCR_REQ_FB_ACT BIT(10) +#define RTCR_REQ_FB_RDY BIT(11) + +/* + * Crypto ring source data descripter. This data is fed into the engine. It + * takes all information about the input data and the type of cypher/hash + * algorithm that we want to apply. Each request consists of several source + * descriptors. + */ +struct rtcr_src_desc { + u32 opmode; + u32 len; + u32 dummy; + phys_addr_t paddr; +}; + +#define RTCR_SRC_DESC_SIZE (sizeof(struct rtcr_src_desc)) +/* + * Owner: This flag identifies the owner of the block. When we send the + * descripter to the ring set this flag to 1. Once the crypto engine has + * finished processing this will be reset to 0. + */ +#define RTCR_SRC_OP_OWN_ASIC BIT(31) +#define RTCR_SRC_OP_OWN_CPU 0 +/* + * End of ring: Setting this flag to 1 tells the crypto engine that this is + * the last descriptor of the whole ring (not the request). If set the engine + * will not increase the processing pointer afterwards but will jump back to + * the first descriptor address it was initialized with. + */ +#define RTCR_SRC_OP_EOR BIT(30) +#define RTCR_SRC_OP_CALC_EOR(idx) ((idx == RTCR_SRC_RING_SIZE - 1) ? \ + RTCR_SRC_OP_EOR : 0) +/* + * First segment: If set to 1 this is the first descriptor of a request. All + * descriptors that follow will have this flag set to 0 belong to the same + * request. + */ +#define RTCR_SRC_OP_FS BIT(29) +/* + * Mode select: Set to 00b for crypto only, set to 01b for hash only, 10b for + * hash then crypto or 11b for crypto then hash. + */ +#define RTCR_SRC_OP_MS_CRYPTO 0 +#define RTCR_SRC_OP_MS_HASH BIT(26) +#define RTCR_SRC_OP_MS_HASH_CRYPTO BIT(27) +#define RTCR_SRC_OP_MS_CRYPTO_HASH GENMASK(27, 26) +/* + * Key application management: Only relevant for cipher (AES/3DES/DES) mode. If + * using AES or DES it has to be set to 0 (000b) for decryption and 7 (111b) for + * encryption. For 3DES it has to be set to 2 (010b = decrypt, encrypt, decrypt) + * for decryption and 5 (101b = encrypt, decrypt, encrypt) for encryption. + */ +#define RTCR_SRC_OP_KAM_DEC 0 +#define RTCR_SRC_OP_KAM_ENC GENMASK(25, 23) +#define RTCR_SRC_OP_KAM_3DES_DEC BIT(24) +#define RTCR_SRC_OP_KAM_3DES_ENC (BIT(23) | BIT(25)) +/* + * AES/3DES/DES mode & key length: Upper two bits for AES mode. If set to values + * other than 0 we want to encrypt/decrypt with AES. The values are 01b for 128 + * bit key length, 10b for 192 bit key length and 11b for 256 bit key length. + * If AES is disabled (upper two bits 00b) then the lowest bit determines if we + * want to use 3DES (1) or DES (0). + */ +#define RTCR_SRC_OP_CIPHER_FROM_KEY(k) ((k - 8) << 18) +#define RTCR_SRC_OP_CIPHER_AES_128 BIT(21) +#define RTCR_SRC_OP_CIPHER_AES_192 BIT(22) +#define RTCR_SRC_OP_CIPHER_AES_256 GENMASK(22, 21) +#define RTCR_SRC_OP_CIPHER_3DES BIT(20) +#define RTCR_SRC_OP_CIPHER_DES 0 +#define RTCR_SRC_OP_CIPHER_MASK GENMASK(22, 20) +/* + * Cipher block mode: Determines the block mode of a cipher request. Set to 00b + * for ECB, 01b for CTR and 10b for CTR. + */ +#define RTCR_SRC_OP_CRYPT_ECB 0 +#define RTCR_SRC_OP_CRYPT_CTR BIT(18) +#define RTCR_SRC_OP_CRYPT_CBC BIT(19) +/* + * Hash mode: Set to 1 for MD5 or 0 for SHA1 calculation. + */ +#define RTCR_SRC_OP_HASH_MD5 BIT(16) +#define RTCR_SRC_OP_HASH_SHA1 0 + +#define RTCR_SRC_OP_DUMMY_LEN 128 + +/* + * Crypto ring destination data descriptor. Data inside will be fed to the + * engine and if we process a hash request we get the resulting hash from here. + * Each request consists of exactly one destination descriptor. + */ +struct rtcr_dst_desc { + u32 opmode; + phys_addr_t paddr; + u32 dummy; + u32 vector[RTCR_HASH_VECTOR_SIZE / sizeof(u32)]; +}; + +#define RTCR_DST_DESC_SIZE (sizeof(struct rtcr_dst_desc)) +/* + * Owner: This flag identifies the owner of the block. When we send the + * descripter to the ring set this flag to 1. Once the crypto engine has + * finished processing this will be reset to 0. + */ +#define RTCR_DST_OP_OWN_ASIC BIT(31) +#define RTCR_DST_OP_OWN_CPU 0 +/* + * End of ring: Setting this flag to 1 tells the crypto engine that this is + * the last descriptor of the whole ring (not the request). If set the engine + * will not increase the processing pointer afterwards but will jump back to + * the first descriptor address it was initialized with. + */ +#define RTCR_DST_OP_EOR BIT(30) +#define RTCR_DST_OP_CALC_EOR(idx) ((idx == RTCR_DST_RING_SIZE - 1) ? \ + RTCR_DST_OP_EOR : 0) + +/* + * Writeback descriptor. This descriptor maintains additional data per request + * about writebac. E.g. the hash result or a cipher that was written to the + * internal buffer only. Remember the post processing information here. + */ +struct rtcr_wbk_desc { + void *dst; + void *src; + int off; + int len; +}; +/* + * To keep the size of the descriptor a power of 2 (cache line aligned) the + * length field can denote special writeback requests that need another type of + * postprocessing. + */ +#define RTCR_WB_LEN_DONE (0) +#define RTCR_WB_LEN_HASH (-1) +#define RTCR_WB_LEN_SG_DIRECT (-2) + +struct rtcr_crypto_dev { + char buf_ring[RTCR_BUF_RING_SIZE]; + struct rtcr_src_desc src_ring[RTCR_SRC_RING_SIZE]; + struct rtcr_dst_desc dst_ring[RTCR_DST_RING_SIZE]; + struct rtcr_wbk_desc wbk_ring[RTCR_DST_RING_SIZE]; + + /* modified under ring lock */ + int cpu_src_idx; + int cpu_dst_idx; + int cpu_buf_idx; + + /* modified in (serialized) tasklet */ + int pp_src_idx; + int pp_dst_idx; + int pp_buf_idx; + + /* modified under asic lock */ + int asic_dst_idx; + int asic_src_idx; + bool busy; + + int irq; + spinlock_t asiclock; + spinlock_t ringlock; + struct tasklet_struct done_task; + wait_queue_head_t done_queue; + + void __iomem *base; + + struct platform_device *pdev; + struct device *dev; +}; + +struct rtcr_alg_template { + struct rtcr_crypto_dev *cdev; + int type; + int opmode; + union { + struct skcipher_alg skcipher; + struct ahash_alg ahash; + } alg; +}; + +struct rtcr_ahash_ctx { + struct rtcr_crypto_dev *cdev; + struct crypto_ahash *fback; + int opmode; +}; + +struct rtcr_ahash_req { + int state; + /* Data from here is lost if fallback switch happens */ + u32 vector[RTCR_HASH_VECTOR_SIZE]; + u64 totallen; + char buf[RTCR_HASH_BUF_SIZE]; + int buflen; +}; + +union rtcr_fallback_state { + struct md5_state md5; + struct sha1_state sha1; +}; + +struct rtcr_skcipher_ctx { + struct rtcr_crypto_dev *cdev; + int opmode; + int keylen; + u32 key_enc[AES_KEYSIZE_256 / sizeof(u32)]; + u32 key_dec[AES_KEYSIZE_256 / sizeof(u32)]; +}; + +extern struct rtcr_alg_template rtcr_ahash_md5; +extern struct rtcr_alg_template rtcr_ahash_sha1; +extern struct rtcr_alg_template rtcr_skcipher_ecb_aes; +extern struct rtcr_alg_template rtcr_skcipher_cbc_aes; +extern struct rtcr_alg_template rtcr_skcipher_ctr_aes; + +extern void rtcr_lock_ring(struct rtcr_crypto_dev *cdev); +extern void rtcr_unlock_ring(struct rtcr_crypto_dev *cdev); + +extern int rtcr_alloc_ring(struct rtcr_crypto_dev *cdev, int srclen, + int *srcidx, int *dstidx, int buflen, char **buf); +extern void rtcr_add_src_ahash_to_ring(struct rtcr_crypto_dev *cdev, int idx, + int opmode, int totallen); +extern void rtcr_add_src_pad_to_ring(struct rtcr_crypto_dev *cdev, + int idx, int len); +extern void rtcr_add_src_skcipher_to_ring(struct rtcr_crypto_dev *cdev, int idx, + int opmode, int totallen, + struct rtcr_skcipher_ctx *sctx); +extern void rtcr_add_src_to_ring(struct rtcr_crypto_dev *cdev, int idx, + void *vaddr, int blocklen, int totallen); +extern void rtcr_add_wbk_to_ring(struct rtcr_crypto_dev *cdev, int idx, + void *dst, int off); +extern void rtcr_add_dst_to_ring(struct rtcr_crypto_dev *cdev, int idx, + void *reqdst, int reqlen, void *wbkdst, + int wbkoff); + +extern void rtcr_kick_engine(struct rtcr_crypto_dev *cdev); + +extern void rtcr_prepare_request(struct rtcr_crypto_dev *cdev); +extern void rtcr_finish_request(struct rtcr_crypto_dev *cdev, int opmode, + int totallen); +extern int rtcr_wait_for_request(struct rtcr_crypto_dev *cdev, int idx); + +extern inline int rtcr_inc_src_idx(int idx, int cnt); +extern inline int rtcr_inc_dst_idx(int idx, int cnt); +#endif From patchwork Tue Dec 6 19:20:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Stockhausen X-Patchwork-Id: 631375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36618C4708C for ; Tue, 6 Dec 2022 19:20:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229660AbiLFTUq (ORCPT ); Tue, 6 Dec 2022 14:20:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229448AbiLFTUp (ORCPT ); Tue, 6 Dec 2022 14:20:45 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.15.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B74574198C for ; Tue, 6 Dec 2022 11:20:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.de; s=s31663417; t=1670354441; bh=y7g7B/KWTPQcBv+WjCGh4gABH0vr/KSnW5YSaahjmjo=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=tC+SYxsL6ZpqNotLVQMVx7vRrPxTfjn9E7brDsn8NRo4CzZzmHAYhRNPOFj9liECs gefcJQdXEiJE0kJo7Y+ESfs1cAqlC5zOEkRblrpSqQfYDVCg63/La956FPMYXd9ZxE QVjbMvJB5NhHCE9I8uJMdhKqyTHo5Od7OV8vVxB2nDnYQUqegR2sumZ8oXK1CUOVwe eULuggYEvBVo8TOBvPqTsnnbBcW22GWlM/cyWSOJm+iX2F7u/+ezxPzzbyqbDSivCQ Fa8C5RZGPvGQTPQXXDQ7pJF2O/n6l1HNQJQMSyfqVw4jbfwiuqo2rzUF8XvZqJf+mz tQcke7vxzEb+A== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from fedora.willemsstb.de ([94.31.87.22]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1MJE6L-1pHHpT3i71-00KeL0; Tue, 06 Dec 2022 20:20:40 +0100 From: Markus Stockhausen To: linux-crypto@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH v2 2/6] crypto/realtek: core functions Date: Tue, 6 Dec 2022 20:20:33 +0100 Message-Id: <20221206192037.608808-3-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206192037.608808-1-markus.stockhausen@gmx.de> References: <20221206192037.608808-1-markus.stockhausen@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:RXPswZiMnvU4shUPnbo1M1gmw3kaZYhG0atHbhmiMNjlB7BM/KK JWYyz+XQxw1xG4+Qod26aHWIjWblqqOuMRsz4SIyDoJYLZG4bzE9wAOj+zaJY1GKwUiWYkB 102n8b5gXfEwXEm23BAJCeaD/BsNvTkcOteg5suB3hinKG+Y+sQwaXAYiKGiALLzCh26Vgr FswfwLxFLYNFfn8jl+TdQ== UI-OutboundReport: notjunk:1;M01:P0:9OzpSwIoxQA=;j+6dGfUkHghDfvsyp4WDt6pKw65 Mz1Ec0hM3ncdUJD/bGKrZP4t7Aiy4ewlj2AFtkF6D34EeSI1UU7HZdjyFp+rLLZmfhP/xlhhY kx4zIdFQKBYACV97zQhvfayTaDWnbwrygnq/9hEg+X2msPg/rhNQo2I9QzM37kUj2SZECcYrN w/fl/hKa4m0Qd+PXABlEf0D+lqMDNInI59S+CAUVhDbipYG4xUnMmfd7c+Hzo7x4rsG1j1N/G X6+gSn3PdXpreRRuTvHPmxvfHAaJ7ApW30hTRDPs3ICbIeHDyagbgl2N2Jh2U5UyPtUXreAtO nEKkZu2T+YkC3/wrPe8SO08yOzyuhPtshbYcLSLCBOZx+jl9g79MW6jKF/hDbN+HW06pCaT2n OZZ4dYoHgeLUd3W6TVzY+4nuMZ/dAm3Qf0kj7JNWO/B4iT6IU224sSnaTyK/t8nQiE2eaa4c2 skLhk39VlxUbUOznogPL0FzuLhfarGzvM0M4et6EjsZsMUtJwd7/otBvXPC92K15Wde2DTovS 58RIEFRAD7b1Ja+QkGjoveCTuoFSm9awwldJCbYTzMRfU8YscEvTAEpEVOL1SsaTlLwm0P0lP O6S/k2jHh1+nRxGP6W0N5prFG3DbfvxJE0v2qCC2cEsfr47f+5LDvkR+b7tJStOeb2VvIdyE5 RLfX9gsCWPOUIr34Vrrw6wJFROVOQPdeO7YqY3BDnhJ2/ztqpIJtL+tc0lI5d8dVWjWwETuhY OGKNk0MqE7iRogDLk58Z/YT2dZMGAcuOABbWaQVi56pIuXrr9ywqzG+7vU7/hfDWT82edmjle tY/dM+C+sEXvptWrNLTwRriirZR24U+qKj5/cQpQ3trZ7H8FFaROayuNwBExduGoksNxmC6MD ss8zWuwI9ZEyn7K/O4eRD+T2meDoUamwrU3if/b06FmArjh8m1c/4HRvju4wSPRlHo+HQcBVV o9JVdw== Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add core functions for new Realtek crypto device. Signed-off-by: Markus Stockhausen --- drivers/crypto/realtek/realtek_crypto.c | 472 ++++++++++++++++++++++++ 1 file changed, 472 insertions(+) create mode 100644 drivers/crypto/realtek/realtek_crypto.c -- 2.38.1 diff --git a/drivers/crypto/realtek/realtek_crypto.c b/drivers/crypto/realtek/realtek_crypto.c new file mode 100644 index 000000000000..f22d117fd3c6 --- /dev/null +++ b/drivers/crypto/realtek/realtek_crypto.c @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Crypto acceleration support for Realtek crypto engine. Based on ideas from + * Rockchip & SafeXcel driver plus Realtek OpenWrt RTK. + * + * Copyright (c) 2022, Markus Stockhausen + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "realtek_crypto.h" + +inline int rtcr_inc_src_idx(int idx, int cnt) +{ + return (idx + cnt) & (RTCR_SRC_RING_SIZE - 1); +} + +inline int rtcr_inc_dst_idx(int idx, int cnt) +{ + return (idx + cnt) & (RTCR_DST_RING_SIZE - 1); +} + +inline int rtcr_inc_buf_idx(int idx, int cnt) +{ + return (idx + cnt) & (RTCR_BUF_RING_SIZE - 1); +} + +inline int rtcr_space_plus_pad(int len) +{ + return (len + 31) & ~31; +} + +int rtcr_alloc_ring(struct rtcr_crypto_dev *cdev, int srclen, int *srcidx, + int *dstidx, int buflen, char **buf) +{ + int srcfree, dstfree, buffree, bufidx; + int srcalloc = (srclen + 1) & ~1, bufalloc = 0; + int ret = -ENOSPC; + + spin_lock(&cdev->ringlock); + + bufidx = cdev->cpu_buf_idx; + if (buflen > 0) { + bufalloc = rtcr_space_plus_pad(buflen); + if (bufidx + bufalloc > RTCR_BUF_RING_SIZE) { + if (unlikely(cdev->cpu_buf_idx > bufidx)) { + dev_err(cdev->dev, "buffer ring full\n"); + goto err_nospace; + } + /* end of buffer is free but too small, skip it */ + bufidx = 0; + } + } + + srcfree = rtcr_inc_src_idx(cdev->pp_src_idx - cdev->cpu_src_idx, -1); + dstfree = rtcr_inc_dst_idx(cdev->pp_dst_idx - cdev->cpu_dst_idx, -1); + buffree = rtcr_inc_buf_idx(cdev->pp_buf_idx - bufidx, -1); + + if (unlikely(srcfree < srcalloc)) { + dev_err(cdev->dev, "source ring full\n"); + goto err_nospace; + } + if (unlikely(dstfree < 1)) { + dev_err(cdev->dev, "destination ring full\n"); + goto err_nospace; + } + if (unlikely(buffree < bufalloc)) { + dev_err(cdev->dev, "buffer ring full\n"); + goto err_nospace; + } + + *srcidx = cdev->cpu_src_idx; + cdev->cpu_src_idx = rtcr_inc_src_idx(cdev->cpu_src_idx, srcalloc); + + *dstidx = cdev->cpu_dst_idx; + cdev->cpu_dst_idx = rtcr_inc_dst_idx(cdev->cpu_dst_idx, 1); + + ret = 0; + cdev->wbk_ring[*dstidx].len = buflen; + if (buflen > 0) { + *buf = &cdev->buf_ring[bufidx]; + cdev->wbk_ring[*dstidx].src = *buf; + cdev->cpu_buf_idx = rtcr_inc_buf_idx(bufidx, bufalloc); + } + +err_nospace: + spin_unlock(&cdev->ringlock); + + return ret; +} + +static inline void rtcr_ack_irq(struct rtcr_crypto_dev *cdev) +{ + int v = ioread32(cdev->base + RTCR_REG_CMD); + + if (unlikely((v != RTCR_CMD_DDOKIP) && v)) + dev_err(cdev->dev, "unexpected IRQ result 0x%08x\n", v); + v = RTCR_CMD_SDUEIP | RTCR_CMD_SDLEIP | RTCR_CMD_DDUEIP | + RTCR_CMD_DDOKIP | RTCR_CMD_DABFIP; + + iowrite32(v, cdev->base + RTCR_REG_CMD); +} + +static void rtcr_done_task(unsigned long data) +{ + struct rtcr_crypto_dev *cdev = (struct rtcr_crypto_dev *)data; + int stop_src_idx, stop_dst_idx, idx, len; + struct scatterlist *sg; + unsigned long flags; + + spin_lock_irqsave(&cdev->asiclock, flags); + stop_src_idx = cdev->asic_src_idx; + stop_dst_idx = cdev->asic_dst_idx; + spin_unlock_irqrestore(&cdev->asiclock, flags); + + idx = cdev->pp_dst_idx; + + while (idx != stop_dst_idx) { + len = cdev->wbk_ring[idx].len; + switch (len) { + case RTCR_WB_LEN_SG_DIRECT: + /* already written to the destination by the engine */ + break; + case RTCR_WB_LEN_HASH: + /* write back hash from destination ring */ + memcpy(cdev->wbk_ring[idx].dst, + cdev->dst_ring[idx].vector, + RTCR_HASH_VECTOR_SIZE); + break; + default: + /* write back data from buffer */ + sg = (struct scatterlist *)cdev->wbk_ring[idx].dst; + sg_pcopy_from_buffer(sg, sg_nents(sg), + cdev->wbk_ring[idx].src, + len, cdev->wbk_ring[idx].off); + len = rtcr_space_plus_pad(len); + cdev->pp_buf_idx = ((char *)cdev->wbk_ring[idx].src - cdev->buf_ring) + len; + } + + cdev->wbk_ring[idx].len = RTCR_WB_LEN_DONE; + idx = rtcr_inc_dst_idx(idx, 1); + } + + wake_up_all(&cdev->done_queue); + cdev->pp_src_idx = stop_src_idx; + cdev->pp_dst_idx = stop_dst_idx; +} + +static irqreturn_t rtcr_handle_irq(int irq, void *dev_id) +{ + struct rtcr_crypto_dev *cdev = dev_id; + u32 p; + + spin_lock(&cdev->asiclock); + + rtcr_ack_irq(cdev); + cdev->busy = false; + + p = (u32)phys_to_virt((u32)ioread32(cdev->base + RTCR_REG_SRC)); + cdev->asic_src_idx = (p - (u32)cdev->src_ring) / RTCR_SRC_DESC_SIZE; + + p = (u32)phys_to_virt((u32)ioread32(cdev->base + RTCR_REG_DST)); + cdev->asic_dst_idx = (p - (u32)cdev->dst_ring) / RTCR_DST_DESC_SIZE; + + tasklet_schedule(&cdev->done_task); + spin_unlock(&cdev->asiclock); + + return IRQ_HANDLED; +} + +void rtcr_add_src_ahash_to_ring(struct rtcr_crypto_dev *cdev, int idx, + int opmode, int totallen) +{ + struct rtcr_src_desc *src = &cdev->src_ring[idx]; + + src->len = totallen; + src->opmode = opmode | RTCR_SRC_OP_FS | + RTCR_SRC_OP_DUMMY_LEN | RTCR_SRC_OP_OWN_ASIC | + RTCR_SRC_OP_CALC_EOR(idx); + + dma_sync_single_for_device(cdev->dev, virt_to_phys(src), + RTCR_SRC_DESC_SIZE, + DMA_TO_DEVICE); +} + +void rtcr_add_src_skcipher_to_ring(struct rtcr_crypto_dev *cdev, int idx, + int opmode, int totallen, + struct rtcr_skcipher_ctx *sctx) +{ + struct rtcr_src_desc *src = &cdev->src_ring[idx]; + + src->len = totallen; + if (opmode & RTCR_SRC_OP_KAM_ENC) + src->paddr = virt_to_phys(sctx->key_enc); + else + src->paddr = virt_to_phys(sctx->key_dec); + + src->opmode = RTCR_SRC_OP_FS | RTCR_SRC_OP_OWN_ASIC | + RTCR_SRC_OP_MS_CRYPTO | RTCR_SRC_OP_CRYPT_ECB | + RTCR_SRC_OP_CALC_EOR(idx) | opmode | sctx->keylen; + + dma_sync_single_for_device(cdev->dev, virt_to_phys(src), + RTCR_SRC_DESC_SIZE, + DMA_TO_DEVICE); +} + +void rtcr_add_src_to_ring(struct rtcr_crypto_dev *cdev, int idx, void *vaddr, + int blocklen, int totallen) +{ + struct rtcr_src_desc *src = &cdev->src_ring[idx]; + + src->len = totallen; + src->paddr = virt_to_phys(vaddr); + src->opmode = RTCR_SRC_OP_OWN_ASIC | RTCR_SRC_OP_CALC_EOR(idx) | blocklen; + + dma_sync_single_for_device(cdev->dev, virt_to_phys(src), + RTCR_SRC_DESC_SIZE, + DMA_BIDIRECTIONAL); +} + +inline void rtcr_add_src_pad_to_ring(struct rtcr_crypto_dev *cdev, int idx, int len) +{ + /* align 16 byte source descriptors with 32 byte cache lines */ + if (!(idx & 1)) + rtcr_add_src_to_ring(cdev, idx + 1, NULL, 0, len); +} + +void rtcr_add_dst_to_ring(struct rtcr_crypto_dev *cdev, int idx, void *reqdst, + int reqlen, void *wbkdst, int wbkoff) +{ + struct rtcr_dst_desc *dst = &cdev->dst_ring[idx]; + struct rtcr_wbk_desc *wbk = &cdev->wbk_ring[idx]; + + dst->paddr = virt_to_phys(reqdst); + dst->opmode = RTCR_DST_OP_OWN_ASIC | RTCR_DST_OP_CALC_EOR(idx) | reqlen; + + wbk->dst = wbkdst; + wbk->off = wbkoff; + + dma_sync_single_for_device(cdev->dev, virt_to_phys(dst), + RTCR_DST_DESC_SIZE, + DMA_BIDIRECTIONAL); +} + +inline int rtcr_wait_for_request(struct rtcr_crypto_dev *cdev, int idx) +{ + int *len = &cdev->wbk_ring[idx].len; + + wait_event(cdev->done_queue, *len == RTCR_WB_LEN_DONE); + return 0; +} + +void rtcr_kick_engine(struct rtcr_crypto_dev *cdev) +{ + unsigned long flags; + + spin_lock_irqsave(&cdev->asiclock, flags); + + if (!cdev->busy) { + cdev->busy = true; + /* engine needs up to 5us to reset poll bit */ + iowrite32(RTCR_CMD_POLL, cdev->base + RTCR_REG_CMD); + } + + spin_unlock_irqrestore(&cdev->asiclock, flags); +} + +static struct rtcr_alg_template *rtcr_algs[] = { + &rtcr_ahash_md5, + &rtcr_ahash_sha1, + &rtcr_skcipher_ecb_aes, + &rtcr_skcipher_cbc_aes, + &rtcr_skcipher_ctr_aes, +}; + +static void rtcr_unregister_algorithms(int end) +{ + int i; + + for (i = 0; i < end; i++) { + if (rtcr_algs[i]->type == RTCR_ALG_SKCIPHER) + crypto_unregister_skcipher(&rtcr_algs[i]->alg.skcipher); + else + crypto_unregister_ahash(&rtcr_algs[i]->alg.ahash); + } +} + +static int rtcr_register_algorithms(struct rtcr_crypto_dev *cdev) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(rtcr_algs); i++) { + rtcr_algs[i]->cdev = cdev; + if (rtcr_algs[i]->type == RTCR_ALG_SKCIPHER) + ret = crypto_register_skcipher(&rtcr_algs[i]->alg.skcipher); + else { + rtcr_algs[i]->alg.ahash.halg.statesize = + max(sizeof(struct rtcr_ahash_req), + offsetof(struct rtcr_ahash_req, vector) + + sizeof(union rtcr_fallback_state)); + ret = crypto_register_ahash(&rtcr_algs[i]->alg.ahash); + } + if (ret) + goto err_cipher_algs; + } + + return 0; + +err_cipher_algs: + rtcr_unregister_algorithms(i); + + return ret; +} + +static void rtcr_init_engine(struct rtcr_crypto_dev *cdev) +{ + int v; + + v = ioread32(cdev->base + RTCR_REG_CMD); + v |= RTCR_CMD_SRST; + iowrite32(v, cdev->base + RTCR_REG_CMD); + + usleep_range(10000, 20000); + + iowrite32(RTCR_CTR_CKE | RTCR_CTR_SDM16 | RTCR_CTR_DDM16 | + RTCR_CTR_SDUEIE | RTCR_CTR_SDLEIE | RTCR_CTR_DDUEIE | + RTCR_CTR_DDOKIE | RTCR_CTR_DABFIE, cdev->base + RTCR_REG_CTR); + + rtcr_ack_irq(cdev); + usleep_range(10000, 20000); +} + +static void rtcr_exit_engine(struct rtcr_crypto_dev *cdev) +{ + iowrite32(0, cdev->base + RTCR_REG_CTR); +} + +static void rtcr_init_rings(struct rtcr_crypto_dev *cdev) +{ + phys_addr_t src = virt_to_phys(cdev->src_ring); + phys_addr_t dst = virt_to_phys(cdev->dst_ring); + + iowrite32(src, cdev->base + RTCR_REG_SRC); + iowrite32(dst, cdev->base + RTCR_REG_DST); + + cdev->asic_dst_idx = cdev->asic_src_idx = 0; + cdev->cpu_src_idx = cdev->cpu_dst_idx = cdev->cpu_buf_idx = 0; + cdev->pp_src_idx = cdev->pp_dst_idx = cdev->pp_buf_idx = 0; +} + +static int rtcr_crypto_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtcr_crypto_dev *cdev; + unsigned long flags = 0; + struct resource *res; + void __iomem *base; + int irq, ret; + +#ifdef CONFIG_MIPS + if ((cpu_dcache_line_size() != 16) && (cpu_dcache_line_size() != 32)) { + dev_err(dev, "cache line size not 16 or 32 bytes\n"); + ret = -EINVAL; + goto err_map; + } +#endif + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "no IO address given\n"); + ret = -ENODEV; + goto err_map; + } + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR_OR_NULL(base)) { + dev_err(dev, "failed to map IO address\n"); + ret = -EINVAL; + goto err_map; + } + + cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); + if (!cdev) { + dev_err(dev, "failed to allocate device memory\n"); + ret = -ENOMEM; + goto err_mem; + } + + irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (!irq) { + dev_err(dev, "failed to determine device interrupt\n"); + ret = -EINVAL; + goto err_of_irq; + } + + if (devm_request_irq(dev, irq, rtcr_handle_irq, flags, "realtek-crypto", cdev)) { + dev_err(dev, "failed to request device interrupt\n"); + ret = -ENXIO; + goto err_request_irq; + } + + platform_set_drvdata(pdev, cdev); + cdev->base = base; + cdev->dev = dev; + cdev->irq = irq; + cdev->pdev = pdev; + + dma_map_single(dev, (void *)empty_zero_page, PAGE_SIZE, DMA_TO_DEVICE); + + init_waitqueue_head(&cdev->done_queue); + tasklet_init(&cdev->done_task, rtcr_done_task, (unsigned long)cdev); + spin_lock_init(&cdev->ringlock); + spin_lock_init(&cdev->asiclock); + + /* Init engine first as it resets the ring pointers */ + rtcr_init_engine(cdev); + rtcr_init_rings(cdev); + rtcr_register_algorithms(cdev); + + dev_info(dev, "%d KB buffer, max %d requests of up to %d bytes\n", + RTCR_BUF_RING_SIZE / 1024, RTCR_DST_RING_SIZE, + RTCR_MAX_REQ_SIZE); + dev_info(dev, "ready for AES/SHA1/MD5 crypto acceleration\n"); + + return 0; + +err_request_irq: + irq_dispose_mapping(irq); +err_of_irq: + kfree(cdev); +err_mem: + iounmap(base); +err_map: + return ret; +} + +static int rtcr_crypto_remove(struct platform_device *pdev) +{ + struct rtcr_crypto_dev *cdev = platform_get_drvdata(pdev); + + rtcr_exit_engine(cdev); + rtcr_unregister_algorithms(ARRAY_SIZE(rtcr_algs)); + tasklet_kill(&cdev->done_task); + return 0; +} + +static const struct of_device_id rtcr_id_table[] = { + { .compatible = "realtek,realtek-crypto" }, + {} +}; +MODULE_DEVICE_TABLE(of, rtcr_id_table); + +static struct platform_driver rtcr_driver = { + .probe = rtcr_crypto_probe, + .remove = rtcr_crypto_remove, + .driver = { + .name = "realtek-crypto", + .of_match_table = rtcr_id_table, + }, +}; + +module_platform_driver(rtcr_driver); + +MODULE_AUTHOR("Markus Stockhausen "); +MODULE_DESCRIPTION("Support for Realtek's cryptographic engine"); +MODULE_LICENSE("GPL"); From patchwork Tue Dec 6 19:20:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Stockhausen X-Patchwork-Id: 632961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2041C47090 for ; Tue, 6 Dec 2022 19:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229537AbiLFTUr (ORCPT ); Tue, 6 Dec 2022 14:20:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229699AbiLFTUp (ORCPT ); Tue, 6 Dec 2022 14:20:45 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AAA140939 for ; Tue, 6 Dec 2022 11:20:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.de; s=s31663417; t=1670354441; bh=5IM/phMQ0TGMCBqH3/NVEG7XFvEwYXix6JL0+2qXL/A=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=DAbqa/6dsgu9MUw3ScLS6++NlCh/LfdL1g/mZZO3FFjz352BILZBzz+kHiV4W0Mj+ UkelZYCszCqRzFd0F2SqHXrsk6FukQuLmU19OzM4owRUadxe7SwSQJ+VwaiTRjzgkB DOG9Th4uz9cDxRKsuutnbMaKdbOqpNX7p8EOwAvGdHELvLzHLILjNYURLoZ3ZIXBDU XF+eoeOpnGLyN2HD+LM02PjJJt/VHIWqke5tiw0ICiWLcbXmU8ocRJWdLQzk0biDnd 0kh3sK1o0bCqCkLWNAdJb6MjhE/JeGdTKOR1V3ZHpf6vTF/R2qeP08odfZPQaA5BWq wxMAc92An6BVQ== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from fedora.willemsstb.de ([94.31.87.22]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1M9FnZ-1p55Xa0Hqx-006Ojq; Tue, 06 Dec 2022 20:20:41 +0100 From: Markus Stockhausen To: linux-crypto@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH v2 3/6] crypto/realtek: hash algorithms Date: Tue, 6 Dec 2022 20:20:34 +0100 Message-Id: <20221206192037.608808-4-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206192037.608808-1-markus.stockhausen@gmx.de> References: <20221206192037.608808-1-markus.stockhausen@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:yVElCvmIwG8Nei6jX1akYmDCxEo1HV4MbCtT7owu1+/MLF6SjL2 bdgpCQQfSYh2RxT+dXlxNlexX/aKObzPj5/NSso5U5JMaBk66hH35EGqxrGiVx2yEv7Y2T3 4THk+cNGzspaoB4pDrzx80gKgCbXF6Z3KCfBWfUlAVJhYzDxT/TYZ0HY0/y9XHIz+b7Waua AUOrQ/zheHsymyp+5LbMw== UI-OutboundReport: notjunk:1;M01:P0:pWjXkWn4u1w=;BrXf6UDJSBlRRo50IZSpZIWXtka /QeKZbRnXurW9EnPS+uSjP6hfb2naVByox+zAgZkBNY/1rssyz1O8OljHrhLYqY5GH8Rv0MuV EtgZ2x89WFmHLV3y//usmxFHCrxW8i64Ws/6JpVkYLmly7lAic84mp9yze5s6R/yfXUw0UrI4 qI7tmV144yFh54kiq/rUIg+mOGb72jB/JoswVMYfRymjKlKHf919kBEOilqraLQlIif4QywgI kxgGa+B5E6lbupkJHBfmFM/R3KOuA2yk8+wX1HV7CnhpDH2NSddCwErdTvAzhOxer8fFWSPlI qcm1nbtjlP7Z0rX0gb0gQXBcCggCuw8cv4s51DYqGIrYSt0uF7Mg1xr2MOLCq+0FW4C8jCjV0 uJt8pQoYQ7JopqdWSZIu9eIQ9P+ZDg6u+0A68slqxEuxlpha3fB52FvVoxRc3UNy4cjxlG3p2 P52C8We35o0ZdjodZpGdDqp8avI1DQyW3+cU9284cLcNmzs23E6F6qkW3scghtVqgSXMB5tZC UYnkSSd0ou7PWYm1GxAhTUbvlUuwtP9BbVucZW6b2TVDpfsSwtnVcGzC6OOHE4BYRYomDEoVu SvNZJiWcNCxH5EkjeauIpNEAuctE0J6JiT6di747aZLHvvlBdm/Rev558wyEx/H8T60Jetd/V JIoykBtXFShOhbDZMCFmtPYqSmawyEWhNUWFsSNDdSxvs+cTTdalvjl53tD4p2Au11zj0zjV8 c8AA3wFf0AQ6J6TZxshWzE7eeDeTQ89cB/+ac5tKXxJD6x5yScayqE6OyH1ikKUY+/w4aEBQo vk51x2Cj3tag0nncQh5TEZmFRtaZg3xJmRpKi5l1YvepkGz6ERAuKXuTUBwZZhj1qLreo4owf cuuSvPQqOgVLKD+YCOxQBoVcXtoYJhEsMQ4xfnGbox9xrt4j6Ln8VUfHnQ0+otVyfUGKv9FJU mDIZvQ== Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add md5/sha1 hash algorithms for new Realtek crypto device. Signed-off-by: Markus Stockhausen --- drivers/crypto/realtek/realtek_crypto_ahash.c | 407 ++++++++++++++++++ 1 file changed, 407 insertions(+) create mode 100644 drivers/crypto/realtek/realtek_crypto_ahash.c -- 2.38.1 diff --git a/drivers/crypto/realtek/realtek_crypto_ahash.c b/drivers/crypto/realtek/realtek_crypto_ahash.c new file mode 100644 index 000000000000..c8476719b3a4 --- /dev/null +++ b/drivers/crypto/realtek/realtek_crypto_ahash.c @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Crypto acceleration support for Realtek crypto engine. Based on ideas from + * Rockchip & SafeXcel driver plus Realtek OpenWrt RTK. + * + * Copyright (c) 2022, Markus Stockhausen + */ + +#include +#include +#include + +#include "realtek_crypto.h" + +static inline struct ahash_request *fallback_request_ctx(struct ahash_request *areq) +{ + char *p = (char *)ahash_request_ctx(areq); + + return (struct ahash_request *)(p + offsetof(struct rtcr_ahash_req, vector)); +} + +static inline void *fallback_export_state(void *export) +{ + char *p = (char *)export; + + return (void *)(p + offsetof(struct rtcr_ahash_req, vector)); +} + +static int rtcr_process_hash(struct ahash_request *areq, int opmode) +{ + unsigned int len, nextbuflen, datalen, padlen, reqlen; + struct rtcr_ahash_req *hreq = ahash_request_ctx(areq); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rtcr_ahash_ctx *hctx = crypto_ahash_ctx(tfm); + int sgcnt = hreq->state & RTCR_REQ_SG_MASK; + struct rtcr_crypto_dev *cdev = hctx->cdev; + struct scatterlist *sg = areq->src; + int idx, srcidx, dstidx, ret; + u64 pad[RTCR_HASH_PAD_SIZE]; + char *ppad; + + /* Quick checks if processing is really needed */ + if (unlikely(!areq->nbytes) && !(opmode & RTCR_HASH_FINAL)) + return 0; + + if (hreq->buflen + areq->nbytes < 64 && !(opmode & RTCR_HASH_FINAL)) { + hreq->buflen += sg_pcopy_to_buffer(areq->src, sg_nents(areq->src), + hreq->buf + hreq->buflen, + areq->nbytes, 0); + return 0; + } + + /* calculate required parts of the request */ + datalen = (opmode & RTCR_HASH_UPDATE) ? areq->nbytes : 0; + if (opmode & RTCR_HASH_FINAL) { + nextbuflen = 0; + padlen = 64 - ((hreq->buflen + datalen) & 63); + if (padlen < 9) + padlen += 64; + hreq->totallen += hreq->buflen + datalen; + + memset(pad, 0, sizeof(pad) - sizeof(u64)); + ppad = (char *)&pad[RTCR_HASH_PAD_SIZE] - padlen; + *ppad = 0x80; + pad[RTCR_HASH_PAD_SIZE - 1] = hreq->state & RTCR_REQ_MD5 ? + cpu_to_le64(hreq->totallen << 3) : + cpu_to_be64(hreq->totallen << 3); + } else { + nextbuflen = (hreq->buflen + datalen) & 63; + padlen = 0; + datalen -= nextbuflen; + hreq->totallen += hreq->buflen + datalen; + } + reqlen = hreq->buflen + datalen + padlen; + + /* Write back any uncommitted data to memory. */ + if (hreq->buflen) + dma_sync_single_for_device(cdev->dev, virt_to_phys(hreq->buf), + hreq->buflen, DMA_TO_DEVICE); + if (padlen) + dma_sync_single_for_device(cdev->dev, virt_to_phys(ppad), + padlen, DMA_TO_DEVICE); + if (datalen) + dma_map_sg(cdev->dev, sg, sgcnt, DMA_TO_DEVICE); + + /* Get free space in the ring */ + sgcnt = 1 + (hreq->buflen ? 1 : 0) + (datalen ? sgcnt : 0) + (padlen ? 1 : 0); + + ret = rtcr_alloc_ring(cdev, sgcnt, &srcidx, &dstidx, RTCR_WB_LEN_HASH, NULL); + if (ret) + return ret; + /* + * Feed input data into the rings. Start with destination ring and fill + * source ring afterwards. Ensure that the owner flag of the first source + * ring is the last that becomes visible to the engine. + */ + rtcr_add_dst_to_ring(cdev, dstidx, NULL, 0, hreq->vector, 0); + + idx = srcidx; + if (hreq->buflen) { + idx = rtcr_inc_src_idx(idx, 1); + rtcr_add_src_to_ring(cdev, idx, hreq->buf, hreq->buflen, reqlen); + } + + while (datalen) { + len = min(sg_dma_len(sg), datalen); + + idx = rtcr_inc_src_idx(idx, 1); + rtcr_add_src_to_ring(cdev, idx, sg_virt(sg), len, reqlen); + + datalen -= len; + if (datalen) + sg = sg_next(sg); + } + + if (padlen) { + idx = rtcr_inc_src_idx(idx, 1); + rtcr_add_src_to_ring(cdev, idx, ppad, padlen, reqlen); + } + + rtcr_add_src_pad_to_ring(cdev, idx, reqlen); + rtcr_add_src_ahash_to_ring(cdev, srcidx, hctx->opmode, reqlen); + + /* Off we go */ + rtcr_kick_engine(cdev); + if (rtcr_wait_for_request(cdev, dstidx)) + return -EINVAL; + + hreq->state |= RTCR_REQ_FB_ACT; + hreq->buflen = nextbuflen; + + if (nextbuflen) + sg_pcopy_to_buffer(sg, sg_nents(sg), hreq->buf, nextbuflen, len); + if (padlen) + memcpy(areq->result, hreq->vector, crypto_ahash_digestsize(tfm)); + + return 0; +} + +static void rtcr_check_request(struct ahash_request *areq, int opmode) +{ + struct rtcr_ahash_req *hreq = ahash_request_ctx(areq); + struct scatterlist *sg = areq->src; + int reqlen, sgcnt, sgmax; + + if (hreq->state & RTCR_REQ_FB_ACT) + return; + + if (reqlen > RTCR_MAX_REQ_SIZE) { + hreq->state |= RTCR_REQ_FB_ACT; + return; + } + + sgcnt = 0; + sgmax = RTCR_MAX_SG_AHASH - (hreq->buflen ? 1 : 0); + reqlen = areq->nbytes; + if (!(opmode & RTCR_HASH_FINAL)) { + reqlen -= (hreq->buflen + reqlen) & 63; + sgmax--; + } + + while (reqlen > 0) { + reqlen -= sg_dma_len(sg); + sgcnt++; + sg = sg_next(sg); + } + + if (sgcnt > sgmax) + hreq->state |= RTCR_REQ_FB_ACT; + else + hreq->state = (hreq->state & ~RTCR_REQ_SG_MASK) | sgcnt; +} + +static bool rtcr_check_fallback(struct ahash_request *areq) +{ + struct ahash_request *freq = fallback_request_ctx(areq); + struct rtcr_ahash_req *hreq = ahash_request_ctx(areq); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + struct rtcr_ahash_ctx *hctx = crypto_ahash_ctx(tfm); + union rtcr_fallback_state state; + + if (!(hreq->state & RTCR_REQ_FB_ACT)) + return false; + + if (!(hreq->state & RTCR_REQ_FB_RDY)) { + /* Convert state to generic fallback state */ + if (hreq->state & RTCR_REQ_MD5) { + memcpy(state.md5.hash, hreq->vector, MD5_DIGEST_SIZE); + if (hreq->totallen) + cpu_to_le32_array(state.md5.hash, 4); + memcpy(state.md5.block, hreq->buf, SHA1_BLOCK_SIZE); + state.md5.byte_count = hreq->totallen + (u64)hreq->buflen; + } else { + memcpy(state.sha1.state, hreq->vector, SHA1_DIGEST_SIZE); + memcpy(state.sha1.buffer, &hreq->buf, SHA1_BLOCK_SIZE); + state.sha1.count = hreq->totallen + (u64)hreq->buflen; + } + } + + ahash_request_set_tfm(freq, hctx->fback); + ahash_request_set_crypt(freq, areq->src, areq->result, areq->nbytes); + + if (!(hreq->state & RTCR_REQ_FB_RDY)) { + crypto_ahash_import(freq, &state); + hreq->state |= RTCR_REQ_FB_RDY; + } + + return true; +} + +static int rtcr_ahash_init(struct ahash_request *areq) +{ + struct rtcr_ahash_req *hreq = ahash_request_ctx(areq); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); + int ds = crypto_ahash_digestsize(tfm); + + memset(hreq, 0, sizeof(*hreq)); + + hreq->vector[0] = SHA1_H0; + hreq->vector[1] = SHA1_H1; + hreq->vector[2] = SHA1_H2; + hreq->vector[3] = SHA1_H3; + hreq->vector[4] = SHA1_H4; + + hreq->state |= (ds == MD5_DIGEST_SIZE) ? RTCR_REQ_MD5 : RTCR_REQ_SHA1; + + return 0; +} + +static int rtcr_ahash_update(struct ahash_request *areq) +{ + struct ahash_request *freq = fallback_request_ctx(areq); + + rtcr_check_request(areq, RTCR_HASH_UPDATE); + if (rtcr_check_fallback(areq)) + return crypto_ahash_update(freq); + return rtcr_process_hash(areq, RTCR_HASH_UPDATE); +} + +static int rtcr_ahash_final(struct ahash_request *areq) +{ + struct ahash_request *freq = fallback_request_ctx(areq); + + if (rtcr_check_fallback(areq)) + return crypto_ahash_final(freq); + + return rtcr_process_hash(areq, RTCR_HASH_FINAL); +} + +static int rtcr_ahash_finup(struct ahash_request *areq) +{ + struct ahash_request *freq = fallback_request_ctx(areq); + + rtcr_check_request(areq, RTCR_HASH_FINAL | RTCR_HASH_UPDATE); + if (rtcr_check_fallback(areq)) + return crypto_ahash_finup(freq); + + return rtcr_process_hash(areq, RTCR_HASH_FINAL | RTCR_HASH_UPDATE); +} + +static int rtcr_ahash_digest(struct ahash_request *areq) +{ + struct ahash_request *freq = fallback_request_ctx(areq); + int ret; + + ret = rtcr_ahash_init(areq); + if (ret) + return ret; + + rtcr_check_request(areq, RTCR_HASH_FINAL | RTCR_HASH_UPDATE); + if (rtcr_check_fallback(areq)) + return crypto_ahash_digest(freq); + + return rtcr_process_hash(areq, RTCR_HASH_FINAL | RTCR_HASH_UPDATE); +} + +static int rtcr_ahash_import(struct ahash_request *areq, const void *in) +{ + const void *fexp = (const void *)fallback_export_state((void *)in); + struct ahash_request *freq = fallback_request_ctx(areq); + struct rtcr_ahash_req *hreq = ahash_request_ctx(areq); + const struct rtcr_ahash_req *hexp = in; + + hreq->state = get_unaligned(&hexp->state); + if (hreq->state & RTCR_REQ_FB_ACT) + hreq->state |= RTCR_REQ_FB_RDY; + + if (rtcr_check_fallback(areq)) + return crypto_ahash_import(freq, fexp); + + memcpy(hreq, hexp, sizeof(struct rtcr_ahash_req)); + + return 0; +} + +static int rtcr_ahash_export(struct ahash_request *areq, void *out) +{ + struct ahash_request *freq = fallback_request_ctx(areq); + struct rtcr_ahash_req *hreq = ahash_request_ctx(areq); + void *fexp = fallback_export_state(out); + struct rtcr_ahash_req *hexp = out; + + if (rtcr_check_fallback(areq)) { + put_unaligned(hreq->state, &hexp->state); + return crypto_ahash_export(freq, fexp); + } + + memcpy(hexp, hreq, sizeof(struct rtcr_ahash_req)); + + return 0; +} + +static int rtcr_ahash_cra_init(struct crypto_tfm *tfm) +{ + struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); + struct rtcr_ahash_ctx *hctx = crypto_tfm_ctx(tfm); + struct rtcr_crypto_dev *cdev = hctx->cdev; + struct rtcr_alg_template *tmpl; + + tmpl = container_of(__crypto_ahash_alg(tfm->__crt_alg), + struct rtcr_alg_template, alg.ahash); + + hctx->cdev = tmpl->cdev; + hctx->opmode = tmpl->opmode; + hctx->fback = crypto_alloc_ahash(crypto_tfm_alg_name(tfm), 0, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); + + if (IS_ERR(hctx->fback)) { + dev_err(cdev->dev, "could not allocate fallback for %s\n", + crypto_tfm_alg_name(tfm)); + return PTR_ERR(hctx->fback); + } + + crypto_ahash_set_reqsize(ahash, max(sizeof(struct rtcr_ahash_req), + offsetof(struct rtcr_ahash_req, vector) + + sizeof(struct ahash_request) + + crypto_ahash_reqsize(hctx->fback))); + + return 0; +} + +static void rtcr_ahash_cra_exit(struct crypto_tfm *tfm) +{ + struct rtcr_ahash_ctx *hctx = crypto_tfm_ctx(tfm); + + crypto_free_ahash(hctx->fback); +} + +struct rtcr_alg_template rtcr_ahash_md5 = { + .type = RTCR_ALG_AHASH, + .opmode = RTCR_SRC_OP_MS_HASH | RTCR_SRC_OP_HASH_MD5, + .alg.ahash = { + .init = rtcr_ahash_init, + .update = rtcr_ahash_update, + .final = rtcr_ahash_final, + .finup = rtcr_ahash_finup, + .export = rtcr_ahash_export, + .import = rtcr_ahash_import, + .digest = rtcr_ahash_digest, + .halg = { + .digestsize = MD5_DIGEST_SIZE, + /* statesize calculated during initialization */ + .base = { + .cra_name = "md5", + .cra_driver_name = "realtek-md5", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SHA1_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct rtcr_ahash_ctx), + .cra_alignmask = 0, + .cra_init = rtcr_ahash_cra_init, + .cra_exit = rtcr_ahash_cra_exit, + .cra_module = THIS_MODULE, + } + } + } +}; + +struct rtcr_alg_template rtcr_ahash_sha1 = { + .type = RTCR_ALG_AHASH, + .opmode = RTCR_SRC_OP_MS_HASH | RTCR_SRC_OP_HASH_SHA1, + .alg.ahash = { + .init = rtcr_ahash_init, + .update = rtcr_ahash_update, + .final = rtcr_ahash_final, + .finup = rtcr_ahash_finup, + .export = rtcr_ahash_export, + .import = rtcr_ahash_import, + .digest = rtcr_ahash_digest, + .halg = { + .digestsize = SHA1_DIGEST_SIZE, + /* statesize calculated during initialization */ + .base = { + .cra_name = "sha1", + .cra_driver_name = "realtek-sha1", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize = SHA1_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct rtcr_ahash_ctx), + .cra_alignmask = 0, + .cra_init = rtcr_ahash_cra_init, + .cra_exit = rtcr_ahash_cra_exit, + .cra_module = THIS_MODULE, + } + } + } +}; From patchwork Tue Dec 6 19:20:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Stockhausen X-Patchwork-Id: 631376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0ACAC636F9 for ; Tue, 6 Dec 2022 19:20:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229448AbiLFTUr (ORCPT ); Tue, 6 Dec 2022 14:20:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229679AbiLFTUp (ORCPT ); Tue, 6 Dec 2022 14:20:45 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.15.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 116B540920 for ; Tue, 6 Dec 2022 11:20:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.de; s=s31663417; t=1670354441; bh=zVUHqCJ84GllTcJFCmSYFeaC4bAuLxzS3zDt/gzsgAY=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=Af1DqJ/oxx2k9gEhYSRb2/QnjoRDUZQkxvQlIqSGyB9ix1zr2DAHZF2XbzoCFA3fN bO0z8vjv5IT2IELiWQqMRHH+LeTy8wKBx4TmxELZJ2gh414huIXk2XkuGcFzxbc+f2 igTVI96DxeuvqfOtsBX637HCyJLsGCIxWROJgi1heSsoiBbhi0OezOoxkStllHCqJG wgqedMKm10llYfsHctSPA6NpF7mKJnj2SASggAIJSphpc83V2iFUYfFL5QahiPhi6K /bwhoF/Cr0oJcJWqn42O1I7irKCtUSod1u38XjHxRdxw5nNIX+0mQeTqkiw68ICerC VOW6Qj8ZzWwow== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from fedora.willemsstb.de ([94.31.87.22]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1M3DO3-1oz4Bo0vLJ-003fyy; Tue, 06 Dec 2022 20:20:41 +0100 From: Markus Stockhausen To: linux-crypto@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH v2 4/6] crypto/realtek: skcipher algorithms Date: Tue, 6 Dec 2022 20:20:35 +0100 Message-Id: <20221206192037.608808-5-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206192037.608808-1-markus.stockhausen@gmx.de> References: <20221206192037.608808-1-markus.stockhausen@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:swL7VYpOD4QWk8c+aPsSJ374Ds8jb5y+mwauPeWiyyXjsnekLf7 7N0LcUu7p5XWUwuVQMj5q3nheD+VxmALHXyKKLaQB8CoPjtu0vUr4N2aed5kEyBraM/ts0W FpPx4SfZLnT/mxzpi/vT4IW7293psGScAmmnNaInYFLyuAEazmULwpHT3Zq8tbmytq+1tk8 ryUBgHEdullthKaaA24lw== UI-OutboundReport: notjunk:1;M01:P0:pzvlXN3M0Gg=;QslXLJtwS3mkWrK4E01GAW03Sk8 WoR3wL4JdMFSt/9tbkGTGgHx3u1fUtqeYwYi1qCBXtItb1X3mibyKGVDvbyfsV+ETB58WM+iI sljFfNZZ00o5DbHz2J581cIFzaSgqvtOZSAViUYsUuuap1EASC+b0jv2DWODWr+oCzpFVOQSu ZM70UkGPzxFMyp0eIge8f+xsnmJRSxxJh8QDECQgfuoXBipsW1Tn/HnJLk/GTtWo3nAm6EG9s /TT/ig7UQQQY9Q4+2BItXXb12VXcSgK5FrjwNKmnCXc5cUlrHm3FwFYgoKy7oq7tgYGNufaEO p5MlFvay3j460j8xDnnGAZgk610YscQSD+7foTVBYsYg+itMQ/EI3cgqoofJSLuqp/IAjK+S9 4h0l/gyUburdDVR4u6hc/JnPpNSRJvNsf7D6FggEw7WSxMxLQgRAkSZYndUtUP3Jweu9ksozk 6HuaHOKmzO0fYcc7qpDn7m6tafeXsSnMPycuZA5eOM//znlzKHJryNo9bhPLv0ufihUq0vwyK LSL8Gg0w5+DAXRb1ZkKvam0BrdRcY0tUdG2pFK5cNHlHfo31mOScfNY60WX5kZ4wXW5ua8U6W gPnDguaabY4diabKU++WaPbGSOLbrCTzkwW8fIHPQ8Yjgcij/ZDMIae3CvIwaDTQVoEfqF1vM lryjVl6Q1/F4F1ZKY21Cwb8idWwKimK5qa1OOatT5Qqvb2NbRJiU5zZQxihi17MBxTnZZ43w3 JGKHxrhYBkx5/H+Qcy7vQ5oM2JyF0pEZlhgGcJFoHsVRxa75JRuWpx81DNYjxcc10JvrosADs VydZlfysEhte//8LNyehBYqiEsDdgnFq7R88RQIvw2t1VHXCcR8X+HwLevhQangMYQHrqLxUH 7tbMvCQZs3WuW681RGhned2/ociOORxnVkKg4Za1i+An1ZLoFfAfhk9YRLFVZ+4QZIS2c2rls 6PcsFX08mk1p8uTJM5+pfl2RDqY= Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add ecb(aes), cbc(aes) and ctr(aes) skcipher algorithms for new Realtek crypto device. Signed-off-by: Markus Stockhausen --- .../crypto/realtek/realtek_crypto_skcipher.c | 361 ++++++++++++++++++ 1 file changed, 361 insertions(+) create mode 100644 drivers/crypto/realtek/realtek_crypto_skcipher.c -- 2.38.1 diff --git a/drivers/crypto/realtek/realtek_crypto_skcipher.c b/drivers/crypto/realtek/realtek_crypto_skcipher.c new file mode 100644 index 000000000000..6e2cde77b4d4 --- /dev/null +++ b/drivers/crypto/realtek/realtek_crypto_skcipher.c @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Crypto acceleration support for Realtek crypto engine. Based on ideas from + * Rockchip & SafeXcel driver plus Realtek OpenWrt RTK. + * + * Copyright (c) 2022, Markus Stockhausen + */ + +#include +#include + +#include "realtek_crypto.h" + +static inline void rtcr_inc_iv(u8 *iv, int cnt) +{ + u32 *ctr = (u32 *)iv + 4; + u32 old, new, carry = cnt; + + /* avoid looping with crypto_inc() */ + do { + old = be32_to_cpu(*--ctr); + new = old + carry; + *ctr = cpu_to_be32(new); + carry = (new < old) && (ctr > (u32 *)iv) ? 1 : 0; + } while (carry); +} + +static inline void rtcr_cut_skcipher_len(int *reqlen, int opmode, u8 *iv) +{ + int len = min(*reqlen, RTCR_MAX_REQ_SIZE); + + if (opmode & RTCR_SRC_OP_CRYPT_CTR) { + /* limit data as engine does not wrap around cleanly */ + u32 ctr = be32_to_cpu(*((u32 *)iv + 3)); + int blocks = min(~ctr, 0x3fffu) + 1; + + len = min(blocks * AES_BLOCK_SIZE, len); + } + + *reqlen = len; +} + +static inline void rtcr_max_skcipher_len(int *reqlen, struct scatterlist **sg, + int *sgoff, int *sgcnt) +{ + int len, cnt, sgnoff, sgmax = RTCR_MAX_SG_SKCIPHER, datalen, maxlen = *reqlen; + struct scatterlist *sgn; + +redo: + datalen = cnt = 0; + sgnoff = *sgoff; + sgn = *sg; + + while (sgn && (datalen < maxlen) && (cnt < sgmax)) { + cnt++; + len = min((int)sg_dma_len(sgn) - sgnoff, maxlen - datalen); + datalen += len; + if (len + sgnoff < sg_dma_len(sgn)) { + sgnoff = sgnoff + len; + break; + } + sgn = sg_next(sgn); + sgnoff = 0; + if (unlikely((cnt == sgmax) && (datalen < AES_BLOCK_SIZE))) { + /* expand search to get at least one block */ + sgmax = AES_BLOCK_SIZE; + maxlen = min(maxlen, AES_BLOCK_SIZE); + } + } + + if (unlikely((datalen < maxlen) && (datalen & (AES_BLOCK_SIZE - 1)))) { + /* recalculate to get aligned size */ + maxlen = datalen & ~(AES_BLOCK_SIZE - 1); + goto redo; + } + + *sg = sgn; + *sgoff = sgnoff; + *sgcnt = cnt; + *reqlen = datalen; +} + +static int rtcr_process_skcipher(struct skcipher_request *sreq, int opmode) +{ + char *dataout, *iv, ivbk[AES_BLOCK_SIZE], datain[AES_BLOCK_SIZE]; + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(sreq); + struct rtcr_skcipher_ctx *sctx = crypto_skcipher_ctx(tfm); + int totallen = sreq->cryptlen, sgoff = 0, dgoff = 0; + int padlen, sgnoff, sgcnt, reqlen, ret, fblen; + struct rtcr_crypto_dev *cdev = sctx->cdev; + struct scatterlist *sg = sreq->src, *sgn; + int idx, srcidx, dstidx, len, datalen; + + if (!totallen) + return 0; + + if ((totallen & (AES_BLOCK_SIZE - 1)) && (!(opmode & RTCR_SRC_OP_CRYPT_CTR))) + return -EINVAL; + +redo: + sgnoff = sgoff; + sgn = sg; + datalen = totallen; + + /* limit input so that engine can process it */ + rtcr_cut_skcipher_len(&datalen, opmode, sreq->iv); + rtcr_max_skcipher_len(&datalen, &sgn, &sgnoff, &sgcnt); + + /* CTR padding */ + padlen = (AES_BLOCK_SIZE - datalen) & (AES_BLOCK_SIZE - 1); + reqlen = datalen + padlen; + + fblen = 0; + if (sgcnt > RTCR_MAX_SG_SKCIPHER) { + /* single AES block with too many SGs */ + fblen = datalen; + sg_pcopy_to_buffer(sg, sgcnt, datain, datalen, sgoff); + } + + if ((opmode & RTCR_SRC_OP_CRYPT_CBC) && + (!(opmode & RTCR_SRC_OP_KAM_ENC))) { + /* CBC decryption IV might get overwritten */ + sg_pcopy_to_buffer(sg, sgcnt, ivbk, AES_BLOCK_SIZE, + sgoff + datalen - AES_BLOCK_SIZE); + } + + /* Get free space in the ring */ + if (padlen || (datalen + dgoff > sg_dma_len(sreq->dst))) { + len = datalen; + } else { + len = RTCR_WB_LEN_SG_DIRECT; + dataout = sg_virt(sreq->dst) + dgoff; + } + + ret = rtcr_alloc_ring(cdev, 2 + (fblen ? 1 : sgcnt) + (padlen ? 1 : 0), + &srcidx, &dstidx, len, &dataout); + if (ret) + return ret; + + /* Write back any uncommitted data to memory */ + if (dataout == sg_virt(sreq->src) + sgoff) { + dma_map_sg(cdev->dev, sg, sgcnt, DMA_BIDIRECTIONAL); + } else { + dma_sync_single_for_device(cdev->dev, virt_to_phys(dataout), + reqlen, DMA_BIDIRECTIONAL); + if (fblen) + dma_sync_single_for_device(cdev->dev, virt_to_phys(datain), + reqlen, DMA_TO_DEVICE); + else + dma_map_sg(cdev->dev, sg, sgcnt, DMA_TO_DEVICE); + } + + if (sreq->iv) + dma_sync_single_for_device(cdev->dev, virt_to_phys(sreq->iv), + AES_BLOCK_SIZE, DMA_TO_DEVICE); + /* + * Feed input data into the rings. Start with destination ring and fill + * source ring afterwards. Ensure that the owner flag of the first source + * ring is the last that becomes visible to the engine. + */ + rtcr_add_dst_to_ring(cdev, dstidx, dataout, reqlen, sreq->dst, dgoff); + + idx = rtcr_inc_src_idx(srcidx, 1); + rtcr_add_src_to_ring(cdev, idx, sreq->iv, AES_BLOCK_SIZE, reqlen); + + if (fblen) { + idx = rtcr_inc_src_idx(idx, 1); + rtcr_add_src_to_ring(cdev, idx, (void *)datain, fblen, reqlen); + } + + datalen -= fblen; + while (datalen) { + len = min((int)sg_dma_len(sg) - sgoff, datalen); + + idx = rtcr_inc_src_idx(idx, 1); + rtcr_add_src_to_ring(cdev, idx, sg_virt(sg) + sgoff, len, reqlen); + + datalen -= len; + sg = sg_next(sg); + sgoff = 0; + } + + if (padlen) { + idx = rtcr_inc_src_idx(idx, 1); + rtcr_add_src_to_ring(cdev, idx, (void *)empty_zero_page, padlen, reqlen); + } + + rtcr_add_src_pad_to_ring(cdev, idx, reqlen); + rtcr_add_src_skcipher_to_ring(cdev, srcidx, opmode, reqlen, sctx); + + /* Off we go */ + rtcr_kick_engine(cdev); + if (rtcr_wait_for_request(cdev, dstidx)) + return -EINVAL; + + /* Handle IV feedback as engine does not provide it */ + if (opmode & RTCR_SRC_OP_CRYPT_CTR) { + rtcr_inc_iv(sreq->iv, reqlen / AES_BLOCK_SIZE); + } else if (opmode & RTCR_SRC_OP_CRYPT_CBC) { + iv = opmode & RTCR_SRC_OP_KAM_ENC ? + dataout + reqlen - AES_BLOCK_SIZE : ivbk; + memcpy(sreq->iv, iv, AES_BLOCK_SIZE); + } + + sg = sgn; + sgoff = sgnoff; + dgoff += reqlen; + totallen -= min(reqlen, totallen); + + if (totallen) + goto redo; + + return 0; +} + +static int rtcr_skcipher_encrypt(struct skcipher_request *sreq) +{ + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(sreq); + struct rtcr_skcipher_ctx *sctx = crypto_skcipher_ctx(tfm); + int opmode = sctx->opmode | RTCR_SRC_OP_KAM_ENC; + + return rtcr_process_skcipher(sreq, opmode); +} + +static int rtcr_skcipher_decrypt(struct skcipher_request *sreq) +{ + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(sreq); + struct rtcr_skcipher_ctx *sctx = crypto_skcipher_ctx(tfm); + int opmode = sctx->opmode; + + opmode |= sctx->opmode & RTCR_SRC_OP_CRYPT_CTR ? + RTCR_SRC_OP_KAM_ENC : RTCR_SRC_OP_KAM_DEC; + + return rtcr_process_skcipher(sreq, opmode); +} + +static int rtcr_skcipher_setkey(struct crypto_skcipher *cipher, + const u8 *key, unsigned int keylen) +{ + struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); + struct rtcr_skcipher_ctx *sctx = crypto_tfm_ctx(tfm); + struct rtcr_crypto_dev *cdev = sctx->cdev; + struct crypto_aes_ctx kctx; + int p, i; + + if (aes_expandkey(&kctx, key, keylen)) + return -EINVAL; + + sctx->keylen = keylen; + sctx->opmode = (sctx->opmode & ~RTCR_SRC_OP_CIPHER_MASK) | + RTCR_SRC_OP_CIPHER_FROM_KEY(keylen); + + memcpy(sctx->key_enc, key, keylen); + /* decryption key is derived from expanded key */ + p = ((keylen / 4) + 6) * 4; + for (i = 0; i < 8; i++) { + sctx->key_dec[i] = cpu_to_le32(kctx.key_enc[p + i]); + if (i == 3) + p -= keylen == AES_KEYSIZE_256 ? 8 : 6; + } + + dma_sync_single_for_device(cdev->dev, virt_to_phys(sctx->key_enc), + 2 * AES_KEYSIZE_256, DMA_TO_DEVICE); + + return 0; +} + +static int rtcr_skcipher_cra_init(struct crypto_tfm *tfm) +{ + struct rtcr_skcipher_ctx *sctx = crypto_tfm_ctx(tfm); + struct rtcr_alg_template *tmpl; + + tmpl = container_of(tfm->__crt_alg, struct rtcr_alg_template, + alg.skcipher.base); + + sctx->cdev = tmpl->cdev; + sctx->opmode = tmpl->opmode; + + return 0; +} + +static void rtcr_skcipher_cra_exit(struct crypto_tfm *tfm) +{ + void *ctx = crypto_tfm_ctx(tfm); + + memzero_explicit(ctx, tfm->__crt_alg->cra_ctxsize); +} + +struct rtcr_alg_template rtcr_skcipher_ecb_aes = { + .type = RTCR_ALG_SKCIPHER, + .opmode = RTCR_SRC_OP_MS_CRYPTO | RTCR_SRC_OP_CRYPT_ECB, + .alg.skcipher = { + .setkey = rtcr_skcipher_setkey, + .encrypt = rtcr_skcipher_encrypt, + .decrypt = rtcr_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .base = { + .cra_name = "ecb(aes)", + .cra_driver_name = "realtek-ecb-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct rtcr_skcipher_ctx), + .cra_alignmask = 0, + .cra_init = rtcr_skcipher_cra_init, + .cra_exit = rtcr_skcipher_cra_exit, + .cra_module = THIS_MODULE, + }, + }, +}; + +struct rtcr_alg_template rtcr_skcipher_cbc_aes = { + .type = RTCR_ALG_SKCIPHER, + .opmode = RTCR_SRC_OP_MS_CRYPTO | RTCR_SRC_OP_CRYPT_CBC, + .alg.skcipher = { + .setkey = rtcr_skcipher_setkey, + .encrypt = rtcr_skcipher_encrypt, + .decrypt = rtcr_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .base = { + .cra_name = "cbc(aes)", + .cra_driver_name = "realtek-cbc-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct rtcr_skcipher_ctx), + .cra_alignmask = 0, + .cra_init = rtcr_skcipher_cra_init, + .cra_exit = rtcr_skcipher_cra_exit, + .cra_module = THIS_MODULE, + }, + }, +}; + +struct rtcr_alg_template rtcr_skcipher_ctr_aes = { + .type = RTCR_ALG_SKCIPHER, + .opmode = RTCR_SRC_OP_MS_CRYPTO | RTCR_SRC_OP_CRYPT_CTR, + .alg.skcipher = { + .setkey = rtcr_skcipher_setkey, + .encrypt = rtcr_skcipher_encrypt, + .decrypt = rtcr_skcipher_decrypt, + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .base = { + .cra_name = "ctr(aes)", + .cra_driver_name = "realtek-ctr-aes", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct rtcr_skcipher_ctx), + .cra_alignmask = 0, + .cra_init = rtcr_skcipher_cra_init, + .cra_exit = rtcr_skcipher_cra_exit, + .cra_module = THIS_MODULE, + }, + }, +}; From patchwork Tue Dec 6 19:20:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Stockhausen X-Patchwork-Id: 632960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D094CC3A5A7 for ; Tue, 6 Dec 2022 19:20:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbiLFTUs (ORCPT ); Tue, 6 Dec 2022 14:20:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229701AbiLFTUp (ORCPT ); Tue, 6 Dec 2022 14:20:45 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.15.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3853641990 for ; Tue, 6 Dec 2022 11:20:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.de; s=s31663417; t=1670354441; bh=f9WWL0ZIKMD+NKnDzl903S+l3tToc5izqiOcKL+3HcU=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=LwV1T7u6KVoUhDAgLSfGZ19lnpLo3Wh6Es3czVCO2RHN8/yv/VybdsJsy8WAu9t70 ERcoOInRD3cXNHqlsoknqmAEVhsFmh80w/s1tRClTXFBbXdu1GKIb/ZDBlU9fJRbgR hjP+XvZsa52KT+czX1WYFZIsWWk6jn3M7huLR3PSq2S+jXP03Xn6JhNyNRKkHrqQGz vaEhckGAAbKihGYSZbOKQXR4bAR6/nkWPn4CFdSo0PMkPpUNKZ6AVqadU6bHXYz4AH oTwH/dHW4ek+yMzgK7jBbiOKdn5v5sek9+knhuI29C5dF7bjMiE0MPRZ7ildUh+5Ox ew3N3N94pSY/Q== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from fedora.willemsstb.de ([94.31.87.22]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1MhU9Z-1oWrFa1kzT-00ed5y; Tue, 06 Dec 2022 20:20:41 +0100 From: Markus Stockhausen To: linux-crypto@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH v2 5/6] crypto/realtek: enable module Date: Tue, 6 Dec 2022 20:20:36 +0100 Message-Id: <20221206192037.608808-6-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206192037.608808-1-markus.stockhausen@gmx.de> References: <20221206192037.608808-1-markus.stockhausen@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:o4VE5jya59gO1oVlc7LTFfX3/1dQFWYti3MZ09wjp1NjDy8YMgp qTBYBAPYWSzxESVWtlgIPDpdHXDDsUchjdflDcDJeY5zlnaI0kH51PHWsSBd7CLkUrm6EBN 5eYRDENteV/sHaRUdElkyYsuFuxg4v3P1gv5KKadDiUjxUBo+12yMNqXf8rochQNi67XiPX 03HKmEh1o99jI4JTgAvRw== UI-OutboundReport: notjunk:1;M01:P0:wkg6hHHot/Y=;bx26l6Ur3oA8p7+EVzCua9qBEsl ePnyex1x/X4iMbBOo3stXYMPLkGa4I1Q7A07IUQMurHLU5PmJfyfesFCbCz7dUkuiMU/aflu+ KbJ3s/C1G2BR+bfXacn6yMtxOhq2WZQUeQeMJEQ6O3bTDRPIT9xHLlO0mqMbPEiGSTbntdVOF U3JbdYTzf/90hNj+DHui2o9v8IoKrTnGqiN/FvYyvPUTnH4QYen/NKB8AAcdn4tZ8XsK0TTfT NTHVzZ1WRUagOrfypoN6yxMBZx9iuA74W7l2+LN7fUdfALJOxCNpesZ27k/fv4NNRpf3PocHb eJ8of9rH1zSVX7pz4Wj0QAcDfsPR+oaF6hlEmXywyBwBtGKeTaZot3mRsnzblEswo/ZiPZZL8 jF+KyTxMEHa+DsvX7/UObZXSUGg78BuLvUTYvNSOqLAnrq9FbaDKuPetJPYgmSFR2O5i0GKTU 8N09YA1QmLKJsj2eLpjYOifJzSsIV9pu3x8mYgErwXTPxcBrz46TDvnDjsrshe7+c9tz+RSEl VmJGi5PwZ+coU2ab9Aoz/CVVOwpBkOrOnNv0TnUX2Dqy+5X03nFY9SMC7ooALiYDnV9CJIYTT pmfwa0+esxiHnHaiVa9wZXml4Ya46eQdzY+ASmrXE8wBedUR/6stCbac9MZcI5Gi8LxI5R3SL fFQFFTH1gaLiNPDADtxXAFI7bN81yHCeWsawZEirf79hYIS5W/vPDEglS5QDqdgWuhEugDjtM k4QmlSXJf9XRQeE44S8WU+yKHul+MgibP5bkL//X/1iMu2o/eV4MfriMawrHj3+HE57j9Rzs/ MdENYp3LPuxwrspYUkYQOlsKuSrtolMj0ciVjqbv5jprBmE8FoNMcQGA7irFN4+R1ztoxComU +te3VGqsCJWtYUYMMV+LWnLusqgv2n/O7Imh7gl1vvz4iubcKv7h9BcV6rKUUcBw7e3vh4C9s BwDU5a+Lj2Lp2YdtzqbPOryTFT0= Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add new Realtek crypto device to the kernel configuration. Signed-off-by: Markus Stockhausen --- drivers/crypto/Kconfig | 13 +++++++++++++ drivers/crypto/Makefile | 1 + drivers/crypto/realtek/Makefile | 5 +++++ 3 files changed, 19 insertions(+) create mode 100644 drivers/crypto/realtek/Makefile -- 2.38.1 diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 55e75fbb658e..990a74f7ad97 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -666,6 +666,19 @@ config CRYPTO_DEV_IMGTEC_HASH hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 hashing algorithms. +config CRYPTO_DEV_REALTEK + tristate "Realtek's Cryptographic Engine driver" + depends on OF && MIPS && CPU_BIG_ENDIAN + select CRYPTO_MD5 + select CRYPTO_SHA1 + select CRYPTO_AES + help + This driver adds support for the Realtek crypto engine. It provides + hardware accelerated AES, SHA1 & MD5 algorithms. It is included in + SoCs of the RTL838x series, such as RTL8380, RTL8381, RTL8382, as + well as SoCs from the RTL930x series, such as RTL9301, RTL9302 and + RTL9303. + config CRYPTO_DEV_ROCKCHIP tristate "Rockchip's Cryptographic Engine driver" depends on OF && ARCH_ROCKCHIP diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 116de173a66c..df4b4b7d7302 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) += qcom-rng.o +obj-$(CONFIG_CRYPTO_DEV_REALTEK) += realtek/ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o obj-$(CONFIG_CRYPTO_DEV_SA2UL) += sa2ul.o diff --git a/drivers/crypto/realtek/Makefile b/drivers/crypto/realtek/Makefile new file mode 100644 index 000000000000..8d973bf1d520 --- /dev/null +++ b/drivers/crypto/realtek/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_CRYPTO_DEV_REALTEK) += rtl_crypto.o +rtl_crypto-objs := realtek_crypto.o \ + realtek_crypto_skcipher.o \ + realtek_crypto_ahash.o From patchwork Tue Dec 6 19:20:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Stockhausen X-Patchwork-Id: 631374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD2C9C63704 for ; Tue, 6 Dec 2022 19:20:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229701AbiLFTUu (ORCPT ); Tue, 6 Dec 2022 14:20:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229702AbiLFTUp (ORCPT ); Tue, 6 Dec 2022 14:20:45 -0500 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F00940902 for ; Tue, 6 Dec 2022 11:20:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.de; s=s31663417; t=1670354441; bh=qhP4xagevY2rvdNlq0yus5MslI8QTd0WduUXHJHOFhE=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=d9HPfjA6z7darC+JVcKrCwfpR1Ut9J2dMSFD3WWpfjEHMlNLxpbQWMGRkiN7CuPNm iJjoalBOHaEJ4APYzsKPgNbMI02K+4oRPqIQdfCs6usdMarMBLi7NiXs2/x+pSeDZ3 JZDMrMFUVsZJWhGByvF3AZVsr8ErI0dZAT3pFHILz3Xb/FVWsPDmmYuQ/QnyHsij6v m5ULOJf0AT5Bx4imjwHrCXV5qbJSt+lkqaOgSOZv6/MX19h2Dyo0zYttkqDN0VW2vH 3OE+IS3zxNibRBuWdNfdFA804NQ6lM7x5YPNCyxOhJYd1gafiSe/2t4kKWpRnV6yyw cEwkdo/t8oPcw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from fedora.willemsstb.de ([94.31.87.22]) by mail.gmx.net (mrgmx004 [212.227.17.184]) with ESMTPSA (Nemesis) id 1N3bWr-1osydu2Hyd-010bwE; Tue, 06 Dec 2022 20:20:41 +0100 From: Markus Stockhausen To: linux-crypto@vger.kernel.org Cc: Markus Stockhausen Subject: [PATCH v2 6/6] crypto/realtek: add devicetree documentation Date: Tue, 6 Dec 2022 20:20:37 +0100 Message-Id: <20221206192037.608808-7-markus.stockhausen@gmx.de> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206192037.608808-1-markus.stockhausen@gmx.de> References: <20221206192037.608808-1-markus.stockhausen@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:4ydH6bfS5gSYDeu1BxjlbMefgyBp7SJJZArYGejjm8UFrUnwCPb H+eyhFNjynGRi0sSK3DAIiH8+yNN6HgZ7mYpsbxPOSIpJtvWswxnLb++xSOzjc4BHYK0u09 4H3tHAdgo62cuZC/w/T3eAKXBvLyE0aCzEeHTWoLQQHDgd/iTM/H8KV6Z0NTkhVFmOW77mN KqWCwyNWJNjccm3RuNDGg== UI-OutboundReport: notjunk:1;M01:P0:IaAgWUHpmeg=;O43+V+5trkJZwHoNKFoHkild/XK 1bPaUlfjCMf5tzOiLlRnCYcyEgZzLUvvpmm9Z0gTaAF3Xr46olcBUZH/Ih0X8xKjJ2UMLZhsx iV7CybLBmEuYYZ6pUbfKmSPEBNCr+6pRwrV9WvidHT0q6XFYTboCnD1+udJjkqymFzvYfFqS6 OZwmaH8uAmaJcqwYcTygK+NAjLFeusi3D177dlVpl/RUig7lnojZ4x+RD+4d8cw3eTge2ySjv hfEC0JwXk/iIDEmIwkhoX7fokoAmfdW5IRzkMJ0XVx+Ym3lWLqH3+cuOAwh2qsByozibLtLP/ m8ctZYv0OBdi0DkSBPdEnAkaw9MzuKucV+9MnFiM1FRIA1jvmeSZ6vVmQpF2qQQt2WNyEG/Lb G0JqDT2rHRAu2NhPxilOw63q/SMxfHOU7gJhplcsbRHHWJiKBW7f18zbvVcyj9xBbK+/4t49V +9F6KuCmoXocl5dSGmSQzT093DpnaNdnHC8GMu0arF3t+oJ29ysqErGyJ4QzTzbHjj7ABjjYQ MLM3Qt/ExkMF+ez2Qq+/KwmFZQWFXxDrPNjtEXu4RJnhlCgrJ6SsCFYSy4HTUIZ+UfMZ6hdts UzzvZ9RYgh+uGUpb+jlMvjb96Cj8TfR3hmoNOGNUz5AUMPCCOvE+vt1AOeISPv/RXZ1B7nrQe EQ80Cay2ABvUxYqwjU1swFc/d15wq7Jz7hDdjqzTZ+wM0ZS4wWGm1IOVbgilPfyAmPZp7K9xm ek6Zla4aQqAF7u3nbVaEPsJPeBR2n7pzDfcEt8KdmKDS49pU6MlfG2bbonUeQzXDMn/CNz/nE zkyonrLp3Kn1uuxmV9h6VH5MMlth0j/9MSCgshyiTmBbqULHYYZFEIMklYgkPiuS9LD25rxVi Nx1oRZjLQV36fg2MY827Cv5TwFUUHHNZpg9fIqg4OAFrdqBShZGSbXZ7D12gZ/X0lBifuFN3y k22hEw== Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add devicetree documentation of new Realtek crypto device. Signed-off-by: Markus Stockhausen --- .../crypto/realtek,realtek-crypto.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/realtek,realtek-crypto.yaml -- 2.38.1 diff --git a/Documentation/devicetree/bindings/crypto/realtek,realtek-crypto.yaml b/Documentation/devicetree/bindings/crypto/realtek,realtek-crypto.yaml new file mode 100644 index 000000000000..443195e2d850 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/realtek,realtek-crypto.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/realtek,realtek-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek crypto engine bindings + +maintainers: + - Markus Stockhausen + +description: | + The Realtek crypto engine provides hardware accelerated AES, SHA1 & MD5 + algorithms. It is included in SoCs of the RTL838x series, such as RTL8380, + RTL8381, RTL8382, as well as SoCs from the RTL930x series, such as RTL9301, + RTL9302 and RTL9303. + +properties: + compatible: + const: realtek,realtek-crypto + + reg: + minItems: 1 + maxItems: 1 + + interrupt-parent: + minItems: 1 + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 1 + +required: + - compatible + - reg + - interrupt-parent + - interrupts + +additionalProperties: false + +examples: + - | + crypto0: crypto@c000 { + compatible = "realtek,realtek-crypto"; + reg = <0xc000 0x10>; + interrupt-parent = <&intc>; + interrupts = <22 3>; + }; + +...