From patchwork Mon Dec 19 14:42:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 635564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EFDAC3DA7D for ; Mon, 19 Dec 2022 14:43:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231952AbiLSOnZ (ORCPT ); Mon, 19 Dec 2022 09:43:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232330AbiLSOnT (ORCPT ); Mon, 19 Dec 2022 09:43:19 -0500 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7471C2724; Mon, 19 Dec 2022 06:43:18 -0800 (PST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BJ9PqqB009699; Mon, 19 Dec 2022 06:43:11 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=bNCt+fkpc/Qu79iu7Av/HQdZvX6GNRSgI33Hmaf9tbk=; b=Vu6p1ayooMcf0M263SZbV6R1hn/8y5R+Dvn045OfFKdw0MzL5YnZLlaC0OAY+kae57Iv zxCjJDs8NNWnk/3Uc2VUEpaaKNfXZsT6Xv0FqqZeVCZsIpFWaJPf/Jd1Pi/9VO6AGjtQ Zo5dffi30yVch0JNXp5IRKrJMvhGuo/kl4XG46t/JdH9X9Lzg3LyiEo4nOAZgC5DeF4p 4dNkled4SftENn6y/8dJXtpoDgyFRYUwaMd3OFaV7GgJkNIwL3IBfdcUOiP0fueJHfpz NZp8EuAIJvw8WTQAiPivgh1S38t21nC72EmGrjY7G1VN+hqcGT9i6JLaeEwwCEcewNy1 OA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mjnans4hp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 19 Dec 2022 06:43:11 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Dec 2022 06:43:10 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 19 Dec 2022 06:43:10 -0800 Received: from localhost.localdomain (unknown [10.110.150.170]) by maili.marvell.com (Postfix) with ESMTP id D0D1B3F7054; Mon, 19 Dec 2022 06:43:09 -0800 (PST) From: Witold Sadowski To: CC: , , , , , , , , Subject: [PATCH 1/7] spi: cadence: Fix busy cycles calculation Date: Mon, 19 Dec 2022 06:42:48 -0800 Message-ID: <20221219144254.20883-2-wsadowski@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com> References: <20221219144254.20883-1-wsadowski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: RJBcxMAiMp0CF9OQrHHxf7Q3lxKWlFsm X-Proofpoint-ORIG-GUID: RJBcxMAiMp0CF9OQrHHxf7Q3lxKWlFsm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_01,2022-12-15_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org If xSPI is in x2/x4/x8 mode to calculate busy cycles, busy bits count must be divided by the number of lanes. If opcommand is using 8 busy bits, but SPI is in x4 mode, there will be only 2 busy cycles. Signed-off-by: Witold Sadowski Reviewed-by: Chandrakala Chavva Reviewed-by: Sunil Kovvuri Goutham --- drivers/spi/spi-cadence-xspi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 520b4cc69cdc..91db3c973167 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -177,7 +177,10 @@ #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \ FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \ ((op)->data.nbytes >> 16) & 0xffff) | \ - FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, (op)->dummy.nbytes * 8)) + FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \ + (op)->dummy.buswidth != 0 ? \ + (((op)->dummy.nbytes * 8) / (op)->dummy.buswidth) : \ + 0)) #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \ FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \ From patchwork Mon Dec 19 14:42:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 635566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD0AEC4332F for ; Mon, 19 Dec 2022 14:43:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231891AbiLSOnX (ORCPT ); Mon, 19 Dec 2022 09:43:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232271AbiLSOnR (ORCPT ); Mon, 19 Dec 2022 09:43:17 -0500 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 058C3638F; Mon, 19 Dec 2022 06:43:17 -0800 (PST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BJ9PqqC009699; Mon, 19 Dec 2022 06:43:12 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=dzyp+x7PZV/+Abe3mq//lTiwi0GxWUoTy9TqJJWfSRU=; b=RSFWeEp145CUxVUN1ghPkHLRqXvJcs5nJwG2zThV6MalXmdlBYdH3mWMU/l8L6dlJTT9 x6s/UCCFlodajmZ00vNeVPG/lvn+MAuW5rW4Rf+AmhLavqyCNz5cMdQoHGxrlIyZo9q7 MQHsb3HoWGpmhaXUvuF0Yr5G9uBwabiuw7ggE3jTZTAS2X1aZwNaZR3KQ8r/z6uShG9X 4P9gJkrJTGokdr0/vX1RNByw68D68lSnDvSWd3Sg3lYOSyRpDHnuLdKjsFGEfxsSO/bq YqCrWeK5i2G52yoWmSPnFD6F3yTZiZVmiiyQ9MkOf/wt/U5kdyTEPD7qMeKFlQK/RIbx EA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mjnans4hp-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 19 Dec 2022 06:43:12 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Dec 2022 06:43:10 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 19 Dec 2022 06:43:10 -0800 Received: from localhost.localdomain (unknown [10.110.150.170]) by maili.marvell.com (Postfix) with ESMTP id 3A6E03F7087; Mon, 19 Dec 2022 06:43:10 -0800 (PST) From: Witold Sadowski To: CC: , , , , , , , , Subject: [PATCH 2/7] spi: cadence: Change dt-bindings documentation for Cadence XSPI controller Date: Mon, 19 Dec 2022 06:42:49 -0800 Message-ID: <20221219144254.20883-3-wsadowski@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com> References: <20221219144254.20883-1-wsadowski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: WoNRhHcgF83oENSrfUbZU5vj7JyDB6LQ X-Proofpoint-ORIG-GUID: WoNRhHcgF83oENSrfUbZU5vj7JyDB6LQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_01,2022-12-15_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Interrupt property is not mandatory. Driver will switch into pooling mode if property will not be avalible. Signed-off-by: Witold Sadowski --- Documentation/devicetree/bindings/spi/cdns,xspi.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml index b8bb8a3dbf54..f71a9c74e2ca 100644 --- a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml @@ -40,7 +40,6 @@ properties: required: - compatible - reg - - interrupts unevaluatedProperties: false From patchwork Mon Dec 19 14:42:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 635563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08C75C4332F for ; Mon, 19 Dec 2022 14:43:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229794AbiLSOn1 (ORCPT ); Mon, 19 Dec 2022 09:43:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231926AbiLSOnU (ORCPT ); Mon, 19 Dec 2022 09:43:20 -0500 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 680596369; Mon, 19 Dec 2022 06:43:19 -0800 (PST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BJ9PoPe009678; Mon, 19 Dec 2022 06:43:12 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=D0oUrq7Lqfz+ranVw2W6f2mza1kwCbji745cITFuHqc=; b=IC6C/QZbgLLEmPwZeJMmOrZMMy8NvWNxm8DmsjxTokUWJPbJuYMapxiaOGWc124o4ViD qGMOIFC7yYetQM4tm+sLQtjCYZnQJ1O2H6eSjufbg37tC4BWChEElIhrAfbZCemSV9Ny vLtJ7s9il1PMiSJr+cuGMjH3y0kZpWSDoIavISGWh7OOEwu77yu1LlwebZxzvKGEjZUw BTRdpSbKq23RCkFl0yU5yirECA06MLSWVtphATiN0wmIkldXdksPEn0hT5cheQFdRr79 lyNLs3VQqlZdT2m1oe5dh4Kl61Ygd9HepcIUz3w9ONwbhWXTrBjuSbOBQjgtXdIg2g5N dg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mjnans4hr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 19 Dec 2022 06:43:12 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Dec 2022 06:43:10 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 19 Dec 2022 06:43:10 -0800 Received: from localhost.localdomain (unknown [10.110.150.170]) by maili.marvell.com (Postfix) with ESMTP id 978CF3F7091; Mon, 19 Dec 2022 06:43:10 -0800 (PST) From: Witold Sadowski To: CC: , , , , , , , , Subject: [PATCH 3/7] spi: cadence: Add polling mode support Date: Mon, 19 Dec 2022 06:42:50 -0800 Message-ID: <20221219144254.20883-4-wsadowski@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com> References: <20221219144254.20883-1-wsadowski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xnGTGLksJn9DNQqJ4GRphIe_1LLxm7ET X-Proofpoint-ORIG-GUID: xnGTGLksJn9DNQqJ4GRphIe_1LLxm7ET X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_01,2022-12-15_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org If IRQ is not configured, switch driver to polling mode instead of returning with error. Code is using SDMA interrupt flag to determine SDMA operation status, and stig ready flag to determine stig engine readiness. Signed-off-by: Witold Sadowski Reviewed-by: Chandrakala Chavva Reviewed-by: Sunil Kovvuri Goutham --- drivers/spi/spi-cadence-xspi.c | 66 +++++++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 91db3c973167..25db0d55d5ef 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -190,6 +190,9 @@ ((op)->data.dir == SPI_MEM_DATA_IN) ? \ CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE)) +#define CDNS_XSPI_POLL_TIMEOUT_US 1000 +#define CDNS_XSPI_POLL_DELAY_US 10 + enum cdns_xspi_stig_instr_type { CDNS_XSPI_STIG_INSTR_TYPE_0, CDNS_XSPI_STIG_INSTR_TYPE_1, @@ -293,6 +296,9 @@ static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi, { u32 intr_enable; + if (!cdns_xspi->irq) + return; + intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); if (enabled) intr_enable |= CDNS_XSPI_INTR_MASK; @@ -345,6 +351,28 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi) } } +bool cdns_xspi_stig_ready(struct cdns_xspi_dev *cdns_xspi) +{ + u32 ctrl_stat; + + return readl_relaxed_poll_timeout + (cdns_xspi->iobase + CDNS_XSPI_CTRL_STATUS_REG, + ctrl_stat, + ((ctrl_stat & BIT(3)) == 0), + CDNS_XSPI_POLL_DELAY_US, CDNS_XSPI_POLL_TIMEOUT_US); +} + +bool cdns_xspi_sdma_ready(struct cdns_xspi_dev *cdns_xspi) +{ + u32 ctrl_stat; + + return readl_relaxed_poll_timeout + (cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG, + ctrl_stat, + (ctrl_stat & CDNS_XSPI_SDMA_TRIGGER), + CDNS_XSPI_POLL_DELAY_US, CDNS_XSPI_POLL_TIMEOUT_US); +} + static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi, const struct spi_mem_op *op, bool data_phase) @@ -385,16 +413,26 @@ static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi, cdns_xspi_trigger_command(cdns_xspi, cmd_regs); - wait_for_completion(&cdns_xspi->sdma_complete); - if (cdns_xspi->sdma_error) { - cdns_xspi_set_interrupts(cdns_xspi, false); - return -EIO; + if (cdns_xspi->irq) { + wait_for_completion(&cdns_xspi->sdma_complete); + if (cdns_xspi->sdma_error) { + cdns_xspi_set_interrupts(cdns_xspi, false); + return -EIO; + } + } else { + if (cdns_xspi_sdma_ready(cdns_xspi)) + return -EIO; } cdns_xspi_sdma_handle(cdns_xspi); } - wait_for_completion(&cdns_xspi->cmd_complete); - cdns_xspi_set_interrupts(cdns_xspi, false); + if (cdns_xspi->irq) { + wait_for_completion(&cdns_xspi->cmd_complete); + cdns_xspi_set_interrupts(cdns_xspi, false); + } else { + if (cdns_xspi_stig_ready(cdns_xspi)) + return -EIO; + } cmd_status = cdns_xspi_check_command_status(cdns_xspi); if (cmd_status) @@ -580,13 +618,15 @@ static int cdns_xspi_probe(struct platform_device *pdev) cdns_xspi->irq = platform_get_irq(pdev, 0); if (cdns_xspi->irq < 0) - return -ENXIO; - - ret = devm_request_irq(dev, cdns_xspi->irq, cdns_xspi_irq_handler, - IRQF_SHARED, pdev->name, cdns_xspi); - if (ret) { - dev_err(dev, "Failed to request IRQ: %d\n", cdns_xspi->irq); - return ret; + cdns_xspi->irq = 0; + + if (cdns_xspi->irq) { + ret = devm_request_irq(dev, cdns_xspi->irq, cdns_xspi_irq_handler, + IRQF_SHARED, pdev->name, cdns_xspi); + if (ret) { + dev_err(dev, "Failed to request IRQ: %d\n", cdns_xspi->irq); + return ret; + } } cdns_xspi_print_phy_config(cdns_xspi); From patchwork Mon Dec 19 14:42:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 635386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3773AC3DA7C for ; Mon, 19 Dec 2022 14:43:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232355AbiLSOn2 (ORCPT ); Mon, 19 Dec 2022 09:43:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232348AbiLSOnU (ORCPT ); Mon, 19 Dec 2022 09:43:20 -0500 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D2616316; 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Mon, 19 Dec 2022 06:43:12 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Dec 2022 06:43:11 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 19 Dec 2022 06:43:11 -0800 Received: from localhost.localdomain (unknown [10.110.150.170]) by maili.marvell.com (Postfix) with ESMTP id EB2A23F7041; Mon, 19 Dec 2022 06:43:10 -0800 (PST) From: Witold Sadowski To: CC: , , , , , , , , Subject: [PATCH 4/7] spi: cadence: Change dt-bindings documentation for Cadence XSPI controller Date: Mon, 19 Dec 2022 06:42:51 -0800 Message-ID: <20221219144254.20883-5-wsadowski@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com> References: <20221219144254.20883-1-wsadowski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 5IXw_acPU3q4AbkPGEfsRV_dZPfU1GV2 X-Proofpoint-ORIG-GUID: 5IXw_acPU3q4AbkPGEfsRV_dZPfU1GV2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_01,2022-12-15_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add parameter cdns,read-size. Parameter is controlling SDMA read size length. Signed-off-by: Witold Sadowski --- Documentation/devicetree/bindings/spi/cdns,xspi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml index f71a9c74e2ca..1274e3bf68e6 100644 --- a/Documentation/devicetree/bindings/spi/cdns,xspi.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,xspi.yaml @@ -37,6 +37,10 @@ properties: interrupts: maxItems: 1 + cdns,read-size: + items: + - description: size of single SDMA read operation + required: - compatible - reg @@ -60,6 +64,7 @@ examples: reg-names = "io", "sdma", "aux"; interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; + cdns,read-size=<0>; flash@0 { compatible = "jedec,spi-nor"; From patchwork Mon Dec 19 14:42:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 635389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBF44C4167B for ; Mon, 19 Dec 2022 14:43:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232083AbiLSOnX (ORCPT ); Mon, 19 Dec 2022 09:43:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231545AbiLSOnT (ORCPT ); Mon, 19 Dec 2022 09:43:19 -0500 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D5F362C5; Mon, 19 Dec 2022 06:43:18 -0800 (PST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BJ9PqqE009699; Mon, 19 Dec 2022 06:43:12 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=zaMB3AHu3ynPWiKaemebld3Nh2wqXea1HpUvMiEtxv0=; b=KBCo5ZGMrDoxYUw++IkwPTavmsblZMnhuOBb7oIFwRSmnlkwD7d0mU6z98Lcg3B3Z1Sk kRXA0woRHcuGBcyWg3owj/jAJ/7KfRmr1BKM5q3SYS5+rVapixrQ7oIOWD5J+eFwkdoG HZoGSncXRDMZz66+wrNFXhoRHGaTZV8D9D0X2FxRTG/l/8KbC51QWqi+HGjJgZfHhbjt BHv5VoBHx4fXymUAyvJb/ZxcGs+1lV5ScF9+GaOuaDXM0utKMbU8xofiyO+AsfDyJHpd pr8YC9r5DB+ikYT2jV6ehFrvHhHPm4VOlU9wGDbS7m+x3EK8P8So+Ffo+e31RDNRkyUW yg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mjnans4hp-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 19 Dec 2022 06:43:12 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Dec 2022 06:43:11 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 19 Dec 2022 06:43:11 -0800 Received: from localhost.localdomain (unknown [10.110.150.170]) by maili.marvell.com (Postfix) with ESMTP id 53D5A3F7054; Mon, 19 Dec 2022 06:43:11 -0800 (PST) From: Witold Sadowski To: CC: , , , , , , , , Subject: [PATCH 5/7] spi: cadence: Add read access size switch Date: Mon, 19 Dec 2022 06:42:52 -0800 Message-ID: <20221219144254.20883-6-wsadowski@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com> References: <20221219144254.20883-1-wsadowski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: QyPaAvPnBBoBXIQwuFQ8pOscZWR-e-n4 X-Proofpoint-ORIG-GUID: QyPaAvPnBBoBXIQwuFQ8pOscZWR-e-n4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_01,2022-12-15_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Allow to use different SDMA read size. In Marvell implementation of that IP each SDMA access will read 8 bytes at once, and is not configurable. Signed-off-by: Witold Sadowski Reviewed-by: Chandrakala Chavva Tested-by: Sunil Kovvuri Goutham --- drivers/spi/spi-cadence-xspi.c | 99 ++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 25db0d55d5ef..719c2f3b4771 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -209,6 +209,11 @@ enum cdns_xspi_stig_cmd_dir { CDNS_XSPI_STIG_CMD_DIR_WRITE, }; +enum cdns_xspi_sdma_size { + CDNS_XSPI_SDMA_SIZE_8B = 0, + CDNS_XSPI_SDMA_SIZE_64B = 1, +}; + struct cdns_xspi_dev { struct platform_device *pdev; struct device *dev; @@ -230,6 +235,7 @@ struct cdns_xspi_dev { const void *out_buffer; u8 hw_num_banks; + enum cdns_xspi_sdma_size read_size; }; static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi) @@ -329,6 +335,82 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi) return 0; } +static void cdns_ioreadq(void __iomem *addr, void *buf, int len) +{ + int i = 0; + int rcount = len / 8; + int rcount_nf = len % 8; + uint64_t tmp; + uint64_t *buf64 = (uint64_t *)buf; + + if (((uint64_t)buf % 8) == 0) { + for (i = 0; i < rcount; i++) + *buf64++ = readq(addr); + } else { + for (i = 0; i < rcount; i++) { + tmp = readq(addr); + memcpy(buf+(i*8), &tmp, 8); + } + } + + if (rcount_nf != 0) { + tmp = readq(addr); + memcpy(buf+(i*8), &tmp, rcount_nf); + } +} + +static void cdns_iowriteq(void __iomem *addr, const void *buf, int len) +{ + int i = 0; + int rcount = len / 8; + int rcount_nf = len % 8; + uint64_t tmp; + uint64_t *buf64 = (uint64_t *)buf; + + if (((uint64_t)buf % 8) == 0) { + for (i = 0; i < rcount; i++) + writeq(*buf64++, addr); + } else { + for (i = 0; i < rcount; i++) { + memcpy(&tmp, buf+(i*8), 8); + writeq(tmp, addr); + } + } + + if (rcount_nf != 0) { + memcpy(&tmp, buf+(i*8), rcount_nf); + writeq(tmp, addr); + } +} + +static void cdns_xspi_sdma_memread(struct cdns_xspi_dev *cdns_xspi, + enum cdns_xspi_sdma_size size, int len) +{ + switch (size) { + case CDNS_XSPI_SDMA_SIZE_8B: + ioread8_rep(cdns_xspi->sdmabase, + cdns_xspi->in_buffer, len); + break; + case CDNS_XSPI_SDMA_SIZE_64B: + cdns_ioreadq(cdns_xspi->sdmabase, cdns_xspi->in_buffer, len); + break; + } +} + +static void cdns_xspi_sdma_memwrite(struct cdns_xspi_dev *cdns_xspi, + enum cdns_xspi_sdma_size size, int len) +{ + switch (size) { + case CDNS_XSPI_SDMA_SIZE_8B: + iowrite8_rep(cdns_xspi->sdmabase, + cdns_xspi->out_buffer, len); + break; + case CDNS_XSPI_SDMA_SIZE_64B: + cdns_iowriteq(cdns_xspi->sdmabase, cdns_xspi->out_buffer, len); + break; + } +} + static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi) { u32 sdma_size, sdma_trd_info; @@ -340,13 +422,15 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi) switch (sdma_dir) { case CDNS_XSPI_SDMA_DIR_READ: - ioread8_rep(cdns_xspi->sdmabase, - cdns_xspi->in_buffer, sdma_size); + cdns_xspi_sdma_memread(cdns_xspi, + cdns_xspi->read_size, + sdma_size); break; case CDNS_XSPI_SDMA_DIR_WRITE: - iowrite8_rep(cdns_xspi->sdmabase, - cdns_xspi->out_buffer, sdma_size); + cdns_xspi_sdma_memwrite(cdns_xspi, + cdns_xspi->read_size, + sdma_size); break; } } @@ -526,7 +610,14 @@ static int cdns_xspi_of_get_plat_data(struct platform_device *pdev) { struct device_node *node_prop = pdev->dev.of_node; struct device_node *node_child; + struct spi_master *master = platform_get_drvdata(pdev); + struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(master); unsigned int cs; + unsigned int read_size = 0; + + if (of_property_read_u32(node_prop, "cdns,read-size", &read_size)) + dev_info(&pdev->dev, "Missing read size property, usining byte access\n"); + cdns_xspi->read_size = read_size; for_each_child_of_node(node_prop, node_child) { if (!of_device_is_available(node_child)) From patchwork Mon Dec 19 14:42:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 635387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A1B2C4708E for ; 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Mon, 19 Dec 2022 06:43:11 -0800 (PST) From: Witold Sadowski To: CC: , , , , , , , , Subject: [PATCH 6/7] spi: cadence: Add Marvell IP modification changes Date: Mon, 19 Dec 2022 06:42:53 -0800 Message-ID: <20221219144254.20883-7-wsadowski@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com> References: <20221219144254.20883-1-wsadowski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: _BllMQlznrPELbW7lqPEphys7WnTNcKt X-Proofpoint-ORIG-GUID: _BllMQlznrPELbW7lqPEphys7WnTNcKt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_01,2022-12-15_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add support for Marvell IP modification - clock divider, and PHY config, and IRQ clearing. Clock divider block is build into Cadence XSPI controller and is connected directly to 800MHz clock. As PHY config is not set directly in IP block, driver can load custom PHY configuration values. To correctly clear interrupt in Marvell implementation MSI-X must be cleared too. Signed-off-by: Witold Sadowski Reviewed-by: Chandrakala Chavva Tested-by: Sunil Kovvuri Goutham --- drivers/spi/Kconfig | 12 +++ drivers/spi/spi-cadence-xspi.c | 172 ++++++++++++++++++++++++++++++++- 2 files changed, 183 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3b1c0878bb85..42af5943d00a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -251,6 +251,18 @@ config SPI_CADENCE_XSPI device with a Cadence XSPI controller and want to access the Flash as an MTD device. +config SPI_CADENCE_MRVL_XSPI + tristate "Marvell mods for XSPI controller" + depends on SPI_CADENCE_XSPI + + help + Enable support for Marvell XSPI modifications + + During implementation of Cadence XSPI core Marvell + has added some additional features like clock divider, + PHY config support or non-memory SPI capabilities. + Enable that option if you want to enable these features. + config SPI_CLPS711X tristate "CLPS711X host SPI controller" depends on ARCH_CLPS711X || COMPILE_TEST diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 719c2f3b4771..c73faf6b0546 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -193,6 +193,46 @@ #define CDNS_XSPI_POLL_TIMEOUT_US 1000 #define CDNS_XSPI_POLL_DELAY_US 10 +#if IS_ENABLED(CONFIG_SPI_CADENCE_MRVL_XSPI) +/* clock config register */ +#define CDNS_XSPI_CLK_CTRL_AUX_REG 0x2020 +#define CDNS_XSPI_CLK_ENABLE BIT(0) +#define CDNS_XSPI_CLK_DIV GENMASK(4, 1) + +/* Clock macros */ +#define CDNS_XSPI_CLOCK_IO_HZ 800000000 +#define CDNS_XSPI_CLOCK_DIVIDED(div) ((CDNS_XSPI_CLOCK_IO_HZ) / (div)) + +/*PHY default values*/ +#define REGS_DLL_PHY_CTRL 0x00000707 +#define CTB_RFILE_PHY_CTRL 0x00004000 +#define RFILE_PHY_TSEL 0x00000000 +#define RFILE_PHY_DQ_TIMING 0x00000101 +#define RFILE_PHY_DQS_TIMING 0x00700404 +#define RFILE_PHY_GATE_LPBK_CTRL 0x00200030 +#define RFILE_PHY_DLL_MASTER_CTRL 0x00800000 +#define RFILE_PHY_DLL_SLAVE_CTRL 0x0000ff01 + +/*PHY config rtegisters*/ +#define CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL 0x1034 +#define CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL 0x0080 +#define CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL 0x0084 +#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING 0x0000 +#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING 0x0004 +#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL 0x0008 +#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL 0x000c +#define CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL 0x0010 +#define CDNS_XSPI_DATASLICE_RFILE_PHY_DLL_OBS_REG_0 0x001c + +#define CDNS_XSPI_DLL_RST_N BIT(24) +#define CDNS_XSPI_DLL_LOCK BIT(0) + +/* MSI-X clear interrupt register */ +#define CDNS_XSPI_SPIX_INTR_AUX 0x2000 +#define CDNS_MSIX_CLEAR_IRQ 0x01 + +#endif + enum cdns_xspi_stig_instr_type { CDNS_XSPI_STIG_INSTR_TYPE_0, CDNS_XSPI_STIG_INSTR_TYPE_1, @@ -238,6 +278,106 @@ struct cdns_xspi_dev { enum cdns_xspi_sdma_size read_size; }; +#if IS_ENABLED(CONFIG_SPI_CADENCE_MRVL_XSPI) + +#define MRVL_DEFAULT_CLK 25000000 + +const int cdns_xspi_clk_div_list[] = { + 4, //0x0 = Divide by 4. SPI clock is 200 MHz. + 6, //0x1 = Divide by 6. SPI clock is 133.33 MHz. + 8, //0x2 = Divide by 8. SPI clock is 100 MHz. + 10, //0x3 = Divide by 10. SPI clock is 80 MHz. + 12, //0x4 = Divide by 12. SPI clock is 66.666 MHz. + 16, //0x5 = Divide by 16. SPI clock is 50 MHz. + 18, //0x6 = Divide by 18. SPI clock is 44.44 MHz. + 20, //0x7 = Divide by 20. SPI clock is 40 MHz. + 24, //0x8 = Divide by 24. SPI clock is 33.33 MHz. + 32, //0x9 = Divide by 32. SPI clock is 25 MHz. + 40, //0xA = Divide by 40. SPI clock is 20 MHz. + 50, //0xB = Divide by 50. SPI clock is 16 MHz. + 64, //0xC = Divide by 64. SPI clock is 12.5 MHz. + 128, //0xD = Divide by 128. SPI clock is 6.25 MHz. + -1 //End of list +}; + +static bool cdns_xspi_reset_dll(struct cdns_xspi_dev *cdns_xspi) +{ + u32 dll_cntrl = readl(cdns_xspi->iobase + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); + u32 dll_lock; + + /*Reset DLL*/ + dll_cntrl |= CDNS_XSPI_DLL_RST_N; + writel(dll_cntrl, cdns_xspi->iobase + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); + + /*Wait for DLL lock*/ + return readl_relaxed_poll_timeout(cdns_xspi->iobase + + CDNS_XSPI_INTR_STATUS_REG, + dll_lock, ((dll_lock & CDNS_XSPI_DLL_LOCK) == 1), 10, 10000); +} + +//Static confiuration of PHY +static bool cdns_xspi_configure_phy(struct cdns_xspi_dev *cdns_xspi) +{ + writel(REGS_DLL_PHY_CTRL, + cdns_xspi->iobase + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); + writel(CTB_RFILE_PHY_CTRL, + cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL); + writel(RFILE_PHY_TSEL, + cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL); + writel(RFILE_PHY_DQ_TIMING, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING); + writel(RFILE_PHY_DQS_TIMING, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING); + writel(RFILE_PHY_GATE_LPBK_CTRL, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL); + writel(RFILE_PHY_DLL_MASTER_CTRL, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL); + writel(RFILE_PHY_DLL_SLAVE_CTRL, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL); + + return cdns_xspi_reset_dll(cdns_xspi); +} + +// Find max avalible clock +static bool cdns_xspi_setup_clock(struct cdns_xspi_dev *cdns_xspi, int requested_clk) +{ + int i = 0; + int clk_val; + u32 clk_reg; + bool update_clk = false; + + while (cdns_xspi_clk_div_list[i] > 0) { + clk_val = CDNS_XSPI_CLOCK_DIVIDED(cdns_xspi_clk_div_list[i]); + if (clk_val <= requested_clk) + break; + i++; + } + + if (cdns_xspi_clk_div_list[i] == -1) { + dev_info(cdns_xspi->dev, "Unable to find clock divider for CLK: %d - setting 6.25MHz\n", + requested_clk); + i = 0x0D; + } else { + dev_dbg(cdns_xspi->dev, "Found clk div: %d, clk val: %d\n", + cdns_xspi_clk_div_list[i], + CDNS_XSPI_CLOCK_DIVIDED(cdns_xspi_clk_div_list[i])); + } + + clk_reg = readl(cdns_xspi->auxbase + CDNS_XSPI_CLK_CTRL_AUX_REG); + + if (FIELD_GET(CDNS_XSPI_CLK_DIV, clk_reg) != i) { + clk_reg = FIELD_PREP(CDNS_XSPI_CLK_DIV, i); + clk_reg |= CDNS_XSPI_CLK_ENABLE; + update_clk = true; + } + + if (update_clk) + writel(clk_reg, cdns_xspi->auxbase + CDNS_XSPI_CLK_CTRL_AUX_REG); + + return update_clk; +} +#endif + static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi) { u32 ctrl_stat; @@ -328,6 +468,9 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi) return -EIO; } + writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG), + cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG); + ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG); cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features); cdns_xspi_set_interrupts(cdns_xspi, false); @@ -534,6 +677,10 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi, if (cdns_xspi->cur_cs != mem->spi->chip_select) cdns_xspi->cur_cs = mem->spi->chip_select; +#if IS_ENABLED(CONFIG_SPI_CADENCE_MRVL_XSPI) + cdns_xspi_setup_clock(cdns_xspi, mem->spi->max_speed_hz); +#endif + return cdns_xspi_send_stig_command(cdns_xspi, op, (dir != SPI_MEM_NO_DATA)); } @@ -574,6 +721,10 @@ static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev) irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); +#if IS_ENABLED(CONFIG_SPI_CADENCE_MRVL_XSPI) + writel(CDNS_MSIX_CLEAR_IRQ, cdns_xspi->auxbase + CDNS_XSPI_SPIX_INTR_AUX); +#endif + if (irq_status & (CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER | CDNS_XSPI_STIG_DONE)) { @@ -654,6 +805,18 @@ static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi) readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL)); } +#if IS_ENABLED(CONFIG_SPI_CADENCE_MRVL_XSPI) +static int cdns_xspi_setup(struct spi_device *spi_dev) +{ + struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master); + + cdns_xspi_setup_clock(cdns_xspi, spi_dev->max_speed_hz); + + return 0; +} +#endif + + static int cdns_xspi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -673,6 +836,9 @@ static int cdns_xspi_probe(struct platform_device *pdev) master->mem_ops = &cadence_xspi_mem_ops; master->dev.of_node = pdev->dev.of_node; master->bus_num = -1; +#if IS_ENABLED(CONFIG_SPI_CADENCE_MRVL_XSPI) + master->setup = cdns_xspi_setup; +#endif platform_set_drvdata(pdev, master); @@ -720,8 +886,12 @@ static int cdns_xspi_probe(struct platform_device *pdev) } } - cdns_xspi_print_phy_config(cdns_xspi); +#if IS_ENABLED(CONFIG_SPI_CADENCE_MRVL_XSPI) + cdns_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK); + cdns_xspi_configure_phy(cdns_xspi); +#endif + cdns_xspi_print_phy_config(cdns_xspi); ret = cdns_xspi_controller_init(cdns_xspi); if (ret) { dev_err(dev, "Failed to initialize controller\n"); From patchwork Mon Dec 19 14:42:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 635565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B70AEC3DA78 for ; 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Mon, 19 Dec 2022 06:43:12 -0800 (PST) From: Witold Sadowski To: CC: , , , , , , , , Subject: [PATCH 7/7] spi: cadence: Force single modebyte Date: Mon, 19 Dec 2022 06:42:54 -0800 Message-ID: <20221219144254.20883-8-wsadowski@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219144254.20883-1-wsadowski@marvell.com> References: <20221219144254.20883-1-wsadowski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: po9GJS0Ptej4WzyagKvGAkmlOGm7ofJD X-Proofpoint-ORIG-GUID: po9GJS0Ptej4WzyagKvGAkmlOGm7ofJD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-19_01,2022-12-15_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org During dummy-cycles xSPI will switch GPIO into Hi-Z mode. To prevent unforeseen consequences of that behaviour, force send single modebyte(0x00). Modebyte will be send only if number of dummy-cycles is not equal to 0. Code must also reduce dummycycle byte count by one - as one byte is send as modebyte. Signed-off-by: Witold Sadowski Reviewed-by: Chandrakala Chavva --- drivers/spi/spi-cadence-xspi.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index c73faf6b0546..7d467169f62b 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -146,6 +146,9 @@ #define CDNS_XSPI_STIG_DONE_FLAG BIT(0) #define CDNS_XSPI_TRD_STATUS 0x0104 +#define MODE_NO_OF_BYTES GENMASK(25, 24) +#define MODEBYTES_COUNT 1 + /* Helper macros for filling command registers */ #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \ FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \ @@ -158,9 +161,10 @@ FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \ FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF)) -#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op) ( \ +#define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, modebytes) ( \ FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \ FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \ + FIELD_PREP(MODE_NO_OF_BYTES, modebytes) | \ FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes)) #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \ @@ -174,12 +178,12 @@ #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \ FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF) -#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \ +#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes) ( \ FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \ ((op)->data.nbytes >> 16) & 0xffff) | \ FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \ (op)->dummy.buswidth != 0 ? \ - (((op)->dummy.nbytes * 8) / (op)->dummy.buswidth) : \ + (((dummybytes) * 8) / (op)->dummy.buswidth) : \ 0)) #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \ @@ -607,6 +611,7 @@ static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi, u32 cmd_regs[6]; u32 cmd_status; int ret; + int dummybytes = op->dummy.nbytes; ret = cdns_xspi_wait_for_controller_idle(cdns_xspi); if (ret < 0) @@ -621,7 +626,12 @@ static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi, memset(cmd_regs, 0, sizeof(cmd_regs)); cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase); cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op); - cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op); + if (dummybytes != 0) { + cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 1); + dummybytes--; + } else { + cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 0); + } cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, cdns_xspi->cur_cs); @@ -631,7 +641,7 @@ static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi, cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG; cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op); cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op); - cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op); + cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes); cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, cdns_xspi->cur_cs);