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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id f14-20020a056870898e00b0014474019e50sm5994933oaq.24.2022.12.20.05.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 05:53:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PULL 02/15] hw/sd/sdhci: MMIO region is implemented in 32-bit accesses Date: Tue, 20 Dec 2022 10:52:38 -0300 Message-Id: <20221220135251.155176-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220135251.155176-1-danielhb413@gmail.com> References: <20221220135251.155176-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Tested-by: Bernhard Beschow Reviewed-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221101222934.52444-2-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza --- hw/sd/sdhci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 306070c872..22c758ad91 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1332,6 +1332,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) static const MemoryRegionOps sdhci_mmio_ops = { .read = sdhci_read, .write = sdhci_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 1, .max_access_size = 4, From patchwork Tue Dec 20 13:52:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 635456 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp2926991pvb; Tue, 20 Dec 2022 05:55:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf6nJgzKbECL49oxP/DSY6GUk2aLabXBMzUBJS/xWctjpeFJ7nQluOPXlEe5dTFcD4FLGtUc X-Received: by 2002:ac8:545a:0:b0:3a8:649:8d0a with SMTP id d26-20020ac8545a000000b003a806498d0amr53972881qtq.30.1671544553700; Tue, 20 Dec 2022 05:55:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671544553; cv=none; d=google.com; s=arc-20160816; b=UEQNfY0OOa9iXwfR2UeqY04GVsydRVvt5gRF0gV1LalD1quK8L6oRT/xRnxD6TyqvZ ucrbruqePcq4KWU6gq7rDHHTjTrJR3RDnUsYalDaHJWM9stqutgYplZqTMqpbmgF3oYB MZAkP+CQkkrfMZbEmWlbRrx9LX7ZxYn+BOo3E1K6Eaz+VVNXriaMs1T7emgxE/M7ZsKn EQHZaJu+KITuVQRx3CLWXeVv8W4sofxE0d498ICI+kFSo5fgVjgrBf3xkwWAyz+k7Fjt tM6yyJRxONhz0WnUDbPqWI683NpxwMABBGV8wbF+aR4c4qRP2/H9W6aIiC7ZByWiUa/A rZLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1VvlOM0ugm9Fr/4dQpsfYlJvQEM3Fz2babkbnBncbxQ=; b=fDvwz0rwGYOFrRg0oDSLXrSXoSsC+JHrSjD/aHfdOYu6gt2fc9T3n4wkKY5wW8yyin Qlshh9OH+TGfaPz0ShatTC2J8RBRZ3GYNq/aYSMGuQPhkTWtpeFW31rc6KtZVZk0W/6L G6uhxYjqMP+3vB9QcqNQtT4zIU9o4mq6TgZ/gr4TaTfDxcuOvRHRiUEMwjJPLRkbNrTu Mbm04pUQmmWtlY9mMzKBSPjyYTChadG6A9DEsvwBoNNmQagjFNSoUCXIVg/lonjr26YS BNo4pGds5NbHfgsiiZvahx0rvIANxZXCsD+VmRHTK0zbi8PgpiqI5PC+JineQ//9JPhr v2yA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=T4N8ldII; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id f14-20020a056870898e00b0014474019e50sm5994933oaq.24.2022.12.20.05.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 05:53:07 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PULL 03/15] hw/sd/sdhci: Support big endian SD host controller interfaces Date: Tue, 20 Dec 2022 10:52:39 -0300 Message-Id: <20221220135251.155176-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220135251.155176-1-danielhb413@gmail.com> References: <20221220135251.155176-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Some SDHCI IP can be synthetized in various endianness: https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. Our current implementation is little-endian. In order to support big endianness: - Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le') - Add an 'endianness' property to SDHCIState (default little endian) - Set the 'io_ops' field in realize() after checking the property - Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daudé Tested-by: Bernhard Beschow Reviewed-by: Bernhard Beschow Message-Id: <20221101222934.52444-3-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza --- hw/sd/sdhci-internal.h | 1 + hw/sd/sdhci.c | 32 +++++++++++++++++++++++++++++--- include/hw/sd/sdhci.h | 1 + 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 964570f8e8..5f3765f12d 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -308,6 +308,7 @@ extern const VMStateDescription sdhci_vmstate; #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ + DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDIAN), \ DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \ diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 22c758ad91..289baa879e 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1329,7 +1329,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) value >> shift, value >> shift); } -static const MemoryRegionOps sdhci_mmio_ops = { +static const MemoryRegionOps sdhci_mmio_le_ops = { .read = sdhci_read, .write = sdhci_write, .impl = { @@ -1344,6 +1344,21 @@ static const MemoryRegionOps sdhci_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static const MemoryRegionOps sdhci_mmio_be_ops = { + .read = sdhci_read, + .write = sdhci_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) { ERRP_GUARD(); @@ -1371,8 +1386,6 @@ void sdhci_initfn(SDHCIState *s) s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); - - s->io_ops = &sdhci_mmio_ops; } void sdhci_uninitfn(SDHCIState *s) @@ -1388,10 +1401,23 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) { ERRP_GUARD(); + switch (s->endianness) { + case DEVICE_LITTLE_ENDIAN: + s->io_ops = &sdhci_mmio_le_ops; + break; + case DEVICE_BIG_ENDIAN: + s->io_ops = &sdhci_mmio_be_ops; + break; + default: + error_setg(errp, "Incorrect endianness"); + return; + } + sdhci_init_readonly_registers(s, errp); if (*errp) { return; } + s->buf_maxsz = sdhci_get_fifolen(s); s->fifo_buffer = g_malloc0(s->buf_maxsz); diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 01a64c5442..a989fca3b2 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -96,6 +96,7 @@ struct SDHCIState { /* Configurable properties */ bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ uint32_t quirks; + uint8_t endianness; uint8_t sd_spec_version; uint8_t uhs_mode; uint8_t vendor; /* For vendor specific functionality */ From patchwork Tue Dec 20 13:52:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 635454 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp2926375pvb; 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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id f14-20020a056870898e00b0014474019e50sm5994933oaq.24.2022.12.20.05.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 05:53:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow Subject: [PULL 04/15] hw/ppc/e500: Add Freescale eSDHC to e500plat Date: Tue, 20 Dec 2022 10:52:40 -0300 Message-Id: <20221220135251.155176-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220135251.155176-1-danielhb413@gmail.com> References: <20221220135251.155176-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Adds missing functionality to e500plat machine which increases the chance of given "real" firmware images to access SD cards. Signed-off-by: Bernhard Beschow Message-Id: <20221018210146.193159-8-shentey@gmail.com> [PMD: Simplify using create_unimplemented_device("esdhc")] Signed-off-by: Philippe Mathieu-Daudé Tested-by: Bernhard Beschow Reviewed-by: Bernhard Beschow Message-Id: <20221101222934.52444-4-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza --- docs/system/ppc/ppce500.rst | 13 ++++++++++ hw/ppc/Kconfig | 2 ++ hw/ppc/e500.c | 48 ++++++++++++++++++++++++++++++++++++- hw/ppc/e500.h | 1 + hw/ppc/e500plat.c | 1 + 5 files changed, 64 insertions(+), 1 deletion(-) diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst index fa40e57d18..c9fe0915dc 100644 --- a/docs/system/ppc/ppce500.rst +++ b/docs/system/ppc/ppce500.rst @@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices: * Power-off functionality via one GPIO pin * 1 Freescale MPC8xxx PCI host controller * VirtIO devices via PCI bus +* 1 Freescale Enhanced Secure Digital Host controller (eSDHC) * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC) Hardware configuration information @@ -180,3 +181,15 @@ as follows: -kernel vmlinux \ -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \ -append "rootwait root=/dev/mtdblock0" + +Alternatively, the root file system can also reside on an emulated SD card +whose size must again be a power of two: + +.. code-block:: bash + + $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \ + -display none -serial stdio \ + -kernel vmlinux \ + -device sd-card,drive=mydrive \ + -drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \ + -append "rootwait root=/dev/mmcblk0" diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index b8d2522f45..72a311edcb 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -128,10 +128,12 @@ config E500 select PFLASH_CFI01 select PLATFORM_BUS select PPCE500_PCI + select SDHCI select SERIAL select MPC_I2C select FDT_PPC select DS1338 + select UNIMP config E500PLAT bool diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 2fe496677c..2bef2f01cb 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -48,6 +48,8 @@ #include "hw/net/fsl_etsec/etsec.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" +#include "hw/sd/sdhci.h" +#include "hw/misc/unimp.h" #define EPAPR_MAGIC (0x45504150) #define DTC_LOAD_PAD 0x1800000 @@ -66,11 +68,14 @@ #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL #define MPC8544_PCI_REGS_OFFSET 0x8000ULL #define MPC8544_PCI_REGS_SIZE 0x1000ULL +#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL +#define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL #define MPC8544_UTIL_OFFSET 0xe0000ULL #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL #define MPC8544_I2C_REGS_OFFSET 0x3000ULL #define MPC8XXX_GPIO_IRQ 47 #define MPC8544_I2C_IRQ 43 +#define MPC85XX_ESDHC_IRQ 72 #define RTC_REGS_OFFSET 0x68 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) @@ -203,6 +208,22 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, g_free(i2c); } +static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic) +{ + hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET; + hwaddr size = MPC85XX_ESDHC_REGS_SIZE; + int irq = MPC85XX_ESDHC_IRQ; + g_autofree char *name = NULL; + + name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0); + qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic); + qemu_fdt_setprop_cells(fdt, name, "bus-width", 4); + qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2); + qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size); + qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc"); +} typedef struct PlatformDevtreeData { void *fdt; @@ -553,6 +574,10 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms, dt_rtc_create(fdt, "i2c", "rtc"); + /* sdhc */ + if (pmc->has_esdhc) { + dt_sdhc_create(fdt, soc, mpic); + } gutil = g_strdup_printf("%s/global-utilities@%llx", soc, MPC8544_UTIL_OFFSET); @@ -982,7 +1007,8 @@ void ppce500_init(MachineState *machine) 0, qdev_get_gpio_in(mpicdev, 42), 399193, serial_hd(1), DEVICE_BIG_ENDIAN); } - /* I2C */ + + /* I2C */ dev = qdev_new("mpc-i2c"); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); @@ -992,6 +1018,26 @@ void ppce500_init(MachineState *machine) i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); + /* eSDHC */ + if (pmc->has_esdhc) { + create_unimplemented_device("esdhc", + pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET, + MPC85XX_ESDHC_REGS_SIZE); + + /* + * Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + * (See MPC8569E Reference Manual) + */ + dev = qdev_new(TYPE_SYSBUS_SDHCI); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN); + s = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ)); + memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET, + sysbus_mmio_get_region(s, 0)); + } /* General Utility device */ dev = qdev_new("mpc8544-guts"); diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 68f754ce50..8c09ef92e4 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -27,6 +27,7 @@ struct PPCE500MachineClass { int mpic_version; bool has_mpc8xxx_gpio; + bool has_esdhc; hwaddr platform_bus_base; hwaddr platform_bus_size; int platform_bus_first_irq; diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 5bb1c603da..44bf874b0f 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) pmc->fixup_devtree = e500plat_fixup_devtree; pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42; pmc->has_mpc8xxx_gpio = true; + pmc->has_esdhc = true; pmc->platform_bus_base = 0xf00000000ULL; pmc->platform_bus_size = 128 * MiB; pmc->platform_bus_first_irq = 5; From patchwork Tue Dec 20 13:52:41 2022 Content-Type: text/plain; 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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id f14-20020a056870898e00b0014474019e50sm5994933oaq.24.2022.12.20.05.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 05:53:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 05/15] target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h" Date: Tue, 20 Dec 2022 10:52:41 -0300 Message-Id: <20221220135251.155176-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220135251.155176-1-danielhb413@gmail.com> References: <20221220135251.155176-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé kvm_ppc.h is missing various declarations from "cpu.h": target/ppc/kvm_ppc.h:128:40: error: unknown type name 'CPUPPCState'; did you mean 'CPUState'? static inline int kvmppc_get_hypercall(CPUPPCState *env, ^~~~~~~~~~~ CPUState include/qemu/typedefs.h:45:25: note: 'CPUState' declared here typedef struct CPUState CPUState; ^ target/ppc/kvm_ppc.h:134:40: error: unknown type name 'PowerPCCPU' static inline int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) ^ target/ppc/kvm_ppc.h:285:38: error: unknown type name 'hwaddr' hwaddr ptex, int n) ^ target/ppc/kvm_ppc.h:220:15: error: unknown type name 'target_ulong' static inline target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, ^ target/ppc/kvm_ppc.h:286:38: error: unknown type name 'ppc_hash_pte64_t' static inline void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Message-Id: <20221213123550.39302-2-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza --- target/ppc/kvm_ppc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index ee9325bf9a..5fd9753953 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -9,6 +9,9 @@ #ifndef KVM_PPC_H #define KVM_PPC_H +#include "exec/hwaddr.h" +#include "cpu.h" + #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") #ifdef CONFIG_KVM From patchwork Tue Dec 20 13:52:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 635459 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp2928644pvb; Tue, 20 Dec 2022 05:59:29 -0800 (PST) X-Google-Smtp-Source: AA0mqf7JTf5n4hawwSJPrevGlPL1cfvrehW056sB+Kb09xDUCzMvzOHu0yVQk4FBxFS9IQsG6MFf X-Received: by 2002:ac8:4a17:0:b0:3a7:e2df:e868 with SMTP id x23-20020ac84a17000000b003a7e2dfe868mr56334356qtq.41.1671544769801; Tue, 20 Dec 2022 05:59:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671544769; cv=none; d=google.com; s=arc-20160816; b=uiAk+47zmdaI4w0GEzj02bpvIE/zUcIQ9T8D3E9Y862DHwAFyHDroW8VgUZQiVTxqs N8UHMvGWIec6W/9h1Zk1rlWYhLrFH5s7ShXxjjaoQKuplb52e8LqxaN2zf+8F482a1pw hpvGhgyqrbDStLCiIrmN5RBLisELbVWkSJL16thSMnM5HnOQeXotbbB3/r1dAYj2B8Fs WBO/b6Lz0jKILCeJ51tDRbGRw3e9GbhY81i2C2E9CXS8JeRY2153mxmvN3+J9GpA/YPO qxzDAe2zdJbgazVrX0yEZkqqApB80kW6gyytJH3vUUCziJMypMJ30HuANRHno/wQG9yh bplg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=umE98gdRHDRDK4EVpp4UFfCVYlLLuK/yAYvtgaqx+tI=; b=0n5aw6EoK+6aYwLjbGrNMWwtjs3uZakRUAJ0nywvnmnOYtdGVvvw4DZdh5JOQPcoYI OZHw63d+RsTYrrW7LSW4y6OJ6tPNJ0SYzhDhTUnBO45sVLdg/a9J59MWeHvbADzAbaLU sq2vuyWjgxVWJthwkmuUcSdJkQYByenYfmY5KwyILBKogpIKN6cyuCXLB62JbuVwNAfa 6ey+BTgwE6ewhBrwMifs4ngwbEAk/YG6nQa5iitQ66hRL/un+Xb2MO1BMBF9dxMdS/VN ivQzQ9+S0R556BtysHklxGIQCbBy35RYqippGT0Z22Lzn/gqxrqAsU0NiD7oTud0k7Tw CRTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=JXaWnjf5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id f14-20020a056870898e00b0014474019e50sm5994933oaq.24.2022.12.20.05.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 05:53:14 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 06/15] hw/ppc/vof: Do not include the full "cpu.h" Date: Tue, 20 Dec 2022 10:52:42 -0300 Message-Id: <20221220135251.155176-7-danielhb413@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220135251.155176-1-danielhb413@gmail.com> References: <20221220135251.155176-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé "vof.h" doesn't need the full "cpu.h" to get the target_ulong definition, including "exec/cpu-defs.h" is enough. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Message-Id: <20221213123550.39302-3-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza --- include/hw/ppc/vof.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/ppc/vof.h b/include/hw/ppc/vof.h index f8c0effcaf..d3f293da8b 100644 --- a/include/hw/ppc/vof.h +++ b/include/hw/ppc/vof.h @@ -9,7 +9,7 @@ #include "qom/object.h" #include "exec/address-spaces.h" #include "exec/memory.h" -#include "cpu.h" +#include "exec/cpu-defs.h" typedef struct Vof { uint64_t top_addr; /* copied from rma_size */ From patchwork Tue Dec 20 13:52:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 635457 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp2927928pvb; Tue, 20 Dec 2022 05:57:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf5NgBFMTp/erJggihoCIVq4sTng/niG4l8MKRRKX0ZQxReNXVfZif++1D9Z+RSmFgXXL0+s X-Received: by 2002:ac8:4913:0:b0:3a6:a95a:f545 with SMTP id e19-20020ac84913000000b003a6a95af545mr58715648qtq.15.1671544678512; Tue, 20 Dec 2022 05:57:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671544678; cv=none; d=google.com; s=arc-20160816; b=qtpjXCUrw4/WkUHG6tDhXdE8h7uBDfCtP3OcrmmZb9l3N0QPRao6Ccwg17mxsFzZuc k4YFxVhb2LWEuhAGWOLj8+ZxwT8Uzo9Z1dpbVDYVXZuI4d0eKCvEm3tivSGoM6ZqhZDP prxiVg9qsFOHy+3WFWuOMib+mFz+w32koOfKC5+kLSN4GuqcnWItVmPnuH8lSBP2yIrC patwdEEzw8+/fSWEzPQRs/4u9IoaFUlMhQn7j6QC3uo8CPt+K738FQwUr2TfrLS0Q/HC SwDE/MCj1syiGYcAnWJyblITylLw91T5D+Ky2ErFN7Q4+8QZxugLwICJ0YMUXEhrUTRK Ml7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=G4SPXsEIXY0CS0seSoT5oNuwNukYT1XRaSgA4LvShkM=; b=AByzJ4x+PD03kZQnxg/QsvXgdvqvkGaOvFFnVMQAxcNusGrtVnkUOPOfdjfXvQCtc8 a2J+74qYI4EcKFJ1U1GOcuw7MGJfBHdwl3uhIDofcx7IgTiuRgtOuEDTyaG/8IaLVdAD NjeP5ifjX1r+55Yowfidh1PAQcVLxVs4wW5jwAOBBZR6YkPsL4Ipyiqfa0cV32APimJs qZRT3FhswKJxWYjvUDm5ITiRwC+qmyTUzdFnFEGkktL+Mf0r2o9/ozJzbH5LOPOw48N+ 6ZOdvtVMBiA/2NRZSD7evYOZXYb2xxVCEVtgQeKvT59pv8h8yK9BXStFKIqhk0FX4bD8 slMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=IriBOeyz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id f14-20020a056870898e00b0014474019e50sm5994933oaq.24.2022.12.20.05.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 05:53:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 07/15] hw/ppc/spapr: Reduce "vof.h" inclusion Date: Tue, 20 Dec 2022 10:52:43 -0300 Message-Id: <20221220135251.155176-8-danielhb413@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220135251.155176-1-danielhb413@gmail.com> References: <20221220135251.155176-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Currently objects including "hw/ppc/spapr.h" are forced to be target specific due to the inclusion of "vof.h" in "spapr.h". "spapr.h" only uses a Vof pointer, so doesn't require the structure declaration. The only place where Vof structure is accessed is in spapr.c, so include "vof.h" there, and forward declare the structure in "spapr.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Message-Id: <20221213123550.39302-4-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza --- hw/ppc/spapr.c | 1 + include/hw/ppc/spapr.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index dc850032ae..59641adaec 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -62,6 +62,7 @@ #include "hw/ppc/fdt.h" #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" +#include "hw/ppc/vof.h" #include "hw/qdev-properties.h" #include "hw/pci-host/spapr.h" #include "hw/pci/msi.h" diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 04a95669ab..5c8aabd444 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -12,7 +12,6 @@ #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ #include "hw/ppc/xics.h" /* For ICSState */ #include "hw/ppc/spapr_tpm_proxy.h" -#include "hw/ppc/vof.h" struct SpaprVioBus; struct SpaprPhbState; @@ -22,6 +21,8 @@ typedef struct SpaprEventLogEntry SpaprEventLogEntry; typedef struct SpaprEventSource SpaprEventSource; typedef struct SpaprPendingHpt SpaprPendingHpt; +typedef struct Vof Vof; + #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL #define SPAPR_ENTRY_POINT 0x100