From patchwork Fri Dec 23 15:38:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54A06C3DA7C for ; Fri, 23 Dec 2022 15:38:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236323AbiLWPi1 (ORCPT ); Fri, 23 Dec 2022 10:38:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235594AbiLWPi0 (ORCPT ); Fri, 23 Dec 2022 10:38:26 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D239037F91 for ; Fri, 23 Dec 2022 07:38:25 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id y16so4912654wrm.2 for ; Fri, 23 Dec 2022 07:38:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EtWGiVmifJ/p5NoM/SB2O4ZTTUxKNKwZjVeO5da62YQ=; b=eoViL67CheerY/GJogWInFCx8oEhaNaDJ48UxfpAPT6Yx1Y3wpgYmwCqQY/xro+8Nk H9dXTVmTUgsTw2FmT5LZlxfSMFMWIbXtJ4RYhSeeTeo1PP2XjumDJ2sAHQ+I+wY72ZTB kOWuDIydGIx04Z0lWdp7/qceGwBiUhEMZlalMIiXHPCKQjvpjB/QmpiVSGGOncGFzvxV cimB5EyTLlFkGxKuQiDyQ9TgimBARZj86hcn8gCvF6k/+IXAFtB53QDSYj3sRTbI+Ajt ManLmmEbaMQIgpLPmLUrgLhSxuRUakauAa8DMaeKWu65TnEteoditriEs6unm9um9EGN kMZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EtWGiVmifJ/p5NoM/SB2O4ZTTUxKNKwZjVeO5da62YQ=; b=PfNuQq65Ql73MaRKSKNiyKZCZPueZAAyULze8klU3wS+zHqGi/9sxvoUBB7XUd69G4 8IVDGJFQskDRGHl2L8bmo6Re44dAhil767GyIrD9MrIVRSLFpPvsOdwbiDj9N4FeDK+A tvVGm3M/XZK9GjMiQ5Mro6JWWHNmEczN5KZpsc4/QAtYLQJZHgxXGo2Wq6KRh9kDsXBm tSw1J09aiypKtITE6Yof2+GX3X8X7rWi64YaMnTmvbGcfgJfaxuBo26ILIS5R+G/iujM nnFIfEiyYYgFCCUHldmn1rg12+3qBDozOOsxpHuAdWqzmHm4SOQaXXgFX+l9G4QsXbKM aLfw== X-Gm-Message-State: AFqh2kqaayDijZtdbcUks3C7yicndOk24/cVq6DNZ6WFPvwEJymFwcDx D2xfkPlmPhf5d7wVxDpgZOQsGA== X-Google-Smtp-Source: AMrXdXsvyUizrp/5r9cTIoO918Nf7mGbUC58pP5NYbsh3QY2qzUAyosHyR6+vtJwjBjRFlLuAnqMCQ== X-Received: by 2002:adf:eb08:0:b0:242:e73:f636 with SMTP id s8-20020adfeb08000000b002420e73f636mr7834154wrn.4.1671809904392; Fri, 23 Dec 2022 07:38:24 -0800 (PST) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:24 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks , Krzysztof Kozlowski Subject: [PATCH v7 01/10] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm-dw-apb-timers-pwm2 Date: Fri, 23 Dec 2022 15:38:11 +0000 Message-Id: <20221223153820.404565-2-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the bindings for Synopsys' DesignWare PWM block as we will be adding DT/platform support to the Linux driver soon. Signed-off-by: Ben Dooks Reviewed-by: Krzysztof Kozlowski Acked-by: Uwe Kleine-König --- v5: - fixed order of properties - corrected clock to two items v4: - fixed typos, added reg v3: - add description and example - merge the snps,pwm-number into this patch - rename snps,pwm to snps,dw-apb-timers-pwm2 v2: - fix #pwm-cells to be 3 - fix indentation and ordering issues --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..9aabdb373afa --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + pwm: pwm@180000 { + compatible = "snps,dw-apb-timers-pwm2"; + reg = <0x180000 0x200>; + #pwm-cells = <3>; + clocks = <&bus>, <&timer>; + clock-names = "bus", "timer"; + }; From patchwork Fri Dec 23 15:38:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3324BC4708D for ; Fri, 23 Dec 2022 15:38:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236409AbiLWPi3 (ORCPT ); Fri, 23 Dec 2022 10:38:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230124AbiLWPi1 (ORCPT ); Fri, 23 Dec 2022 10:38:27 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9A2937F8F for ; Fri, 23 Dec 2022 07:38:26 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id w15so4892152wrl.9 for ; Fri, 23 Dec 2022 07:38:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LaKMC7NJJS8Y0MMlr5K0QsyzZJpC85cOVEafIt4Qty0=; b=V1l553I7oXg2C4qHnYmFpqG503sjIbNgnxto6sYHsaO6xODmi2RhQG3hUeJIQMhxil ienlHVx59OcUQoZAFPhXm0SvnJzf4HPu05gMUSEw18ld1kIqzuyQUxq+xZZWx7xlC+rz yNhsjYUMEzQHfyAHBaYRj1ReZWj+ldX8KfK0aJwMXEQ7UVT77SNAI6YkyfbsznrceyuY u55Q0IsrCnclU7f+E+N6Hfrwz9eLkG6yn0sviThtmL7YuPys4HJmiNTRpW31SopmUxSZ 0JBZrrxWaEfiq8QFob3Ba27uPL+xK4p13H3SoiBwORvRyC2RAwqRBq1+7o6QBy+6U4HF 1NAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LaKMC7NJJS8Y0MMlr5K0QsyzZJpC85cOVEafIt4Qty0=; b=P1CFXy9xTSIp7PKP3Ew5sFnbuzMV+0peJAmIi8sGZRW2JnI7e0g+AbwqKAHgA4nSdh VebTMDnPuvU0unuOi8jStzFTPz0fFbg9M70dIabZrCSceFuYwiFgrXmJIHMMkC2g4jmt SCF+iYk9su694qcqHBX/ds7E7W6V6T9Qs/yBnottEsTd25vSa6bKRijnOtqvgB6UXPzp //W+kSJ1tUFdQ55gnILPf1aXfsR9DTpXW1rEptmWhVaYHWVQanSmGjxYAArLen3/M5vq DQKQEYz8K3YdHnZmEtC5ov7CubYZTuerwqaoGBlvFWc2nSidT+wGVk6kwy2DiKeBBmQ0 4n4g== X-Gm-Message-State: AFqh2krchNNbvOfHNYZAIfjDvTANHb9PCFqP4YfYxrsb6v53U52Bu1Iy OkygevuEhG/g1/OrnPaLEd3/Wg== X-Google-Smtp-Source: AMrXdXtsOoK7IIaJwi0rQ/Qg1U1ANupeWnCz12A+frhdNo1KNGXo1GQqy7SEtL7EEzLMqGDMLwRHAA== X-Received: by 2002:a5d:46c3:0:b0:242:404c:2039 with SMTP id g3-20020a5d46c3000000b00242404c2039mr6729654wrs.34.1671809905358; Fri, 23 Dec 2022 07:38:25 -0800 (PST) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:25 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 02/10] pwm: dwc: allow driver to be built with COMPILE_TEST Date: Fri, 23 Dec 2022 15:38:12 +0000 Message-Id: <20221223153820.404565-3-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow dwc driver to be built with COMPILE_TEST should allow better coverage when build testing. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-König --- v4: - moved to earlier in the series v3: - add HAS_IOMEM depdency for compile testing --- drivers/pwm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..3f3c53af4a56 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,7 +176,8 @@ config PWM_CROS_EC config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI + depends on PCI || COMPILE_TEST + depends on HAS_IOMEM help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:25 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 03/10] pwm: dwc: change &pci->dev to dev in probe Date: Fri, 23 Dec 2022 15:38:13 +0000 Message-Id: <20221223153820.404565-4-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dwc_pwm_probe() assignes dev to be &pci->dev but then uses &pci->dev throughout the function. Change these all to the be 'dev' variable to make lines shorter. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 7568300bb11e..c706ef9a7ba1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -202,14 +202,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL); + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; ret = pcim_enable_device(pci); if (ret) { - dev_err(&pci->dev, - "Failed to enable device (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); return ret; } @@ -217,14 +216,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); if (ret) { - dev_err(&pci->dev, - "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); return ret; } dwc->base = pcim_iomap_table(pci)[0]; if (!dwc->base) { - dev_err(&pci->dev, "Base address missing\n"); + dev_err(dev, "Base address missing\n"); return -ENOMEM; } From patchwork Fri Dec 23 15:38:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01497C3DA79 for ; Fri, 23 Dec 2022 15:38:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236504AbiLWPic (ORCPT ); Fri, 23 Dec 2022 10:38:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236418AbiLWPia (ORCPT ); Fri, 23 Dec 2022 10:38:30 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89B1937FB2 for ; Fri, 23 Dec 2022 07:38:28 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id co23so4907580wrb.4 for ; Fri, 23 Dec 2022 07:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3SdKoJam1KKdYl+ZS8hBn9qpHaB89KQkUoXzOnMw6QQ=; b=eMHE3ifyHwq7DBESvLs+KwGR2m0Y40+X3Frl1shhGCohSAXv3eveeNglOqp/4TzAXC HIQBR+9yfIwDQtGvmwVXNW/Fb5xLL6AAfyrC3OawLdGZFzhi7lGFGN8nCRCQ3OYRho5/ 6BpkpttCeD+Js59R0Uf71Ug8omMmf3aN8X6YVDax81g08TBALpsqOUW0ZjoLjpMgrNXS PT7d4YYAVmply/EjKxv6AX8D0+fXoTKNRTCh8kxJJaouL/pEphMi4CqDzgHHomDKiihB HOT9UHEAsMmIZK1DqeBCkhWVrIcxBRNxb2Zcp3Sa1UWtszTfBH7t20+LIJuf1aTqLGg/ EVvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3SdKoJam1KKdYl+ZS8hBn9qpHaB89KQkUoXzOnMw6QQ=; b=xvM31iKvLBFG5l7L7mkj7vs63YgfRyBXMgQZoo7tL4248x6V9zn0YofNzPnyct/j7h BHmzQrGt+e0/hTvifhuW11o7JNfk19p2bKkX7xNto7NAeNga50/j/vi6ie8luE3hRz3z jtcXHkWJXHAwdKMjzEgW0raOid8w5oj2jEykBgUl8iGbyagId74ybBrRFd3fI1ixVwi7 skmQ90SpeL9dvcLQgSCzUGYUC25Lk+LmS2JyGfs6ibNW+o99878+baSFCMK2HYNMdX3b V67NGbl9/gPa2CCbUGsKHVU8sYRJ+kp6oMI4VZ8Zo+TDYR6czwyRx6BZAzbzNqtw7N+W HRBg== X-Gm-Message-State: AFqh2kq2psObazd43SR1/qbDQndA7I6IWw6ib512Z+TkCCFOP8OoeyXM EfqieurlUa0g4OnfEBv1yY/yMg== X-Google-Smtp-Source: AMrXdXv/HH3IlYJcA2aohjbZtgVWaSs3osRL51qncwx+0JP9cfrmd0SKMNjjQA30LiRZy3yixwncDQ== X-Received: by 2002:a05:6000:70a:b0:263:542c:5918 with SMTP id bs10-20020a056000070a00b00263542c5918mr7163867wrb.38.1671809907080; Fri, 23 Dec 2022 07:38:27 -0800 (PST) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:26 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 04/10] pwm: dwc: move memory alloc to own function Date: Fri, 23 Dec 2022 15:38:14 +0000 Message-Id: <20221223153820.404565-5-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation for adding other bus support, move the allocation of the pwm struct out of the main driver code. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index c706ef9a7ba1..61f11e0a9319 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -196,13 +196,29 @@ static const struct pwm_ops dwc_pwm_ops = { .owner = THIS_MODULE, }; +static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev = dev; + dwc->chip.ops = &dwc_pwm_ops; + dwc->chip.npwm = DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} + static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) { struct device *dev = &pci->dev; struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + dwc = dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; @@ -226,12 +242,6 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - pci_set_drvdata(pci, dwc); - - dwc->chip.dev = dev; - dwc->chip.ops = &dwc_pwm_ops; - dwc->chip.npwm = DWC_TIMERS_TOTAL; - ret = pwmchip_add(&dwc->chip); if (ret) return ret; From patchwork Fri Dec 23 15:38:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636430 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCA81C4167B for ; Fri, 23 Dec 2022 15:38:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236477AbiLWPib (ORCPT ); Fri, 23 Dec 2022 10:38:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236400AbiLWPi3 (ORCPT ); Fri, 23 Dec 2022 10:38:29 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5741A37F9C for ; Fri, 23 Dec 2022 07:38:28 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id l10so1494583wrv.7 for ; Fri, 23 Dec 2022 07:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=62ZS7JkYul2m8VHv1f4RSJBR/i75r0mH9YhXsFCm5ng=; b=kkNBCyTDnoMYXmE+0z0ruJGNOmPedCYqRQg9Z2I2JpHduRO843zCdWs9Vio4cgOBw8 71h1Cvoyr+Z/YAM6n+4vvf+gYit3f0ffbrqKPs++M7j47yE7tKJ3nW+FVmn2jXOuaIi3 TjVYYo1ZWSGkuLdvZDStRP2MiDt0DsGFzS7ald0dbMv2sAAjNQ60aCyjyQYZ+q9pokpS VNrbxnVU0BJfq8+nmJ3nSkTt8FoUUffj5xNVLA2XoQW3WtJpQIeZ0FPO1eU1RXsyUy12 0IQh07jo6D7zREz/vJ8EzeVI5tkztX3ndIotAOfE2TzQF8ZLBwIc6E2VSV3I3JkdiHF9 o+gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=62ZS7JkYul2m8VHv1f4RSJBR/i75r0mH9YhXsFCm5ng=; b=eqJYljaiY2LedjWvZlNlMo/3gxXZWQywzc67HIBmGjdQR4P32v0nUh43NS+unUixvy hgUBelL7SkXgYmJCab+I6WWyIvDhuiBbIJ6R+rfmLsjRNIgtEP08Rff//7yPHBNPLhvc 71vEikms983Hi1QHbJBnndHfJHE8Wfq32KXulk7Ur6yi+7I6iUx26StPKbZaQUpY8bo9 /+JdDoy2GVUvIgryok0EfW2e7nxHqg2eRO9NEUZBd2Ew06fZ/SwzWg9LDvqg/VFaoVvn g4+dfUlgzsuMG17HeMvCAo7RkA78BTUTeLUg3toccqWfa33K8SxcjovgESLC8EHaBZZG L4mA== X-Gm-Message-State: AFqh2kqZipM4p3hHpXIqg/YEI4rQOjimxRh6/swETlT2nfE1At7MYlYw mZHVcktHC0sgJ8XxH8D2hQGAfw== X-Google-Smtp-Source: AMrXdXuez67Czj0Gg1F7GnS0247uGtRGqJzpwsoZyvsWa1w5xuXBq2EhWRarnlCIkdwMsdLAe6yQdg== X-Received: by 2002:a5d:58fc:0:b0:242:7f6e:9192 with SMTP id f28-20020a5d58fc000000b002427f6e9192mr6618305wrd.52.1671809907978; Fri, 23 Dec 2022 07:38:27 -0800 (PST) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:27 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 05/10] pwm: dwc: use devm_pwmchip_add Date: Fri, 23 Dec 2022 15:38:15 +0000 Message-Id: <20221223153820.404565-6-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use devm_pwmchip_add() to add the pwm chip to avoid having to manually remove it (useful for the next patch which adds the platform-device support). Signed-off-by: Ben Dooks Reviewed-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 61f11e0a9319..56cde9da2c0e 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -242,7 +242,7 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - ret = pwmchip_add(&dwc->chip); + ret = devm_pwmchip_add(dev, &dwc->chip); if (ret) return ret; @@ -254,12 +254,8 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) static void dwc_pwm_remove(struct pci_dev *pci) { - struct dwc_pwm *dwc = pci_get_drvdata(pci); - pm_runtime_forbid(&pci->dev); pm_runtime_get_noresume(&pci->dev); - - pwmchip_remove(&dwc->chip); } #ifdef CONFIG_PM_SLEEP From patchwork Fri Dec 23 15:38:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4496C3DA79 for ; Fri, 23 Dec 2022 15:38:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236467AbiLWPil (ORCPT ); Fri, 23 Dec 2022 10:38:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236499AbiLWPib (ORCPT ); Fri, 23 Dec 2022 10:38:31 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57B5844958 for ; Fri, 23 Dec 2022 07:38:30 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id bs20so2799550wrb.3 for ; Fri, 23 Dec 2022 07:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CPH/M1In5tZiaCGNrlAGn5CCO6XSXCQRQXthkDBcqi0=; b=NeKzld304lre/CyfiM+FMjHdDsxPfjJ+t+nYAv7Q1sUtZ8MJXo5mT+7bW0Udb5p27B 2AKsKEfWsyRSfAAMuG/LM03sftGwWpdSMKD88o2XkY+kSpBT4pKAFrBEw+X6qqGwrqge yqI08deVU6sMfpweKKBYs+fLX7hS82IVvqCLNLxgd4g1X2StAhLPOexOj+8LcbolYAGt SiyA/deOaOvYh28udrJFgCdGHEJEC3cOZVaL9KeuMy9Utg3bqsO+xl421+XZwKWdUC7C 1tfB5szKJlHfXpOS9MUkyXwSnrXZAEgVgz7i1oTHxYv5W3EG/i6i6En+kISVFcjJGeNp 8vFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CPH/M1In5tZiaCGNrlAGn5CCO6XSXCQRQXthkDBcqi0=; b=G1lrS0hH1737k24OgmV8hOTDMC1xWHp7RapLUbR5MoftfOAAnpOKMmkJdGe5NLuE/e TgZxx/BXi8qRaL7wLXw2S/0YBhMUJyqAe83FT464LjtB4fttOWlSqWlr9/jQdw1fxi/p LXGkzWY3uIIVu+xyCWttpr8/hugJm9CglLfVNkIdnTmYMPIHH9/HnGthh1Ikn8192y5P N5t4fGZ6t+F6vnynN6TbWN8zzApOlVFfk6FHb/07m9hQy4iBSf/5asvVgqOLe7tdGOd8 jdCgmgiiAdjCcbSWEWrmANoY2nvpPWADOzlP7GQI1c++YooTlG8j1e9F4mVwdQpa/DSs CaKw== X-Gm-Message-State: AFqh2kq0gJ6ze+sIRk93EOrjRRa01EoqeiW2nF+Hmx9LukZ8MJy0cUxC X72eBq3m3MJWh4ZNjk2tPj0HmA== X-Google-Smtp-Source: AMrXdXv4dtOzvGj0dofL5UE0QvvGfpdaTEyMLYhJcfiS7lkiYB8O33l6V5AQr7BF4M6DjXYRNyQckg== X-Received: by 2002:adf:e68e:0:b0:242:46f1:1d90 with SMTP id r14-20020adfe68e000000b0024246f11d90mr6456901wrm.64.1671809908862; Fri, 23 Dec 2022 07:38:28 -0800 (PST) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:28 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 06/10] pwm: dwc: split pci out of core driver Date: Fri, 23 Dec 2022 15:38:16 +0000 Message-Id: <20221223153820.404565-7-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Moving towards adding non-pci support for the driver, move the pci parts out of the core into their own module. This is partly due to the module_driver() code only being allowed once in a module and also to avoid a number of #ifdef if we build a single file in a system without pci support. Signed-off-by: Ben Dooks --- v7: - re-order kconfig to make dwc core be selected by PCI driver v6: - put DWC_PERIOD_NS back to avoid bisect issues v4: - removed DWC_PERIOD_NS as not needed --- drivers/pwm/Kconfig | 17 +++- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-pci.c | 133 ++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 158 +------------------------------------- drivers/pwm/pwm-dwc.h | 58 ++++++++++++++ 5 files changed, 209 insertions(+), 158 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-pci.c create mode 100644 drivers/pwm/pwm-dwc.h diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3f3c53af4a56..8c5ef388a981 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -174,16 +174,25 @@ config PWM_CROS_EC PWM driver for exposing a PWM attached to the ChromeOS Embedded Controller. -config PWM_DWC - tristate "DesignWare PWM Controller" - depends on PCI || COMPILE_TEST +config PWM_DWC_CORE + tristate depends on HAS_IOMEM help - PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + PWM driver for Synopsys DWC PWM Controller. To compile this driver as a module, choose M here: the module will be called pwm-dwc. +config PWM_DWC + tristate "DesignWare PWM Controller (PCI bus)" + depends on HAS_IOMEM && PCI + select PWM_DWC_CORE + help + PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-pci. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..a70d36623129 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) += pwm-dwc.o +obj-$(CONFIG_PWM_DWC_PCI) += pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c new file mode 100644 index 000000000000..2213d0e7f3c8 --- /dev/null +++ b/drivers/pwm/pwm-dwc-pci.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver (PCI part) + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + * + * Limitations: + * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low + * periods are one or more input clock periods long. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) +{ + struct device *dev = &pci->dev; + struct dwc_pwm *dwc; + int ret; + + dwc = dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + ret = pcim_enable_device(pci); + if (ret) { + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); + return ret; + } + + pci_set_master(pci); + + ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); + if (ret) { + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + return ret; + } + + dwc->base = pcim_iomap_table(pci)[0]; + if (!dwc->base) { + dev_err(dev, "Base address missing\n"); + return -ENOMEM; + } + + ret = devm_pwmchip_add(dev, &dwc->chip); + if (ret) + return ret; + + pm_runtime_put(dev); + pm_runtime_allow(dev); + + return 0; +} + +static void dwc_pwm_remove(struct pci_dev *pci) +{ + pm_runtime_forbid(&pci->dev); + pm_runtime_get_noresume(&pci->dev); +} + +#ifdef CONFIG_PM_SLEEP +static int dwc_pwm_suspend(struct device *dev) +{ + struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc = pci_get_drvdata(pdev); + int i; + + for (i = 0; i < DWC_TIMERS_TOTAL; i++) { + if (dwc->chip.pwms[i].state.enabled) { + dev_err(dev, "PWM %u in use by consumer (%s)\n", + i, dwc->chip.pwms[i].label); + return -EBUSY; + } + dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); + dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); + dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); + } + + return 0; +} + +static int dwc_pwm_resume(struct device *dev) +{ + struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc = pci_get_drvdata(pdev); + int i; + + for (i = 0; i < DWC_TIMERS_TOTAL; i++) { + dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); + +static const struct pci_device_id dwc_pwm_id_table[] = { + { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ + { } /* Terminating Entry */ +}; +MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); + +static struct pci_driver dwc_pwm_driver = { + .name = "pwm-dwc", + .probe = dwc_pwm_probe, + .remove = dwc_pwm_remove, + .id_table = dwc_pwm_id_table, + .driver = { + .pm = &dwc_pwm_pm_ops, + }, +}; + +module_pci_driver(dwc_pwm_driver); + +MODULE_AUTHOR("Felipe Balbi (Intel)"); +MODULE_AUTHOR("Jarkko Nikula "); +MODULE_AUTHOR("Raymond Tan "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 56cde9da2c0e..90a8ae1252a1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -1,16 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * DesignWare PWM Controller driver + * DesignWare PWM Controller driver core * * Copyright (C) 2018-2020 Intel Corporation * * Author: Felipe Balbi (Intel) * Author: Jarkko Nikula * Author: Raymond Tan - * - * Limitations: - * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low - * periods are one or more input clock periods long. */ #include @@ -21,51 +17,7 @@ #include #include -#define DWC_TIM_LD_CNT(n) ((n) * 0x14) -#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) -#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) -#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) -#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) -#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) - -#define DWC_TIMERS_INT_STS 0xa0 -#define DWC_TIMERS_EOI 0xa4 -#define DWC_TIMERS_RAW_INT_STS 0xa8 -#define DWC_TIMERS_COMP_VERSION 0xac - -#define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 - -/* Timer Control Register */ -#define DWC_TIM_CTRL_EN BIT(0) -#define DWC_TIM_CTRL_MODE BIT(1) -#define DWC_TIM_CTRL_MODE_FREE (0 << 1) -#define DWC_TIM_CTRL_MODE_USER (1 << 1) -#define DWC_TIM_CTRL_INT_MASK BIT(2) -#define DWC_TIM_CTRL_PWM BIT(3) - -struct dwc_pwm_ctx { - u32 cnt; - u32 cnt2; - u32 ctrl; -}; - -struct dwc_pwm { - struct pwm_chip chip; - void __iomem *base; - struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; -}; -#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) - -static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) -{ - return readl(dwc->base + offset); -} - -static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) -{ - writel(value, dwc->base + offset); -} +#include "pwm-dwc.h" static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) { @@ -196,7 +148,7 @@ static const struct pwm_ops dwc_pwm_ops = { .owner = THIS_MODULE, }; -static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +struct dwc_pwm *dwc_pwm_alloc(struct device *dev) { struct dwc_pwm *dwc; @@ -211,109 +163,7 @@ static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) dev_set_drvdata(dev, dwc); return dwc; } - -static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) -{ - struct device *dev = &pci->dev; - struct dwc_pwm *dwc; - int ret; - - dwc = dwc_pwm_alloc(dev); - if (!dwc) - return -ENOMEM; - - ret = pcim_enable_device(pci); - if (ret) { - dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); - return ret; - } - - pci_set_master(pci); - - ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); - if (ret) { - dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); - return ret; - } - - dwc->base = pcim_iomap_table(pci)[0]; - if (!dwc->base) { - dev_err(dev, "Base address missing\n"); - return -ENOMEM; - } - - ret = devm_pwmchip_add(dev, &dwc->chip); - if (ret) - return ret; - - pm_runtime_put(dev); - pm_runtime_allow(dev); - - return 0; -} - -static void dwc_pwm_remove(struct pci_dev *pci) -{ - pm_runtime_forbid(&pci->dev); - pm_runtime_get_noresume(&pci->dev); -} - -#ifdef CONFIG_PM_SLEEP -static int dwc_pwm_suspend(struct device *dev) -{ - struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc = pci_get_drvdata(pdev); - int i; - - for (i = 0; i < DWC_TIMERS_TOTAL; i++) { - if (dwc->chip.pwms[i].state.enabled) { - dev_err(dev, "PWM %u in use by consumer (%s)\n", - i, dwc->chip.pwms[i].label); - return -EBUSY; - } - dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); - dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); - dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); - } - - return 0; -} - -static int dwc_pwm_resume(struct device *dev) -{ - struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc = pci_get_drvdata(pdev); - int i; - - for (i = 0; i < DWC_TIMERS_TOTAL; i++) { - dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); - } - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); - -static const struct pci_device_id dwc_pwm_id_table[] = { - { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ - { } /* Terminating Entry */ -}; -MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); - -static struct pci_driver dwc_pwm_driver = { - .name = "pwm-dwc", - .probe = dwc_pwm_probe, - .remove = dwc_pwm_remove, - .id_table = dwc_pwm_id_table, - .driver = { - .pm = &dwc_pwm_pm_ops, - }, -}; - -module_pci_driver(dwc_pwm_driver); +EXPORT_SYMBOL_GPL(dwc_pwm_alloc); MODULE_AUTHOR("Felipe Balbi (Intel)"); MODULE_AUTHOR("Jarkko Nikula "); diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h new file mode 100644 index 000000000000..68f98eb76152 --- /dev/null +++ b/drivers/pwm/pwm-dwc.h @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ + +#define DWC_TIM_LD_CNT(n) ((n) * 0x14) +#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) +#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) +#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) +#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) +#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) + +#define DWC_TIMERS_INT_STS 0xa0 +#define DWC_TIMERS_EOI 0xa4 +#define DWC_TIMERS_RAW_INT_STS 0xa8 +#define DWC_TIMERS_COMP_VERSION 0xac + +#define DWC_TIMERS_TOTAL 8 +#define DWC_CLK_PERIOD_NS 10 + +/* Timer Control Register */ +#define DWC_TIM_CTRL_EN BIT(0) +#define DWC_TIM_CTRL_MODE BIT(1) +#define DWC_TIM_CTRL_MODE_FREE (0 << 1) +#define DWC_TIM_CTRL_MODE_USER (1 << 1) +#define DWC_TIM_CTRL_INT_MASK BIT(2) +#define DWC_TIM_CTRL_PWM BIT(3) + +struct dwc_pwm_ctx { + u32 cnt; + u32 cnt2; + u32 ctrl; +}; + +struct dwc_pwm { + struct pwm_chip chip; + void __iomem *base; + struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; +}; +#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) + +static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) +{ + return readl(dwc->base + offset); +} + +static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) +{ + writel(value, dwc->base + offset); +} + +extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev); From patchwork Fri Dec 23 15:38:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5A6CC4332F for ; Fri, 23 Dec 2022 15:38:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236530AbiLWPik (ORCPT ); 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:29 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 07/10] pwm: dwc: make timer clock configurable Date: Fri, 23 Dec 2022 15:38:17 +0000 Message-Id: <20221223153820.404565-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks Reviewed-by: Uwe Kleine-König --- v7: - remove the "struct clk *" clk field from dwc_pwm_ctx, not used here, v6: - removed DWC_CLK_PERIOD_NS as it is now not needed v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc.c | 9 +++++---- drivers/pwm/pwm-dwc.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 90a8ae1252a1..0c6beafa8c41 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -47,13 +47,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -128,12 +128,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty += 1; - duty *= DWC_CLK_PERIOD_NS; + duty *= dwc->clk_ns; state->duty_cycle = duty; period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period += 1; - period *= DWC_CLK_PERIOD_NS; + period *= dwc->clk_ns; period += duty; state->period = period; @@ -156,6 +156,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; + dwc->clk_ns = 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 68f98eb76152..b29d8cd21208 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -22,7 +22,6 @@ #define DWC_TIMERS_COMP_VERSION 0xac #define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 /* Timer Control Register */ #define DWC_TIM_CTRL_EN BIT(0) @@ -41,6 +40,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + unsigned int clk_ns; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) From patchwork Fri Dec 23 15:38:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB36FC4332F for ; Fri, 23 Dec 2022 15:38:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236553AbiLWPir (ORCPT ); Fri, 23 Dec 2022 10:38:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236440AbiLWPif (ORCPT ); Fri, 23 Dec 2022 10:38:35 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2243D4497D for ; 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:30 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 08/10] pwm: dwc: add of/platform support Date: Fri, 23 Dec 2022 15:38:18 +0000 Message-Id: <20221223153820.404565-9-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dwc pwm controller can be used in non-PCI systems, so allow either platform or OF based probing. Signed-off-by: Ben Dooks --- v7: - fixup kconfig from previous pcie changes v5: - fix missing " in kconfig - remove .remove method, devm already sorts this. - merge pwm-number code - split the of code out of the core - get bus clock v4: - moved the compile test code earlier - fixed review comments - used NS_PER_SEC - use devm_clk_get_enabled - ensure we get the bus clock v3: - changed compatible name fixup add pwm/Kconfig fixup: kconfig change for of addition --- drivers/pwm/Kconfig | 10 ++++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-of.c | 76 +++++++++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc-pci.c | 1 + drivers/pwm/pwm-dwc.c | 1 + drivers/pwm/pwm-dwc.h | 1 + 6 files changed, 90 insertions(+) create mode 100644 drivers/pwm/pwm-dwc-of.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8c5ef388a981..74ab526e8b8c 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -193,6 +193,16 @@ config PWM_DWC To compile this driver as a module, choose M here: the module will be called pwm-dwc-pci. +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus)" + depends on HAS_IOMEM && OF + select PWM_DWC_CORE + help + PWM driver for Synopsys DWC PWM Controller on an OF bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index a70d36623129..d1fd1641f077 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) += pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) += pwm-dwc-of.o obj-$(CONFIG_PWM_DWC_PCI) += pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c new file mode 100644 index 000000000000..c5b4351cc7b0 --- /dev/null +++ b/drivers/pwm/pwm-dwc-of.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver OF + * + * Copyright (C) 2022 SiFive, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwc_pwm *dwc; + struct clk *bus; + u32 nr_pwm; + + dwc = dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs (%d) specified, capping at %d\n", + nr_pwm, dwc->chip.npwm); + else + dwc->chip.npwm = nr_pwm; + } + + dwc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return PTR_ERR(dwc->base); + + bus = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(bus)) + return dev_err_probe(dev, PTR_ERR(bus), + "failed to get clock\n"); + + dwc->clk = devm_clk_get_enabled(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + dwc->clk_ns = NSEC_PER_SEC / clk_get_rate(dwc->clk); + return devm_pwmchip_add(dev, &dwc->chip); +} + +static const struct of_device_id dwc_pwm_dt_ids[] = { + { .compatible = "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver = { + .driver = { + .name = "dwc-pwm", + .of_match_table = dwc_pwm_dt_ids, + }, + .probe = dwc_pwm_plat_probe, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm-of"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c index 2213d0e7f3c8..949423e368f9 100644 --- a/drivers/pwm/pwm-dwc-pci.c +++ b/drivers/pwm/pwm-dwc-pci.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "pwm-dwc.h" diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 0c6beafa8c41..1251620ab771 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index b29d8cd21208..dc451cb2eff5 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -40,6 +40,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + struct clk *clk; unsigned int clk_ns; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; From patchwork Fri Dec 23 15:38:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DCC0C3DA79 for ; Fri, 23 Dec 2022 15:38:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236543AbiLWPip (ORCPT ); Fri, 23 Dec 2022 10:38:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236508AbiLWPif (ORCPT ); Fri, 23 Dec 2022 10:38:35 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5C8244977 for ; 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:31 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 09/10] pwm: dwc: add PWM bit unset in get_state call Date: Fri, 23 Dec 2022 15:38:19 +0000 Message-Id: <20221223153820.404565-10-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 1251620ab771..5ef0fe7ea3e9 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -121,23 +121,30 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, { struct dwc_pwm *dwc = to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; pm_runtime_get_sync(chip->dev); - state->enabled = !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty += 1; - duty *= dwc->clk_ns; - state->duty_cycle = duty; + state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); - period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period += 1; - period *= dwc->clk_ns; - period += duty; - state->period = period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty = (ld + 1) * dwc->clk_ns; + period = (ld2 + 1) * dwc->clk_ns; + period += duty; + } else { + duty = (ld + 1) * dwc->clk_ns; + period = duty * 2; + } + state->period = period; + state->duty_cycle = duty; state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev); From patchwork Fri Dec 23 15:38:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 636427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BE58C46467 for ; Fri, 23 Dec 2022 15:38:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236513AbiLWPiu (ORCPT ); Fri, 23 Dec 2022 10:38:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236516AbiLWPij (ORCPT ); Fri, 23 Dec 2022 10:38:39 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13FA46646 for ; Fri, 23 Dec 2022 07:38:32 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id i7so4890478wrv.8 for ; Fri, 23 Dec 2022 07:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MuQJZUiYgsrv6ydPrE/ryH64TRoc2yWi4dM3ARWJNR4=; b=RTjhswt+6tiiYquqWIf1Bv153VnSU5lDEY/YBSphlnlos0M3DB13yo7Hh+2JH2ey+Y 1Ymok9XvOR/yPOU0DYRS5sk8YHSlt6OBr9V3sCmo8ujrt6odD5XcgfuoUzb9+BBU/iZd AgFVwYFMQWZUWh4OGWuCgczBV3lRP+qNQSHciNEps3oi4wSyxKE1Hku5Xq/XJsq1wqVg KZJvbjVHNElq3pyjVIF5WJjtUEizlrUOrf/M/cXR2296ja2hQget+VGe1YJ8sIHnzSUy FVswQmXyWDODAv2PevUwlny7tYq4kJP8sQiyc4UQjba38d9U4qXJtndmu2UAvOYWu1m2 MhEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MuQJZUiYgsrv6ydPrE/ryH64TRoc2yWi4dM3ARWJNR4=; b=J7H6/pbmkIsRjfcSq6A1iwNNq5t8A5zVhxavmp9ti4lh2QJ3Dsr88csgEO6mAZHim2 UEruSHuwIZZFWFcCYAnau1Y5nU8I/DjbFG1w+YyRVAnwS9E46KBuczqUG3ijO4BG6JxJ CQC2rNIXmQS+zt2mslUxlwDC7pY3yq5szq8e0Tyrp2j17/zXpOuvazw2BlipeSLZZLPL JDfJWhX4JHQtw5Kjd2nS/HAt4NecDY6+2kMLrBVegthCfmKvzk3q0Gc10qnWoIfOf4Ci h0Ds1mr9LKZFwuOrk4BnUzTLiU58QPrmfdyLJBVCjH9oWU6qU+FtcFjNJ7iqarDlE4YP /hgA== X-Gm-Message-State: AFqh2kqu0/6xeKFg3YDRlBU93cSa62m9ljA7TLbvRwvS0BieM80CIpFW Z6eG0vTxTfokREmoLRe4ZGUB/Q== X-Google-Smtp-Source: AMrXdXt+D8+ShGwprnyREr39W/oKiY2rcuXwLgfb5FfMzfQ33k2idZKt03tPoJi/+kllQcoCQDJupQ== X-Received: by 2002:a5d:470a:0:b0:242:22e4:998f with SMTP id y10-20020a5d470a000000b0024222e4998fmr6055124wrq.55.1671809912419; Fri, 23 Dec 2022 07:38:32 -0800 (PST) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id m5-20020adfc585000000b00236488f62d6sm3491610wrg.79.2022.12.23.07.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Dec 2022 07:38:32 -0800 (PST) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v7 10/10] pwm: dwc: use clock rate in hz to avoid rounding issues Date: Fri, 23 Dec 2022 15:38:20 +0000 Message-Id: <20221223153820.404565-11-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221223153820.404565-1-ben.dooks@sifive.com> References: <20221223153820.404565-1-ben.dooks@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As noted, the clock-rate when not a nice multiple of ns is probably going to end up with inacurate caculations, as well as on a non pci system the rate may change (although we've not put a clock rate change notifier in this code yet) so we also add some quick checks of the rate when we do any calculations with it. Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc-of.c | 2 +- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c index c5b4351cc7b0..5f7f066859d4 100644 --- a/drivers/pwm/pwm-dwc-of.c +++ b/drivers/pwm/pwm-dwc-of.c @@ -50,7 +50,7 @@ static int dwc_pwm_plat_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(dwc->clk), "failed to get timer clock\n"); - dwc->clk_ns = NSEC_PER_SEC / clk_get_rate(dwc->clk); + dwc->clk_rate = clk_get_rate(dwc->clk); return devm_pwmchip_add(dev, &dwc->chip); } diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 5ef0fe7ea3e9..f48a6245a3b5 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -43,18 +43,22 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, u32 high; u32 low; + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); + /* * Calculate width of low and high period in terms of input clock * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp = state->duty_cycle * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; - tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp = (state->period - state->duty_cycle) * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -120,6 +124,7 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc = to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; @@ -129,22 +134,28 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); + + clk_rate = dwc->clk_rate; state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); /* If we're not in PWM, technically the output is a 50-50 * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty = (ld + 1) * dwc->clk_ns; - period = (ld2 + 1) * dwc->clk_ns; + duty = ld + 1; + period = ld2 + 1; period += duty; } else { - duty = (ld + 1) * dwc->clk_ns; + duty = ld + 1; period = duty * 2; } - state->period = period; - state->duty_cycle = duty; + duty *= NSEC_PER_SEC; + period *= NSEC_PER_SEC; + state->period = DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev); @@ -164,7 +175,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; - dwc->clk_ns = 10; + dwc->clk_rate = NSEC_PER_SEC / 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index dc451cb2eff5..19bdc2224690 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -41,7 +41,7 @@ struct dwc_pwm { struct pwm_chip chip; void __iomem *base; struct clk *clk; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))