From patchwork Thu Dec 29 20:04:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 638059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E47AC3DA79 for ; Thu, 29 Dec 2022 20:04:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230458AbiL2UEy (ORCPT ); Thu, 29 Dec 2022 15:04:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229598AbiL2UEx (ORCPT ); Thu, 29 Dec 2022 15:04:53 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3CF014D19 for ; Thu, 29 Dec 2022 12:04:51 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id h7-20020a17090aa88700b00225f3e4c992so11255680pjq.1 for ; Thu, 29 Dec 2022 12:04:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=THu9QMNuJA2VLaqG7RBOupd/FwlnEsHSPzLMTF3bhmM=; b=E+kP4To4Zqmzj4VnzgJ7fPeHfDNzUJ5kN99ndY4qRVSFbjiMwEBPI0CMuh5MA9ITBZ Lo6LeHpg8JxUxDp+pO+NFqh1DHjCHvP4cytZpfyuC7zp/lxvftZZuACyM4B08QArfUzx a1+UHy8ikaWM2TrhR4qSGZvAuWh+9KvMhlynA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=THu9QMNuJA2VLaqG7RBOupd/FwlnEsHSPzLMTF3bhmM=; b=r1YfzbKnuyKhXPk3DGakz5qFbWk+hMUfx6x2MIkEH5Fp1MU2F4xiF/MiPGOhowX4FY DogQqq4vmMSZUd0+5p/wJTMU0HdvFOvl8kb35sO+aMPWQLC0sbrqHK6AWBfR2knOnNXy MdQUXPh1ptWsEFvNeUGDhhOmgLlx0eVE851xVx+8xSr0ePEJQ1kw3HyMAEhroMy2YYcL HDb+bQqm/R91EOWH2ZwwareLpPBqeBVE5LL/zD5yse0zKUzI4N+w8F+kPyiTPOMFRfpu 4sNWuzZCjDsF2stzNECGi/oo2XtVyKvjgUtA+plVbRX9Ldi9I5dN1xteo9ZhKbm3tHHY B6Dg== X-Gm-Message-State: AFqh2kqWodnF+aAMQfNMZuZ/ZyoObA0ZUancLOIN7WreZ0/84NmY/xVl alDUFxz205fafQQiIEgH8TiYpA== X-Google-Smtp-Source: AMrXdXuXmlyeuQYOw90K/c3dIQQ7TFZ/gllINgDBn4Z8lOCzZ0Nd+Wwljgg+hiODBHHeoT5T6huhzQ== X-Received: by 2002:a17:902:c10a:b0:188:bc62:276f with SMTP id 10-20020a170902c10a00b00188bc62276fmr31841494pli.3.1672344291243; Thu, 29 Dec 2022 12:04:51 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:04:50 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v3 1/8] mmc: sdhci-pxav2: add initial support for PXA168 V1 controller Date: Thu, 29 Dec 2022 12:04:04 -0800 Message-Id: <20221229200411.295339-2-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a new compatible string for the version 1 controller used in the PXA168, along with necessary quirks. Use a separate ops struct in preparation for a silicon bug workaround only necessary on V1. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 40 +++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index f18906b5575f..5707d597ecae 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -101,6 +101,24 @@ static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); } +struct sdhci_pxa_variant { + const struct sdhci_ops *ops; + unsigned int extra_quirks; +}; + +static const struct sdhci_ops pxav1_sdhci_ops = { + .set_clock = sdhci_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .set_bus_width = pxav2_mmc_set_bus_width, + .reset = pxav2_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + +static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = { + .ops = &pxav1_sdhci_ops, + .extra_quirks = SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE, +}; + static const struct sdhci_ops pxav2_sdhci_ops = { .set_clock = sdhci_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, @@ -109,11 +127,14 @@ static const struct sdhci_ops pxav2_sdhci_ops = { .set_uhs_signaling = sdhci_set_uhs_signaling, }; +static const struct sdhci_pxa_variant pxav2_variant = { + .ops = &pxav2_sdhci_ops, +}; + #ifdef CONFIG_OF static const struct of_device_id sdhci_pxav2_of_match[] = { - { - .compatible = "mrvl,pxav2-mmc", - }, + { .compatible = "mrvl,pxav1-mmc", .data = &pxav1_variant, }, + { .compatible = "mrvl,pxav2-mmc", .data = &pxav2_variant, }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); @@ -157,7 +178,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; struct device *dev = &pdev->dev; struct sdhci_host *host = NULL; - const struct of_device_id *match; + const struct sdhci_pxa_variant *variant; int ret; struct clk *clk; @@ -185,10 +206,12 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; - match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev); - if (match) { + variant = of_device_get_match_data(dev); + if (variant) pdata = pxav2_get_mmc_pdata(dev); - } + else + variant = &pxav2_variant; + if (pdata) { if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { /* on-chip device */ @@ -208,7 +231,8 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) host->mmc->pm_caps |= pdata->pm_caps; } - host->ops = &pxav2_sdhci_ops; + host->quirks |= variant->extra_quirks; + host->ops = variant->ops; ret = sdhci_add_host(host); if (ret) From patchwork Thu Dec 29 20:04:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 637651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF47CC3DA7A for ; Thu, 29 Dec 2022 20:04:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233290AbiL2UE4 (ORCPT ); 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([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:04:53 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v3 2/8] mmc: sdhci-pxav2: enable CONFIG_MMC_SDHCI_IO_ACCESSORS Date: Thu, 29 Dec 2022 12:04:05 -0800 Message-Id: <20221229200411.295339-3-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable CONFIG_MMC_SDHCI_IO_ACCESSORS for the pxav2 driver. The read_w callback is needed for a silicon bug workaround in the PXA168. Signed-off-by: Doug Brown --- drivers/mmc/host/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5e19a961c34d..b9e9185c86a6 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -360,6 +360,7 @@ config MMC_SDHCI_PXAV2 depends on MMC_SDHCI_PLTFM depends on ARCH_MMP || COMPILE_TEST default CPU_PXA910 + select MMC_SDHCI_IO_ACCESSORS help This selects the Marvell(R) PXAV2 SD Host Controller. If you have a PXA9XX platform with SD Host Controller From patchwork Thu Dec 29 20:04:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 638058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF485C3DA7D for ; Thu, 29 Dec 2022 20:05:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233614AbiL2UFB (ORCPT ); Thu, 29 Dec 2022 15:05:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233560AbiL2UE6 (ORCPT ); Thu, 29 Dec 2022 15:04:58 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A57D16596 for ; Thu, 29 Dec 2022 12:04:57 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id 20so6452529plo.3 for ; Thu, 29 Dec 2022 12:04:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LwLsC88yYEr+DqM5Cbp/GViuH3X6Lo7mSbslRIXTWPU=; b=LjH2StdHqe6JYBWUWVbsuH+RmGQIbgDYNdf5tFtjGE6tljxlLRNvV6iZa8Zh8EECch 2AYa2EV/cDKNSrt0fUPHZuFJ7JmA79xHx691usBv4PJNS+Xfv2SMPJhEVwNx9KwjGqKE xzz6nDemAYTZMzKp9cGvz+JD+Q05uuDTKcGSo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LwLsC88yYEr+DqM5Cbp/GViuH3X6Lo7mSbslRIXTWPU=; b=PAHg/WfGX5iuARLTwY9KGIILzjdV95LSfFCaqRH+3GknyiS5AjDANfeHc+8U2XONEb 4xprJChZ6QM8MCvPOhLyTeGSvouDhywGGlx88WLndPWsqZZ54a7whfLOMKS3C4wS5oUx vWFXlCUnFxauer1Z8eoNof9bN6fnrP+1PxiGcn+YGEfsh4je6UyjJL3Wv2oU2aga+YE8 YSujhO8QdiPvSXOTCpqfqgLwajYBEDmQVyXjIpvQ0xY9P9+y+OsMmY8BPDZtYdwXQOA5 DBrJGne5lvH97QRjCfpYSnptQ/wh0Ba4sI24jI3TgwidEhUT0ZiMCkUtN8W61qOzHzri KkUg== X-Gm-Message-State: AFqh2kqZegU90gm/NfypWZ6/WA/BiVrZSqr6Qk7qmYePOHGAVBt1Bb3m 6xS8zQSfGbeaqcE1HYRwzHGQYg== X-Google-Smtp-Source: AMrXdXsGuQulywqUBmvyH6G+s9J9Et6wj8YN7mdwrB0SInKmC/Prto+piCu2D0/N7FjRfUHOFD3Q9g== X-Received: by 2002:a17:902:d2ce:b0:192:a4d5:55b8 with SMTP id n14-20020a170902d2ce00b00192a4d555b8mr3541205plc.52.1672344297022; Thu, 29 Dec 2022 12:04:57 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:04:56 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v3 3/8] mmc: sdhci-pxav2: add register workaround for PXA168 silicon bug Date: Thu, 29 Dec 2022 12:04:06 -0800 Message-Id: <20221229200411.295339-4-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PXA168 has a documented silicon bug that results in a data abort exception when accessing the SDHCI_HOST_VERSION register on SDH2 and SDH4 through a 16-bit read. Implement the workaround described in the errata, which performs a 32-bit read from a lower address instead. This is safe to use on all four SDH peripherals. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 5707d597ecae..5e01dab94426 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -80,6 +80,15 @@ static void pxav2_reset(struct sdhci_host *host, u8 mask) } } +static u16 pxav1_readw(struct sdhci_host *host, int reg) +{ + /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */ + if (reg == SDHCI_HOST_VERSION) + return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16; + + return readw(host->ioaddr + reg); +} + static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) { u8 ctrl; @@ -107,6 +116,7 @@ struct sdhci_pxa_variant { }; static const struct sdhci_ops pxav1_sdhci_ops = { + .read_w = pxav1_readw, .set_clock = sdhci_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = pxav2_mmc_set_bus_width, From patchwork Thu Dec 29 20:04:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 637650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60F68C46467 for ; Thu, 29 Dec 2022 20:05:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233600AbiL2UFC (ORCPT ); Thu, 29 Dec 2022 15:05:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233504AbiL2UFA (ORCPT ); Thu, 29 Dec 2022 15:05:00 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5320215F1B for ; Thu, 29 Dec 2022 12:05:00 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id o1-20020a17090a678100b00219cf69e5f0so23898842pjj.2 for ; Thu, 29 Dec 2022 12:05:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D6r2GlaNz1+YzI6wDR7hgOyWZe3jS4KnaVe8emuVcm0=; b=Jx7ayWpipJYx1V2Zz6YI+oqhOTf2hCPRcDx4+pt4+GpRUI8GjlocIDH/I55wrcAHHr a8xB3t7jUa22B4ke2tsyTwm4ssdu5FCXuOa0RRWMDZ6ioYakg652LoBKY0ONRPSTUJVu bCgq0+4w1KYw3Vu9NS+uDKc4uw452vmAUrmd8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D6r2GlaNz1+YzI6wDR7hgOyWZe3jS4KnaVe8emuVcm0=; b=ufH2Lp2mauHnCv5sIRLFe81zV8MEdRHZazRDlIiP9iuy0H8I7cXuJueJxEKsQ8aT3N xdXtVolHHpSqcRUItwSAgp/FFDM7yUfNIkA2My4q1OfJYtikzHEo/3/aCFSGL9oEkUDD 3YRqyO/0S1LkQYQsx4LS+4W89b/EnDnIqucVT6K90JWKDU2XMICvmCpDKM/6pq9fBZMD 5CmMy5Qju4QKMP1cUejJiIK5ILNikZMHcdP8LMZKp1PWsuYL9YOHTv7SBs9Hj5At5c8t QIxzyEAJ4gZRtMyHETP1fOF9vpno9sTJ+s1OlxlteOq7yraPzvxTFjcHNw0FkT8XGTBp 6koQ== X-Gm-Message-State: AFqh2koM11Qfi2Sz8k45TYSRdEu+g3qweR6hPJL2iPAZYRihyKaPNYfA 7kzT/GlJaIrTun3hHFKUVA697g== X-Google-Smtp-Source: AMrXdXt4jnO+nwqLg9k7tVFSzwfWxCncGvAMj63+hcAjF+UdoJLLIOYqMk/fR+q22DFODXF5DWdjmg== X-Received: by 2002:a17:902:e74a:b0:192:8e0b:23d3 with SMTP id p10-20020a170902e74a00b001928e0b23d3mr14138994plf.23.1672344299598; Thu, 29 Dec 2022 12:04:59 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:04:59 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v3 4/8] mmc: sdhci-pxav2: change clock name to match DT bindings Date: Thu, 29 Dec 2022 12:04:07 -0800 Message-Id: <20221229200411.295339-5-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The devicetree bindings for this driver specify that the two allowed clock names are io and core. Change this driver to look for io, but allow any name if it fails for backwards compatibility. Follow the same pattern used in sdhci-pxav3, but add support for EPROBE_DEFER. Get rid of an unnecessary pdev->dev while we're at it. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 5e01dab94426..f5c86e1ba734 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -199,16 +199,18 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); - clk = devm_clk_get(dev, "PXA-SDHCLK"); + clk = devm_clk_get(dev, "io"); + if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFER) + clk = devm_clk_get(dev, NULL); if (IS_ERR(clk)) { - dev_err(dev, "failed to get io clock\n"); ret = PTR_ERR(clk); + dev_err_probe(dev, ret, "failed to get io clock\n"); goto free; } pltfm_host->clk = clk; ret = clk_prepare_enable(clk); if (ret) { - dev_err(&pdev->dev, "failed to enable io clock\n"); + dev_err(dev, "failed to enable io clock\n"); goto free; } From patchwork Thu Dec 29 20:04:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 638057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AD56C3DA79 for ; Thu, 29 Dec 2022 20:05:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233504AbiL2UFF (ORCPT ); Thu, 29 Dec 2022 15:05:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233818AbiL2UFE (ORCPT ); Thu, 29 Dec 2022 15:05:04 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED77013EB5 for ; Thu, 29 Dec 2022 12:05:02 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id v23so20248561pju.3 for ; Thu, 29 Dec 2022 12:05:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KFjpQddF6K9jQuFhw0EZBw3KCqxEcEHNGaoCdbNy9Uw=; b=kewFcvPnmlK/daoedJ07uHcuNvIXEj8SG32nFgtaneG8Vk00S3miIVACLw+x/4+5XO HyhmjbkPjPC72TFziQuJKWLqAk5/0xEgKpvpJkKCC34lngvWsP3QXpTZlj6CswA/ZZA+ RIYvIBZvUKDbTfqAHDg9Pil8Me3L9Saj5kCFw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KFjpQddF6K9jQuFhw0EZBw3KCqxEcEHNGaoCdbNy9Uw=; b=gkGcA8erw8afmAvcwPEYMzu4tBESO/SJiIg19EG2MBT37PufJy+sX+8JlQHOxgrF/p IBSeZO0EyzMOa6jq5xw+KcROQYJ//0sAcTwZGe5HobcQ/iRmxGN3W5aymC+tdhMPYlNJ GMCB1vXeMg9ILMSi6+vkq2h5xhqKUBbA0RCq4v9EzT+/SseHC1I+hS8cyX8bKaQSQ9yb 1wvdCmFQNsVUMX17fB8+DisYGdmXPGxsgg2IUfqP9ttMzY8q0vcmqlZFzYR56btagmK3 +PemKOoQe6VpfKGcyk4ZxbfuiZnOD4rbwE6vo6cLzro+VlBvzBlbK8ZJmxlptKDtHjgA x0Tw== X-Gm-Message-State: AFqh2kpBvdPLWJJc29xT2kF+K6dp5owXIM5m1cNcyOB2+uHWXNcZc23m NBAwSHEaLLUvlDHscBbEatxOjg== X-Google-Smtp-Source: AMrXdXsRMMggph1dSmqk1DtjLX0D9GUCc0yQufbYA5KUQ3uQUn+V2j4jyqiSafsbRuz+q/xqxDV2TA== X-Received: by 2002:a17:903:12d7:b0:189:854a:fff3 with SMTP id io23-20020a17090312d700b00189854afff3mr28679184plb.23.1672344302232; Thu, 29 Dec 2022 12:05:02 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:05:01 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v3 5/8] mmc: sdhci-pxav2: add optional core clock Date: Thu, 29 Dec 2022 12:04:08 -0800 Message-Id: <20221229200411.295339-6-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ability to have an optional core clock just like the pxav3 driver. The PXA168 needs this because its SDHC controllers have separate core and io clocks that both need to be enabled. This also correctly matches the documented devicetree bindings for this driver. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index f5c86e1ba734..b10f55b478fc 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -191,7 +191,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) const struct sdhci_pxa_variant *variant; int ret; - struct clk *clk; + struct clk *clk, *clk_core; host = sdhci_pltfm_init(pdev, NULL, 0); if (IS_ERR(host)) @@ -214,6 +214,12 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) goto free; } + clk_core = devm_clk_get_optional_enabled(dev, "core"); + if (IS_ERR(clk_core)) { + dev_err_probe(dev, PTR_ERR(clk_core), "failed to enable core clock\n"); + goto disable_clk; + } + host->quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; From patchwork Thu Dec 29 20:04:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 637649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AE11C3DA79 for ; Thu, 29 Dec 2022 20:05:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233856AbiL2UFI (ORCPT ); Thu, 29 Dec 2022 15:05:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233866AbiL2UFG (ORCPT ); Thu, 29 Dec 2022 15:05:06 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88D83165A8 for ; Thu, 29 Dec 2022 12:05:05 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id m7-20020a17090a730700b00225ebb9cd01so11985078pjk.3 for ; Thu, 29 Dec 2022 12:05:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lA6khbYwNTUEkyhgFPN6yUEAH+2Z3l7izmoOYpawnMY=; b=BMMNNSCPn2qhoE9uGm4q6zrLXVMvzRWmjNRiDjcnpHxoVYmr4H+RDr5TfSgSbKSeeY CNSfknKs2ijddQagcIl9TJW/ul9xMSxhQ/Wuawj0loG7XQxjyOw3giiJF1hIXFQWq5hy 6ql18QO1JzCf5ccMtQGiUhZt0FllnANDTUGio= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lA6khbYwNTUEkyhgFPN6yUEAH+2Z3l7izmoOYpawnMY=; b=4mfTuaCJts/4LpagKQKugtimHFPIXI7WpoKCpI9zwcFVigBWp3g4h/odr51XD7053M YY61BOsHi0OA3N6octJ/eYTzCdVbjLM/kUXNXS9u9aSEeZzpiLZjhYy2hD88eam5dmfU lqYCB0Lvi7C+na5STdmO9EXmxEw+RSWTA6krUC+gHq5FB/ZJb/opBzSiTqK6ArJpNHyu wdeDFZQkUsnsJ/TizohgYbbkZpBhsM/hSRcx4Th/96VNHwf3NKOdsHZHbhamcvt37iIn MtNy2SHPHoGyJhtpjyprCeWLniu8SEtiHO9TsSH3Y6aSsJ8+1MobnM5Svtlt5gAdo5Sq Fndg== X-Gm-Message-State: AFqh2kr4UAckFwPH4zLfOXYRbgpTmM6LIyb0ncC56X+vkYOzxL3DMRNp qhf5E/MnJJABookQ7AmHXL7Dhs6C0PpA/R8TCt++Ng== X-Google-Smtp-Source: AMrXdXtDdcoBE8iBS3xNoIhIbIPoZH6cfi+bNg4YggYsyXWMRDsuQC9k3AjS032M55xFYRpLDlKSrw== X-Received: by 2002:a17:902:a510:b0:192:48d1:f06c with SMTP id s16-20020a170902a51000b0019248d1f06cmr27429481plq.35.1672344304934; Thu, 29 Dec 2022 12:05:04 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:05:04 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v3 6/8] mmc: sdhci-pxav2: add SDIO card IRQ workaround for PXA168 V1 controller Date: Thu, 29 Dec 2022 12:04:09 -0800 Message-Id: <20221229200411.295339-7-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PXA168 has a documented silicon bug that causes SDIO card IRQs to be missed. Implement the first half of the suggested workaround, which involves resetting the data port logic and issuing a dummy CMD0 to restart the clock. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 56 +++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index b10f55b478fc..10fa9de14ad4 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -41,6 +43,10 @@ #define MMC_CARD 0x1000 #define MMC_WIDTH 0x0100 +struct sdhci_pxav2_host { + struct mmc_request *sdio_mrq; +}; + static void pxav2_reset(struct sdhci_host *host, u8 mask) { struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); @@ -89,6 +95,52 @@ static u16 pxav1_readw(struct sdhci_host *host, int reg) return readw(host->ioaddr + reg); } +static u32 pxav1_irq(struct sdhci_host *host, u32 intmask) +{ + struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); + struct mmc_request *sdio_mrq; + + if (pxav2_host->sdio_mrq && (intmask & SDHCI_INT_CMD_MASK)) { + /* The dummy CMD0 for the SDIO workaround just completed */ + sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); + intmask &= ~SDHCI_INT_CMD_MASK; + sdio_mrq = pxav2_host->sdio_mrq; + pxav2_host->sdio_mrq = NULL; + mmc_request_done(host->mmc, sdio_mrq); + } + + return intmask; +} + +static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq) +{ + u16 tmp; + struct sdhci_pxav2_host *pxav2_host; + + /* If this is an SDIO command, perform errata workaround for silicon bug */ + if (mrq->cmd && !mrq->cmd->error && + (mrq->cmd->opcode == SD_IO_RW_DIRECT || + mrq->cmd->opcode == SD_IO_RW_EXTENDED)) { + /* Reset data port */ + tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL); + tmp |= 0x400; + writew(tmp, host->ioaddr + SDHCI_TIMEOUT_CONTROL); + + /* Clock is now stopped, so restart it by sending a dummy CMD0 */ + pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); + pxav2_host->sdio_mrq = mrq; + sdhci_writel(host, 0, SDHCI_ARGUMENT); + sdhci_writew(host, 0, SDHCI_TRANSFER_MODE); + sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE), + SDHCI_COMMAND); + + /* Don't finish this request until the dummy CMD0 finishes */ + return; + } + + mmc_request_done(host->mmc, mrq); +} + static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) { u8 ctrl; @@ -118,10 +170,12 @@ struct sdhci_pxa_variant { static const struct sdhci_ops pxav1_sdhci_ops = { .read_w = pxav1_readw, .set_clock = sdhci_set_clock, + .irq = pxav1_irq, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = pxav2_mmc_set_bus_width, .reset = pxav2_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, + .request_done = pxav1_request_done, }; static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = { @@ -193,7 +247,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) int ret; struct clk *clk, *clk_core; - host = sdhci_pltfm_init(pdev, NULL, 0); + host = sdhci_pltfm_init(pdev, NULL, sizeof(struct sdhci_pxav2_host)); if (IS_ERR(host)) return PTR_ERR(host); From patchwork Thu Dec 29 20:04:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 638056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E5FAC46467 for ; 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([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:05:07 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v3 7/8] mmc: sdhci-pxav2: add optional pinctrl for SDIO IRQ workaround Date: Thu, 29 Dec 2022 12:04:10 -0800 Message-Id: <20221229200411.295339-8-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PXA168 errata recommends that the CMD signal should be detached from the SD bus while performing the dummy CMD0 to restart the clock. Implement this using pinctrl states. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 10fa9de14ad4..38edd1fcc992 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -45,6 +46,9 @@ struct sdhci_pxav2_host { struct mmc_request *sdio_mrq; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_cmd_gpio; }; static void pxav2_reset(struct sdhci_host *host, u8 mask) @@ -104,6 +108,11 @@ static u32 pxav1_irq(struct sdhci_host *host, u32 intmask) /* The dummy CMD0 for the SDIO workaround just completed */ sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); intmask &= ~SDHCI_INT_CMD_MASK; + + /* Restore MMC function to CMD pin */ + if (pxav2_host->pinctrl && pxav2_host->pins_default) + pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_default); + sdio_mrq = pxav2_host->sdio_mrq; pxav2_host->sdio_mrq = NULL; mmc_request_done(host->mmc, sdio_mrq); @@ -129,6 +138,11 @@ static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq) /* Clock is now stopped, so restart it by sending a dummy CMD0 */ pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); pxav2_host->sdio_mrq = mrq; + + /* Set CMD as high output rather than MMC function while we do CMD0 */ + if (pxav2_host->pinctrl && pxav2_host->pins_cmd_gpio) + pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_cmd_gpio); + sdhci_writel(host, 0, SDHCI_ARGUMENT); sdhci_writew(host, 0, SDHCI_TRANSFER_MODE); sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE), @@ -240,6 +254,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) { struct sdhci_pltfm_host *pltfm_host; struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; + struct sdhci_pxav2_host *pxav2_host; struct device *dev = &pdev->dev; struct sdhci_host *host = NULL; const struct sdhci_pxa_variant *variant; @@ -247,11 +262,12 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) int ret; struct clk *clk, *clk_core; - host = sdhci_pltfm_init(pdev, NULL, sizeof(struct sdhci_pxav2_host)); + host = sdhci_pltfm_init(pdev, NULL, sizeof(*pxav2_host)); if (IS_ERR(host)) return PTR_ERR(host); pltfm_host = sdhci_priv(host); + pxav2_host = sdhci_pltfm_priv(pltfm_host); clk = devm_clk_get(dev, "io"); if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFER) @@ -306,6 +322,21 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) host->quirks |= variant->extra_quirks; host->ops = variant->ops; + /* Set up optional pinctrl for PXA168 SDIO IRQ fix */ + pxav2_host->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(pxav2_host->pinctrl)) { + pxav2_host->pins_cmd_gpio = pinctrl_lookup_state(pxav2_host->pinctrl, + "state_cmd_gpio"); + if (IS_ERR(pxav2_host->pins_cmd_gpio)) + pxav2_host->pins_cmd_gpio = NULL; + pxav2_host->pins_default = pinctrl_lookup_state(pxav2_host->pinctrl, + "default"); + if (IS_ERR(pxav2_host->pins_default)) + pxav2_host->pins_default = NULL; + } else { + pxav2_host->pinctrl = NULL; + } + ret = sdhci_add_host(host); if (ret) goto disable_clk; From patchwork Thu Dec 29 20:04:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 637648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5E8FC3DA7D for ; Thu, 29 Dec 2022 20:05:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233850AbiL2UFM (ORCPT ); Thu, 29 Dec 2022 15:05:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229598AbiL2UFK (ORCPT ); Thu, 29 Dec 2022 15:05:10 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FCAB167D0 for ; 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Thu, 29 Dec 2022 12:05:09 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id w17-20020a170902e89100b00189ac5a2340sm13438589plg.124.2022.12.29.12.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 12:05:09 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown , Krzysztof Kozlowski Subject: [PATCH v3 8/8] dt-bindings: mmc: sdhci-pxa: add pxav1 Date: Thu, 29 Dec 2022 12:04:11 -0800 Message-Id: <20221229200411.295339-9-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229200411.295339-1-doug@schmorgal.com> References: <20221229200411.295339-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a compatible for the pxav1 controller in the PXA168, along with optional pinctrl properties to use for an errata workaround. Signed-off-by: Doug Brown Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/mmc/sdhci-pxa.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index 1c87f4218e18..09455f9fa8de 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell PXA SDHCI v2/v3 bindings +title: Marvell PXA SDHCI v1/v2/v3 maintainers: - Ulf Hansson @@ -34,6 +34,7 @@ allOf: properties: compatible: enum: + - mrvl,pxav1-mmc - mrvl,pxav2-mmc - mrvl,pxav3-mmc - marvell,armada-380-sdhci @@ -61,6 +62,22 @@ properties: - const: io - const: core + pinctrl-names: + description: + Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between + SDIO CMD and GPIO mode. + items: + - const: default + - const: state_cmd_gpio + + pinctrl-0: + description: + Should contain default pinctrl. + + pinctrl-1: + description: + Should switch CMD pin to GPIO mode as a high output. + mrvl,clk-delay-cycles: description: Specify a number of cycles to delay for tuning. $ref: /schemas/types.yaml#/definitions/uint32