From patchwork Wed Apr 3 03:43:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161651 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2512369jan; Tue, 2 Apr 2019 20:47:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwMANLcF/8vSqYNuCa8k37G0paAZJcQs4wWXy7ZYUAPzKwsV+ioJeYOuzPA6jPUpe9Hm6pu X-Received: by 2002:a25:5785:: with SMTP id l127mr60922383ybb.395.1554263229264; Tue, 02 Apr 2019 20:47:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263229; cv=none; d=google.com; s=arc-20160816; b=UjbTW1x/wAlK072DIHFXtfFyJRhyYo6iUSpCw+Rym1m2/tsFIJtuyWGn1eH9ruYn/z n/06p6JpyzZlYurLk7TKISRXIQtG8jhFiqZDiWp0IKl3XGlweDljhKRtmEi1mLmwSKDK MMonD3FL2Vu+IdDyAUypLxSPqzk/WwfdhtiT60zZfGSOns2b0Yrf0JQLWmPIKh/9t4gX RLCLPNC7ngE6yMOj4JZUYuh27Tp84NF0qTRoFrgQAgeW7xBZgk1qfeOQn/92w7x495CH ig2ahJ5FI3hyiEHS1rWJQPWzrd8HMK0ino8XKXAxHjKh8qM2m57ZO2+O5ECJyP3JeKwB OXYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=eEcb3jpHhBL5V4XKribm6nF4P3y4UD0GK5XfT/XCp8U=; b=CvbarCjNPxC+sVYk4vAwJt9kvj9jc6fMRVLiezKIjSq7esVMhpTKKf/mYtGuSfLKFv bETVmYl3xS7gqSPUDLrqu5yJ3+VzUofuk9H4XjBX0PBUn7U7uvsIyrIKQbiAaNpdRV2y MWNRFImHaegXa7Qr1zXC/l+sihJQZJOELYrf8wuu9CnoPmue2MgNzAM9QVREmhqhC/mw 3F5S0g7I0Zvei+8ZK4DIeboHN/ZAYl/Afhidl/yvdXTjZw6+BiS+0lpnNI9YXHR11DUT fWpzTRBMtX2Bvy9D+5DwG0QysQSRK7UU6WasBAXjDyGVR8UF94wEtXoYtwpxZHhc26WX I4Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B90uKOmq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b71si7083202ywe.132.2019.04.02.20.47.09 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 02 Apr 2019 20:47:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=B90uKOmq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:51880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWrk-0005Gi-Pq for patch@linaro.org; Tue, 02 Apr 2019 23:47:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48452) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWoo-0002c4-P4 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWon-0007mW-SY for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:06 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:37469) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWon-0007lf-Lo for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:05 -0400 Received: by mail-pl1-x644.google.com with SMTP id w23so4370461ply.4 for ; Tue, 02 Apr 2019 20:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=eEcb3jpHhBL5V4XKribm6nF4P3y4UD0GK5XfT/XCp8U=; b=B90uKOmqgF7EsJHr8jSCfUoZlwOmSDsOZZtu6n0roECm9uhF5MwZQEW/64NwI9+LU8 e0+YUXJh2N9qzqCCZEZyZXmtjw601kvBv43pZM1CiepuZAm2C2LT/QLuglE9g6r93275 pp5tsptbbK8+x5KHBosJhGSZE8IFY6Lq0tyCOQkw5DbffPsnH4JtSaJ5PMA0NzXrZ6Al F2Bmw/HCk2t9O2Kb14udtmaK1ydmxcf+9uKvjQTE7Tov2uKjgocLkNPxeV8d3sqrjuan QN1VjGYe5n0mCia7Gxa1Z/zJPt9w8gu0H36NtYc5Kl+N7yWsD5E03oUhXUBiFLbmd6pZ fHqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=eEcb3jpHhBL5V4XKribm6nF4P3y4UD0GK5XfT/XCp8U=; b=ZNoMOUXfjVT3HPQ2eEViaRA2/9wm1NR1QSKsNP3c/4rneac50td0R1KJTICAQGiRqn YyhNswATuQaXuMiYqDDgbpzG6Ty9IX/sn0f1yxL+OQ43/Sk25ubfdhPSEbOAuRbviuQf EFkD+MMmiJ5GMsUMHVCJJYZ+n1+kWUHHrhE54Q4GqCnnKma8Jdd1Dco6ywROpqREixj2 +UGI/N8h14mNRUYVDd3lJ8GFvaHIRWdF1hzcF08bTs5/u1WNA1AViBc/76Ee3T4NNdUp g1wqICkFMFCG34KeH9ToO3lJRu2ONleK/lR24oQbIY1DNdMVEn0kEbDk3Sgy5xWNt1OE KbmA== X-Gm-Message-State: APjAAAWHtveauEHGUpyGZm9q0JG17jQxsHlJDkbN6XH2h9VmI+TdsFQ/ 1rgxnxGskEffLFXglVjYf0FpPt7u8DuH1g== X-Received: by 2002:a17:902:2bab:: with SMTP id l40mr74190163plb.273.1554263044391; Tue, 02 Apr 2019 20:44:04 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:33 +0700 Message-Id: <20190403034358.21999-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 01/26] tcg: Assert h2g_valid for 32-bit guest on 64-bit host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For this combination, we can tell whether or not the address being accessed is within the 4GB range that is accessible by the guest. Otherwise the fault must be elsewhere in qemu, accessing qemu data structures. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0789984fe6..fa9380a380 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -143,6 +143,15 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, } } + /* + * For a 32-bit guest on a 64-bit host, the set of addresses that we + * access on behalf of the guest is constrained. Anything outside + * that range is a bug elsewhere in QEMU. + */ +#if TARGET_LONG_BITS == 32 && HOST_LONG_BITS == 64 + g_assert(h2g_valid(address)); +#endif + /* Convert forcefully to guest address space, invalid addresses are still valid segv ones */ address = h2g_nocheck(address); From patchwork Wed Apr 3 03:43:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161654 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2514208jan; Tue, 2 Apr 2019 20:50:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqx4TyQlum1LWEupaujgTyZbn+o4bVhiNLLFjQzfB91602cEJulBHl5v6x1MJcBJv4wxUoA0 X-Received: by 2002:a0d:de82:: with SMTP id h124mr14530689ywe.430.1554263411339; Tue, 02 Apr 2019 20:50:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263411; cv=none; d=google.com; s=arc-20160816; b=R93WKaUji+XKFOti4ON6PVsIiMWqcjCFakGlrXVZnWG8w1jKIfhUYjmaz4s0r2wv0L jtrrjpx0YQxy77xHYZRwguCi9ZRSqyoEpR5lBSRsMNHIGclgHoLWZ2BJKFbmU5yGSct3 1wh0OzqpKlLRpZEl2DRAGx01z1e9Nm8hMU2yrBJ06EBZA1NU2Ka4tE0jXhwq5ZHODNcf WeJKpJn8lvMf2Lz3It49BtBnujnGbTI5PcbvQYm9eJc9oEcgYj8jBUxvxyALBA6mwvt6 UhVPhbbp5cIHTW++8EO+9tqIvH53ugm74MLI3RRAk8EwiGtG5OYgW7u6kOFOpA0KfUnO pjnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=a1RF8tzN4d+znSGg74/q0NFp8F7G9Ydq9o76y67KjZ4=; b=1Jn9GYpWUZOqcG7jZuyq8snGh1ppzXNnq3NMK0L/QSb357qYgC9XRq8hJjB2ZlKuX6 sS2FzQg8pwyy9YMrsysfo4ZY9jqGTShgszN+o7E6781yBoe7a5Fk6G93jkdUqH35aAOi x0aszIKDalxaJm8Myil7LU0KcfDP3wGWtRwdaZBukbAcSKzIYP/qikjH1BuR/X7QTBXB 8vlb/2l8MHQ1DSMnl8982pAnBIPX2qI9uRWEg6Wp7KM3GH1k/7agXpxACrUD5ZI1sL5J JoggdBcVimxFWTI8b3Sum58kWaGVqO7ujhU5NIqZ5aG38Vbcyxlqnzt4S4QNrOys+rne X48A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C9gLXxmP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 02/26] tcg: Add CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This hook will replace the (user-only mode specific) handle_mmu_fault hook, and the (system mode specific) tlb_fill function. The handle_mmu_fault hook was written as if there was a valid way to recover from an mmu fault, and had 3 possible return states. In reality, the only valid action is to raise an exception, return to the main loop, and delver the SIGSEGV to the guest. Using the hook for system mode requires that all targets be converted, so for now the hook is (optionally) used only from user-only mode. Signed-off-by: Richard Henderson --- include/qom/cpu.h | 9 +++++++++ accel/tcg/user-exec.c | 42 ++++++++++++++---------------------------- 2 files changed, 23 insertions(+), 28 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1d6099e5d4..7e96a0aed3 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -119,6 +119,12 @@ struct TranslationBlock; * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). * @handle_mmu_fault: Callback for handling an MMU fault. + * @tlb_fill: Callback for handling a softmmu tlb miss or user-only + * address fault. For system mode, if the access is valid, call + * tlb_set_page and return true; if the access is invalid, and + * probe is true, return false; otherwise raise an exception and + * do not return. For user-only mode, always raise an exception + * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the * associated memory transaction attributes to use for the access. @@ -194,6 +200,9 @@ typedef struct CPUClass { void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, int mmu_index); + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fa9380a380..f13c0b2b67 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -65,6 +65,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, CPUClass *cc; int ret; unsigned long address = (unsigned long)info->si_addr; + MMUAccessType access_type; /* We must handle PC addresses from two different sources: * a call return address and a signal frame address. @@ -151,40 +152,25 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, #if TARGET_LONG_BITS == 32 && HOST_LONG_BITS == 64 g_assert(h2g_valid(address)); #endif - - /* Convert forcefully to guest address space, invalid addresses - are still valid segv ones */ address = h2g_nocheck(address); - cc = CPU_GET_CLASS(cpu); - /* see if it is an MMU fault */ - g_assert(cc->handle_mmu_fault); - ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); - - if (ret == 0) { - /* The MMU fault was handled without causing real CPU fault. - * Retain helper_retaddr for a possible second fault. - */ - return 1; - } - - /* All other paths lead to cpu_exit; clear helper_retaddr - * for next execution. + /* + * There is no way the target can handle this other than raising + * an exception. Undo signal and retaddr state prior to longjmp. */ + sigprocmask(SIG_SETMASK, old_set, NULL); helper_retaddr = 0; - if (ret < 0) { - return 0; /* not an MMU fault */ + cc = CPU_GET_CLASS(cpu); + if (cc->tlb_fill) { + access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + g_assert_not_reached(); + } else { + ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); + g_assert(ret > 0); + cpu_loop_exit_restore(cpu, pc); } - - /* Now we have a real cpu fault. */ - cpu_restore_state(cpu, pc, true); - - sigprocmask(SIG_SETMASK, old_set, NULL); - cpu_loop_exit(cpu); - - /* never comes here */ - return 1; } #if defined(__i386__) From patchwork Wed Apr 3 03:43:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161653 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2514124jan; Tue, 2 Apr 2019 20:50:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqwycaSyL6DnE+Q0pA2MN5G6f3PrtyFroCe8JsXS+XaImXq6a3MQy2uOOf5MT8akdSFeS7ok X-Received: by 2002:a0d:c745:: with SMTP id j66mr61431074ywd.258.1554263405381; Tue, 02 Apr 2019 20:50:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263405; cv=none; d=google.com; s=arc-20160816; b=hGG8aR2UNwwfTs7bvk7fgCOtQVjHpvuFUPJpK0OgtcpmLFUnVKiw7CwybXOLEwonw3 2sI6fijhAJozZHeCr5QFBV8koITxH3p+NIJaLLSHGg/PHRx+jZcZGNqMCbJbnao1l8YG Wo837r9U0qLMvLy4F6Wpfi4weekK8J7Ksm980kkSoMc+3u6yxCPH1HW3Sz4fWiv6NtVk tfIq1QTFTaFR9GVkOM0fC9tutGSc6a+o8WbRCI/Xq+3AME19vOSrsgaQqQbExeyuuUy3 3X+DLbMPX9yKIbhAi7wiXrjZ+8qyhWd/FnWc8ah3TF2CwxCt7WG2Rba7sImSuEWFKf3J Av/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=T6WPmTFnuwgmwKqzFLAzjRNZe3eRbqRWr6UuIt9sYlM=; b=o5a6N1QudlZVGcF8TLhhmE1ftvP6iCulHu/l64yLhc0c32Sp10ePV5W+xbfT3h48YN +7d1l2MN0+1IWIHkoE8BWDYe2Cq7/TqUhmFtkMm2ew+rP4WqwGR5IrwpgaDOeSwCjM1E YLhATBXNDMrvUvf3VFGbcdwnlD2wkluRg/LzbgWF6DVBbfKLkPXpf6oVX1oV3V5WASj+ 4CaosjhNKVKlWQZyoTZbDQCa3DUm9vYgpMbbudquUmZnMDXqqhR394Zd6M8KWVq9oS3b Nj/BBVxUdU2LSdSzYySpqECyxuOf5Ytps3f5BZDP83h61wUQLFwJ4bGJpjBcTPtQWT4u IBAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xFz3J8Yr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 03/26] target/alpha: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 5 ++-- target/alpha/cpu.c | 5 ++-- target/alpha/helper.c | 50 +++++++++++++++++++++++---------------- target/alpha/mem_helper.c | 16 ------------- 4 files changed, 35 insertions(+), 41 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 7b50be785d..aecf8d75c1 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -476,8 +476,9 @@ void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf); is returned if the signal was handled by the virtual CPU. */ int cpu_alpha_signal_handler(int host_signum, void *pinfo, void *puc); -int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 1fd95d6c0f..5aa4581b9f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -230,9 +230,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; cc->gdb_write_register = alpha_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault; -#else + cc->tlb_fill = alpha_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed = alpha_cpu_do_transaction_failed; cc->do_unaligned_access = alpha_cpu_do_unaligned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 57e2c212b3..e54197d5fb 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -102,17 +102,7 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val) *cpu_alpha_addr_gr(env, reg) = val; } -#if defined(CONFIG_USER_ONLY) -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - AlphaCPU *cpu = ALPHA_CPU(cs); - - cs->exception_index = EXCP_MMFAULT; - cpu->env.trap_arg0 = address; - return 1; -} -#else +#ifndef CONFIG_USER_ONLY /* Returns the OSF/1 entMM failure indication, or -1 on success. */ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, @@ -246,29 +236,49 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot); return (fail >= 0 ? -1 : phys); } +#endif /* !USER_ONLY */ -int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw, - int mmu_idx) +bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { AlphaCPU *cpu = ALPHA_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cs->exception_index = EXCP_MMFAULT; + cpu->env.trap_arg0 = address; + cpu_loop_exit_restore(cs, retaddr); +#else CPUAlphaState *env = &cpu->env; target_ulong phys; int prot, fail; - fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot); + fail = get_physical_address(env, address, 1 << access_type, + mmu_idx, &phys, &prot); if (unlikely(fail >= 0)) { + if (probe) { + return false; + } cs->exception_index = EXCP_MMFAULT; - env->trap_arg0 = addr; + env->trap_arg0 = address; env->trap_arg1 = fail; - env->trap_arg2 = (rw == 2 ? -1 : rw); - return 1; + env->trap_arg2 = (access_type == MMU_INST_FETCH ? -1 : access_type); + cpu_loop_exit_restore(cs, retaddr); } - tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, + tlb_set_page(cs, address & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; +#endif } -#endif /* USER_ONLY */ + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif void alpha_cpu_do_interrupt(CPUState *cs) { diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 011bc73dca..934faa1d6f 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -62,20 +62,4 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, env->error_code = 0; cpu_loop_exit_restore(cs, retaddr); } - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = alpha_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret != 0)) { - /* Exception index and error code are already set */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif /* CONFIG_USER_ONLY */ From patchwork Wed Apr 3 03:43:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161649 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2510874jan; Tue, 2 Apr 2019 20:44:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqyvbqzJkjF69KOlKnHDuI76N9xi6rKN34zHAWdAUU1GKtwxm8mWlJBkP0KYqG2ELzHaMMaV X-Received: by 2002:a25:1e55:: with SMTP id e82mr34088400ybe.119.1554263081754; Tue, 02 Apr 2019 20:44:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263081; cv=none; d=google.com; s=arc-20160816; b=jB2hhW2GFm4uqm1Cf2RnaElorbJyCvLQwFxX48+V/qwz0zP3uSfavWv7SeHfO3IPzS hsjt4IoM2sGl0JiNFDaCXkj+s0uunjhjaauDjRcrCWsBp5Itmm3SMiyIdlhhCR02pYH/ S6JLgHDh6S/kXqo2K6si5oQc/qVRNGk2Pxuanup9YxWjZT4mBXPOp3kOvrNaiANqjk0b ZCKYAuSIL6M7R4M84YGyqkTBXT6BFKmXwIb+V7pDJqBPxcuCkSqHzC9eTKY85jFAwuf9 7uC96lT14IZJFypjOx0k7lttdt5ktZA9eZr1DNWVw/Z+haeVerc9Eqh3dE1sjTkVwtKj CqYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=TcaPmSrwhcdn8wz+i6qqtqby6cFp9SRTGijL0/DhbE8=; b=JUKK6ocSBAySTChorK6Woho/IAWFNVVQqeaiiJg7jkoPT4LH4z8mxalT9DDLhj0qSH kwJxn/t9hM1N/S3AhiBuVcWvE7I3V86o0tFu6f6JCxnmHzMmIDiK2KQZs4YlQQm4zPAp RHEfbgczhUo3q+EQPWuHNNnEusqKKC08RrwNTBP4P7ySUJuNP4G/qdfikRaL8TJVaSoj fsZGvcBzqFMWcwsNXkrXAHRMThipBlQYrrRFiEUgKwvaBMpcbWpT9Ohl8l2y4TqD8GUg NqluFOsbZj8akXSQvRABWweoU5az62QrCUJ65SRKYPCZvD8Kak+abqFnHVz6MoVYXCwM 58Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GQjvsQmF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 04/26] target/arm: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-arm@nongnu.org Signed-off-by: Richard Henderson --- target/arm/internals.h | 10 +++-- target/arm/cpu.c | 22 +--------- target/arm/helper.c | 97 ++++++++++++++++++++++++++---------------- target/arm/op_helper.c | 29 ++----------- 4 files changed, 72 insertions(+), 86 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..5a02f458f3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -761,10 +761,12 @@ static inline bool arm_extabort_type(MemTxResult result) return result != MEMTX_DECODE_ERROR; } -/* Do a page table walk and add page to TLB if possible */ -bool arm_tlb_fill(CPUState *cpu, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi); +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) QEMU_NORETURN; /* Return true if the stage 1 translation regime is using LPAE format page * tables */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4155782197..3b87d897a2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2114,23 +2114,6 @@ static Property arm_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; -#ifdef CONFIG_USER_ONLY -static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - env->exception.vaddress = address; - if (rw == 2) { - cs->exception_index = EXCP_PREFETCH_ABORT; - } else { - cs->exception_index = EXCP_DATA_ABORT; - } - return 1; -} -#endif - static gchar *arm_gdb_arch_name(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); @@ -2163,9 +2146,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; cc->gdb_read_register = arm_cpu_gdb_read_register; cc->gdb_write_register = arm_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; -#else + cc->tlb_fill = arm_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_cpu_do_interrupt; cc->do_unaligned_access = arm_cpu_do_unaligned_access; cc->do_transaction_failed = arm_cpu_do_transaction_failed; diff --git a/target/arm/helper.c b/target/arm/helper.c index a36f4b3d69..0fc4abc651 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11918,43 +11918,6 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } } -/* Walk the page table and (if the mapping exists) add the page - * to the TLB. Return false on success, or true on failure. Populate - * fsr with ARM DFSR/IFSR fault register format value on failure. - */ -bool arm_tlb_fill(CPUState *cs, vaddr address, - MMUAccessType access_type, int mmu_idx, - ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - int ret; - MemTxAttrs attrs = {}; - - ret = get_phys_addr(env, address, access_type, - core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fi, NULL); - if (!ret) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (page_size >= TARGET_PAGE_SIZE) { - phys_addr &= TARGET_PAGE_MASK; - address &= TARGET_PAGE_MASK; - } - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); - return 0; - } - - return ret; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { @@ -12389,6 +12352,66 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) #endif +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu = ARM_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cpu->env.exception.vaddress = address; + if (access_type == MMU_INST_FETCH) { + cs->exception_index = EXCP_PREFETCH_ABORT; + } else { + cs->exception_index = EXCP_DATA_ABORT; + } + cpu_loop_exit_restore(cs, retaddr); +#else + hwaddr phys_addr; + target_ulong page_size; + int prot, ret; + MemTxAttrs attrs = {}; + ARMMMUFaultInfo fi = {}; + + /* + * Walk the page table and (if the mapping exists) add the page + * to the TLB. Return false on success, or true on failure. Populate + * fsr with ARM DFSR/IFSR fault register format value on failure. + */ + ret = get_phys_addr(&cpu->env, address, access_type, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &phys_addr, &attrs, &prot, &page_size, &fi, NULL); + if (likely(!ret)) { + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >= TARGET_PAGE_SIZE) { + phys_addr &= TARGET_PAGE_MASK; + address &= TARGET_PAGE_MASK; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); + return true; + } else if (probe) { + return false; + } else { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + } +#endif +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif + void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..8ee15a4bd4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -126,8 +126,8 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } -static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) +void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env = &cpu->env; int target_el; @@ -179,27 +179,6 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, raise_exception(env, exc, syn, target_el); } -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - bool ret; - ARMMMUFaultInfo fi = {}; - - ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi); - if (unlikely(ret)) { - ARMCPU *cpu = ARM_CPU(cs); - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); - } -} - /* Raise a data fault alignment exception for the specified virtual address */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, @@ -212,7 +191,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, cpu_restore_state(cs, retaddr, true); fi.type = ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } /* arm_cpu_do_transaction_failed: handle a memory system error response @@ -233,7 +212,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, fi.ea = arm_extabort_type(response); fi.type = ARMFault_SyncExternal; - deliver_fault(cpu, addr, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } #endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Wed Apr 3 03:43:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161652 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2512634jan; Tue, 2 Apr 2019 20:47:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqx/o4xzK6seqTdkbErXxtlv784A70fR1EEV/3OHSPxHqtu3YQvdSvO8xBi+3yg/9oC1lRxU X-Received: by 2002:a25:910f:: with SMTP id v15mr5802288ybl.92.1554263256195; Tue, 02 Apr 2019 20:47:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263256; cv=none; d=google.com; s=arc-20160816; b=jMR2qhFWEtQMoF7G7SY/WQgyJAs9EUZyIzimZjiTLojF5TUKNKLAtmnRX5d4uj+OZK Q5lRhbdlbsnL/zAF3v4D0N9XhVg5Wd/9fkR8KR52YpAFhDCZHwoGCiEETzo0QZYbPs3z lKihh5rG9EGQAViymDq0kYKDSpgdz8Q4xycyvcaMz4D9dAATqoJGqFkQup1G+CrBgOTr DpbEV/yoT960Jgq2ngJbZhiZll1CLfrGs1/+BPKpzSpMbvbs5c8ttdUTaW68uhIablbB vYgS2VyadLhNhehepW14RZFUydcWJvfU0qcTkMFjbmeaL8MTRL2OPjPThoBLoZqwxvmv 4Gxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=xpwl7WdMeWcUgLBr7cxgr4owlhQ7kgg63h4qX+x2VJ8=; b=hdSf8OOqV5CKPG4KtUwXRTE7T6GsftLZkpKbvqRbyv9eCxzBD7TquQY7AfZQ7BAc26 AH8AVXIGjaiBL5SJxepk6BoP2+21itsa8yEaCuLtEzWehZ2CgyVyzLEfg+kRZ768/Bhk h33y/qOSqDVWUc+ZDgAJDASnjdCYn+vLxOJN2zeW9VIN9HIlGerDo+dSRtwxO+tLoSVQ hf+8anp1O+qB6mBtGd05Hs4nFejTNL2Dh251+VPDn10bV/8kqoooR9RwN0Tqyr9EacrA H3RIPoHLZ175Ebd8oLDpLg2VqjkFtEkARaYttLPCoDcgIIsQ63LvbbclUfZrsbG1rX9v KrXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="N80X/egJ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 05/26] target/cris: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/cris/cpu.h | 5 +-- target/cris/cpu.c | 5 ++- target/cris/helper.c | 67 +++++++++++++++++++++++------------------ target/cris/op_helper.c | 28 ----------------- 4 files changed, 42 insertions(+), 63 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 8bb1dbc989..f3c3b428ca 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -282,8 +282,9 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } -int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index a23aba2688..145c33a85a 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -273,9 +273,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; cc->gdb_write_register = cris_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = cris_cpu_handle_mmu_fault; -#else + cc->tlb_fill = cris_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; dc->vmsd = &vmstate_cris_cpu; #endif diff --git a/target/cris/helper.c b/target/cris/helper.c index b2dbb2075c..69464837c8 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -24,6 +24,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" //#define CRIS_HELPER_DEBUG @@ -53,15 +54,15 @@ void crisv10_cpu_do_interrupt(CPUState *cs) cris_cpu_do_interrupt(cs); } -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu = CRIS_CPU(cs); cs->exception_index = 0xaa; cpu->env.pregs[PR_EDA] = address; - cpu_dump_state(cs, stderr, fprintf, 0); - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else /* !CONFIG_USER_ONLY */ @@ -76,33 +77,19 @@ static void cris_shift_ccs(CPUCRISState *env) env->pregs[PR_CCS] = ccs; } -int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; struct cris_mmu_result res; int prot, miss; - int r = -1; target_ulong phy; - qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n", - __func__, address, env->pc, rw); miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, - rw, mmu_idx, 0); - if (miss) { - if (cs->exception_index == EXCP_BUSFAULT) { - cpu_abort(cs, - "CRIS: Illegal recursive bus fault." - "addr=%" VADDR_PRIx " rw=%d\n", - address, rw); - } - - env->pregs[PR_EDA] = address; - cs->exception_index = EXCP_BUSFAULT; - env->fault_vector = res.bf_vec; - r = 1; - } else { + access_type, mmu_idx, 0); + if (likely(!miss)) { /* * Mask off the cache selection bit. The ETRAX busses do not * see the top bit. @@ -111,15 +98,35 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, prot = res.prot; tlb_set_page(cs, address & TARGET_PAGE_MASK, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - r = 0; + return true; } - if (r > 0) { - qemu_log_mask(CPU_LOG_MMU, - "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" - " pc=%x\n", __func__, r, cs->interrupt_request, address, - res.phy, res.bf_vec, env->pc); + + if (probe) { + return false; } - return r; + + if (cs->exception_index == EXCP_BUSFAULT) { + cpu_abort(cs, "CRIS: Illegal recursive bus fault." + "addr=%" VADDR_PRIx " access_type=%d\n", + address, access_type); + } + + env->pregs[PR_EDA] = address; + cs->exception_index = EXCP_BUSFAULT; + env->fault_vector = res.bf_vec; + if (retaddr) { + if (cpu_restore_state(cs, retaddr, true)) { + /* Evaluate flags after retranslation. */ + helper_top_evaluate_flags(env); + } + } + cpu_loop_exit(cs); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } void crisv10_cpu_do_interrupt(CPUState *cs) diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 0ee3a3117b..26a395b413 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -37,34 +37,6 @@ #define D_LOG(...) do { } while (0) #endif -#if !defined(CONFIG_USER_ONLY) -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; - int ret; - - D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__, - env->pc, env->pregs[PR_EDA], (void *)retaddr); - ret = cris_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - if (retaddr) { - /* now we have a real cpu fault */ - if (cpu_restore_state(cs, retaddr, true)) { - /* Evaluate flags after retranslation. */ - helper_top_evaluate_flags(env); - } - } - cpu_loop_exit(cs); - } -} - -#endif - void helper_raise_exception(CPUCRISState *env, uint32_t index) { CPUState *cs = CPU(cris_env_get_cpu(env)); From patchwork Wed Apr 3 03:43:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161656 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2514524jan; Tue, 2 Apr 2019 20:50:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxIJYpyWPJNZizc80uGmhHyBxbJt81T52UPTAjJUXlKv64GYMSXdkk4y/uzRrqyxfuEu2hI X-Received: by 2002:a25:5985:: with SMTP id n127mr1275090ybb.36.1554263440509; Tue, 02 Apr 2019 20:50:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263440; cv=none; d=google.com; s=arc-20160816; b=bwSagBnfeIiWl9hNnVHQk4iN3vnk3hbCsMIvXjjBGH84tt0hhdPb62GOyPdb2h5QbV vA1EKJKCm4Wkf5BQ7s8PxwyVJHhBR32ivJfBwqhOwL/3EkSOJneT8ljb3AGnc/8AEAEi Yp4KJz+VFqzEvYYVwFBS4N97OrWqgmuG5Ltt4J915wMsc2TnOTwQPkpzEkEMVMw9Oxi+ fJJl3cajXHwklIgWOBCaIBb2993KZNhiKfDCMjlmwUiP2Tk6LoxitpRoZNbg4tv71eMY BxbnBDUd0lR9b1O10y6IZOEwWiPzyTeD/q/aecGk0MAy3jtrl6cwVFWHdd5v7MrPzgf1 VASQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IUotWWo3041r0D9XZuJ8LGQL3RkKcjD1vbj2Rf1RYCg=; b=pxZLj+xSLC8M9tQeLMuHL1/59Tqjca07IZu0HbNv0x+hsLNw2mOxRV+987kBLBKr5A /9m8Y27K6emaVa99376Ay7/FGhfFbMcGNfUZq3+0Sm7J1Cfvs3997K+ykBpZoSx0n1MX 8x8dVZXkX13mb0mWP9XA1JMywAyHIbQKXia3Wils7qM2o/gFx6wQrs0ZlonSqQGqWMZ9 B+2IJ5apdYp44F3D/2m/vKpNuMN312IbdKFgnhpWfzZ20eD3KPVeAIOs54I+LAkuYVwc Kb+cAfItptQ+7Wf9u2jSSs8R3UAXfKETvxT9l3WmfbU4h7McxGO6un8lDG7YBduPo589 Fa5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="j/hfGQxb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 06/26] target/hppa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 8 ++++---- target/hppa/cpu.c | 5 ++--- target/hppa/mem_helper.c | 22 +++++++++++++++++----- 3 files changed, 23 insertions(+), 12 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c062c7969c..e0e5d879e1 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -360,10 +360,10 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int); -#ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int midx); -#else +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +#ifndef CONFIG_USER_ONLY int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 00bf444620..46750980f7 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -167,9 +167,8 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; cc->gdb_read_register = hppa_cpu_gdb_read_register; cc->gdb_write_register = hppa_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; -#else + cc->tlb_fill = hppa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; dc->vmsd = &vmstate_hppa_cpu; #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c9b57d07c3..f61b0fdb9f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -25,8 +25,9 @@ #include "trace.h" #ifdef CONFIG_USER_ONLY -int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, - int size, int rw, int mmu_idx) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu = HPPA_CPU(cs); @@ -34,7 +35,7 @@ int hppa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, which would affect si_code. */ cs->exception_index = EXCP_DMP; cpu->env.cr[CR_IOR] = address; - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) @@ -214,8 +215,9 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return excp == EXCP_DTLB_MISS ? -1 : phys; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) +bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType type, int mmu_idx, + bool probe, uintptr_t retaddr) { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; @@ -237,6 +239,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >= 0)) { + if (probe) { + return false; + } trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); /* Failure. Raise the indicated exception. */ cs->exception_index = excp; @@ -253,6 +258,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType type, int mmu_idx, uintptr_t retaddr) +{ + hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); } /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ From patchwork Wed Apr 3 03:43:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161655 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2514365jan; Tue, 2 Apr 2019 20:50:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqyPI7ZHcpzxNt7MTLEb8UGpVEhGLHij4Cim2U7uMtwt5YJx5jDIZahxqaRSv734HWPaAffL X-Received: by 2002:a0d:d9c5:: with SMTP id b188mr59409953ywe.420.1554263424940; Tue, 02 Apr 2019 20:50:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263424; cv=none; d=google.com; s=arc-20160816; b=nBbSW/Xr1GZVNlLbs5MNnlO+xiKINpN7XY4teKvJqQ5u5J31SvqFA5iHGpdZt3FKKx tRn3ZbTc/4lTiEI2w1Qkljke4e0B0DdkpiIsNcePECde89zDP99WhDTzOZFlc+7s1eXt ceNUYFqn44eA9it+BXY5GAHcsFpkA/S5Sid7oq2uGZqL06dTSOWFGJDY2h0yl7lWzWbv 5te1uYfG1Dvy6cfkV/8bZ1eiufPoob5PhU5HIXFQawWQ8Sg7bT0BLyGaXOC5Q4KdUqPe hhcX3uQ9gpvZInQOeXPtQ3kjVnD4gUFAcAPQvAYZ52DV/7JZVroacCdMjRsHaBn91KE+ s4hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=03y4rJUeRFEukrKOoroIoXi8bqiR++D8zkd8dBnyBJA=; b=JQwvHrLsLlnQHkUWHf0oZy3D5sUoKn+Pqb2IJ86/V5Oa+csBnZ5/hodpN18vRRhQeB 7EKM3NJGXZ1gZ0m8gUdaZSv/xH2yIsmFZN46wTwoM4M7p+74XNCe1cLnJ13ajg9XGkPE WTNXelZ4f2xh7s9pdHbSPL4JqRLIzDsm/1dzViRetjORV0+jhKDk0hvg81MF4ZEQfguL yGwdN4lvjbP5+6CWvBH6hhPaXYXEWiIyg/7ghwTbrBcNRB6J12fG0SZ33nxN/hWnL8oR POpPArtAQOPVglzDS5XSljdx1i2PQitQHv/5HfIht/ShIBHfc0uMwEpPxr3fZWTX39AS xAng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fZfC+CaP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PATCH 07/26] target/i386: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not support probing, but we do not need it yet either. Cc: Paolo Bonzini Cc: Eduardo Habkost Signed-off-by: Richard Henderson --- target/i386/cpu.h | 5 ++-- target/i386/cpu.c | 5 ++-- target/i386/excp_helper.c | 61 +++++++++++++++++++++++++-------------- target/i386/mem_helper.c | 21 -------------- 4 files changed, 44 insertions(+), 48 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 83fb522554..1ce070ceb9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1655,8 +1655,9 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); /* helper.c */ -int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, - int is_write, int mmu_idx); +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d6bb57d210..237bd88710 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5866,9 +5866,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = x86_cpu_gdb_write_register; cc->get_arch_id = x86_cpu_get_arch_id; cc->get_paging_enabled = x86_cpu_get_paging_enabled; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = x86_cpu_handle_mmu_fault; -#else + cc->tlb_fill = x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->asidx_from_attrs = x86_asidx_from_attrs; cc->get_memory_mapping = x86_cpu_get_memory_mapping; cc->get_phys_page_debug = x86_cpu_get_phys_page_debug; diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 49231f6b69..6f59b7bafc 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -137,26 +137,7 @@ void raise_exception_ra(CPUX86State *env, int exception_index, uintptr_t retaddr raise_interrupt2(env, exception_index, 0, 0, 0, retaddr); } -#if defined(CONFIG_USER_ONLY) -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write, int mmu_idx) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - - /* user mode only emulation */ - is_write &= 1; - env->cr[2] = addr; - env->error_code = (is_write << PG_ERROR_W_BIT); - env->error_code |= PG_ERROR_U_MASK; - cs->exception_index = EXCP0E_PAGE; - env->exception_is_int = 0; - env->exception_next_eip = -1; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, int *prot) { @@ -365,8 +346,8 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, * 0 = nothing more to do * 1 = generate PF fault */ -int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, - int is_write1, int mmu_idx) +static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, + int is_write1, int mmu_idx) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; @@ -691,3 +672,39 @@ do_check_protect_pse36: return 1; } #endif + +bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + +#ifdef CONFIG_USER_ONLY + /* user mode only emulation */ + env->cr[2] = addr; + env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT; + env->error_code |= PG_ERROR_U_MASK; + cs->exception_index = EXCP0E_PAGE; + env->exception_is_int = 0; + env->exception_next_eip = -1; + cpu_loop_exit_restore(cs, retaddr); +#else + env->retaddr = retaddr; + if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) { + /* FIXME: On error in get_hphys we have already jumpped out. */ + g_assert(!probe); + raise_exception_err_ra(env, cs->exception_index, + env->error_code, retaddr); + } + return true; +#endif +} + +#if !defined(CONFIG_USER_ONLY) +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 6cc53bcb40..1885df29d2 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -191,24 +191,3 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v) raise_exception_ra(env, EXCP05_BOUND, GETPC()); } } - -#if !defined(CONFIG_USER_ONLY) -/* try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - int ret; - - env->retaddr = retaddr; - ret = x86_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr); - } -} -#endif From patchwork Wed Apr 3 03:43:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161657 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2514843jan; Tue, 2 Apr 2019 20:51:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqys88m/QzyvhWTZDB7+yeu7YqPuLCxG2nWE17CKKuPP+nnf/5oRtcuElwMNN4EF7LF84KCg X-Received: by 2002:a81:234b:: with SMTP id j72mr60794101ywj.279.1554263472726; Tue, 02 Apr 2019 20:51:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263472; cv=none; d=google.com; s=arc-20160816; b=WheS8jPirw+lJvptEUED3yiBlApZfLTBPcSv0EmCOuoMngO60U4NGlLg8SOT3YZcQZ Y3TNNGl3cI83c08FGmzWN1ZOMW97hTavIgwESiM8YHDWqPghRvqqOsx5wJ/8jZ51qkxT ljoUYJ4ZJek2RVmfB6CVtj+Z/QjRl30GpvUmAXx6UWzrKoYyaPbD8Qysz/V5+0WV2Y0m XO8NVwl65EoBRShiJmAbzZzQ40CtChGN5WlaEl8P+t0qeCjT03s6m9QFoZqqAk9GSHsj wu3cFVaOXhLCa9+9G5A/VGz8I0iSSiM3sz5HvApqCEDXuJc6dM01oUkkcXKRJoUq2ICq Xaxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=lVkBfrW6VirLiLfiWJMR0NKgqluxD319D02OYmRqkHk=; b=hXGG6Lb8N7XupO7mimOK4npQEAfXZ7rvL2dwGYIiY+R/8AxbC1KkeRUrNN55PsIzfZ wm4iD6xiMwanYOHo1gDTJR6CBqCkL+RF+RWeibzAltn+UUsbNNu551QFg9+zopVE6FpR 8F2ZZHdmm0chhEjiGj/5UgOyCR/AWRXZMd+de63HhRrCZR4I/+87Z8dgNm/ilXH1VUkk //KAnGM6ysEVJ+wu6YopNUMHRhP8/P92kW7TjChWG1ZDkrS/c+fkoGm2hBdi6boxuatj 4VGn/OffASXlAAdZAVOfCCOdfp5UgxwnSNHcAU+Xn4aSm6mdUT1Ojvw4uvzozcM9OzHU sSbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iCFXyCbS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 08/26] target/lm32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Walle Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Michael Walle Signed-off-by: Richard Henderson --- target/lm32/cpu.h | 5 +++-- target/lm32/cpu.c | 5 ++--- target/lm32/helper.c | 12 +++++++++--- target/lm32/op_helper.c | 16 ---------------- 4 files changed, 14 insertions(+), 24 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 66157eefe9..7cc279bcd0 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -262,8 +262,9 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define cpu_list lm32_cpu_list #define cpu_signal_handler cpu_lm32_signal_handler -int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #include "exec/cpu-all.h" diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index b7499cb627..6d2a176c87 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -235,9 +235,8 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = lm32_cpu_set_pc; cc->gdb_read_register = lm32_cpu_gdb_read_register; cc->gdb_write_register = lm32_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault; -#else + cc->tlb_fill = lm32_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_lm32_cpu; #endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index a039a993ff..1db9a5562e 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -25,8 +25,9 @@ #include "exec/semihost.h" #include "exec/log.h" -int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { LM32CPU *cpu = LM32_CPU(cs); CPULM32State *env = &cpu->env; @@ -40,8 +41,13 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, } else { tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); } + return true; +} - return 0; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c index 234d55e056..be12b11b02 100644 --- a/target/lm32/op_helper.c +++ b/target/lm32/op_helper.c @@ -143,21 +143,5 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env) { return lm32_juart_get_jrx(env->juart_state); } - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = lm32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} #endif From patchwork Wed Apr 3 03:43:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161664 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2518136jan; Tue, 2 Apr 2019 20:56:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqxfg0vsr0F2ddXuUC5GqDs2gInkPNc485nfQYb7yL/9A7s+maLd7bJ+i5JAg7R+497F7UQA X-Received: by 2002:a81:1b52:: with SMTP id b79mr61693949ywb.285.1554263801256; Tue, 02 Apr 2019 20:56:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263801; cv=none; d=google.com; s=arc-20160816; b=Sy46TpHFIL2KclLJ/FHBQ6ky4T8vEfolfFJjsjWut6W80UfkeCreq9AzvE1nVcW0My 176XwphC2I5gjWreGDfAwByZ0L9LxsRzrQoYtJINxpwqGwJQ4rDeNOL9JZhr9E3ZLVb9 wtFx4OGruqo0ZVh0tdOZVM46pJWuSdgdBWVNpnOH2c91FtbVhiftB6HKXmgoasDmDtbA QBkbn4M1NVF2WaH5+oHhQb4WlEgdIEYY1eHzpoAG0zU7ZxiZujVUu1grx3Gm0FzK8eVU o31SIrf+cLP85w86WCjSJSDitryrWxoXCsxOSeSVEpReMrZLeUVyJfuL4cg29k4WZjYR 41oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=cqLJBmieT/JY9FOcf60NXGKLtJWacSntKsw5Msw8hSU=; b=nD/Q9Jchqp2f6ClwDd+tTc6HPxfqyHDsO+UNWq1gXA9Svhkp+cMQc7B46hjURIoPlr eAnJM5hRVpprC0JeYrNaqbnETBeWtd7iTGKtGp6tX4wnT1pLDOZ/YyQo8gY6NbBnM9NL 0QihhVihr8f7SZYv4prHKP1qf+oFWe2xVlE2QT0dQaVQot5kNp0evMdNcbuOi9ULGq7G a1kGAXF3jIQfwfBpDMMiWFELouiqpOYgdm7muALN8jGqAaZKCaAMIPbyF76kx/ifX9UD dDzuYGC56hKg9dAUwyd0r5oete5fg7POCBcqIj6o1st1K5zwZRAEUo2h1Fhh3PG9r4jU E07Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TgvOpAzs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 09/26] target/m68k: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 5 ++- target/m68k/cpu.c | 2 +- target/m68k/helper.c | 87 ++++++++++++++++++++++------------------- target/m68k/op_helper.c | 15 ------- 4 files changed, 50 insertions(+), 59 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index f154565117..663c4c0307 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -543,8 +543,9 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) return (env->sr & SR_S) == 0 ? 1 : 0; } -int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 582e3a73b3..6f441bc973 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -269,7 +269,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; cc->gdb_write_register = m68k_cpu_gdb_write_register; - cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault; + cc->tlb_fill = m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_unassigned_access = m68k_cpu_unassigned_access; cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 3e26d337bf..9768b4517f 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -359,20 +359,7 @@ void m68k_switch_sp(CPUM68KState *env) env->current_sp = new_sp; } -#if defined(CONFIG_USER_ONLY) - -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - M68kCPU *cpu = M68K_CPU(cs); - - cs->exception_index = EXCP_ACCESS; - cpu->env.mmu.ar = address; - return 1; -} - -#else - +#if !defined(CONFIG_USER_ONLY) /* MMU: 68040 only */ static void print_address_zone(FILE *f, fprintf_function cpu_fprintf, @@ -804,11 +791,36 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } -int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +/* + * Notify CPU of a pending interrupt. Prioritization and vectoring should + * be handled by the interrupt controller. Real hardware only requests + * the vector when the interrupt is acknowledged by the CPU. For + * simplicitly we calculate it when the interrupt is signalled. + */ +void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +{ + CPUState *cs = CPU(cpu); + CPUM68KState *env = &cpu->env; + + env->pending_level = level; + env->pending_vector = vector; + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +#endif + +bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType qemu_access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { M68kCPU *cpu = M68K_CPU(cs); CPUM68KState *env = &cpu->env; + +#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; int access_type; @@ -821,32 +833,35 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, address & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } - if (rw == 2) { + if (qemu_access_type == MMU_INST_FETCH) { access_type = ACCESS_CODE; - rw = 0; } else { access_type = ACCESS_DATA; - if (rw) { + if (qemu_access_type == MMU_DATA_STORE) { access_type |= ACCESS_STORE; } } - if (mmu_idx != MMU_USER_IDX) { access_type |= ACCESS_SUPER; } ret = get_physical_address(&cpu->env, &physical, &prot, address, access_type, &page_size); - if (ret == 0) { + if (likely(ret == 0)) { address &= TARGET_PAGE_MASK; physical += address & (page_size - 1); tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } + + if (probe) { + return false; + } + /* page fault */ env->mmu.ssw = M68K_ATC_040; switch (size) { @@ -871,29 +886,19 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, if (!(access_type & ACCESS_STORE)) { env->mmu.ssw |= M68K_RW_040; } - env->mmu.ar = address; +#endif + cs->exception_index = EXCP_ACCESS; - return 1; + env->mmu.ar = address; + cpu_loop_exit_restore(cs, retaddr); } -/* Notify CPU of a pending interrupt. Prioritization and vectoring should - be handled by the interrupt controller. Real hardware only requests - the vector when the interrupt is acknowledged by the CPU. For - simplicitly we calculate it when the interrupt is signalled. */ -void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUState *cs = CPU(cpu); - CPUM68KState *env = &cpu->env; - - env->pending_level = level; - env->pending_vector = vector; - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } + m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } - #endif uint32_t HELPER(bitrev)(uint32_t x) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 76f439985a..d421614727 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -36,21 +36,6 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) #else -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = m68k_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - static void cf_rte(CPUM68KState *env) { uint32_t sp; From patchwork Wed Apr 3 03:43:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161660 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2516310jan; Tue, 2 Apr 2019 20:53:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqxXyjlY8MluVvGRNFROioIlwAe/dUqGaz4S5QPcLjSMmtVyvcjmYxvctQY2JXZ3mUkLvKrZ X-Received: by 2002:a25:c0c2:: with SMTP id c185mr2491688ybf.436.1554263609508; Tue, 02 Apr 2019 20:53:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263609; cv=none; d=google.com; s=arc-20160816; b=lt27KJyqHOp3B0jF/+jpBNuuY4othFMvJYJ0sUAmWAX5u5veD4PjOc9KpANz3AkbAz I9bzGTWrc1b/48ysQyOFUxJ9Z1ElieUjbmS9Phc4JiBgDThApzGErFlPdjwmBLU6Cg3i wq0xKOlmfaPDr4sJJGqaxgmko+uvuBX8BSP42aC2ZhxDTou6n8xS5hMOK0NdYjx7KF5N u7BnU8KB1jyNqlpAksNasI9SBwTvpqOhYax3rDMkEwu/OP8aP8u8cjnnO/9/H9Il5JwK koEOeQELh7VetGjFUQKZCYQbogE6EJ34xmndPBCC2hG7bKOY1cHQWRFSFnD68i2MeaHT +woQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RvZL9Bk1/BL1xpfiQMAt2J0TEi4VsVh2Sx8xG9Gdt3Q=; b=yVQoFe6gVtJEC2YmI4ntBU6PFBtGohxy6r6m1U5YHYIxtffPpiWr+8LoboPfFOZr0G 0bRdJrmQJmOGTx4zfjTyv9xMJrnY/vPUaKwx435iIpJsL2mxGhLITntq/D+jTwqGJpxj JYWZG1MTKfqhk7thrMlPVHH/TQb3/y8qLWlYAp0JtFEK1CVm4n5U8eFZoO9UOyyUXWid tYUJnzA7WGqF9lWmnP2/2iktkJUYOHOkk3H+tzxsyq91TeTHOhOWFcfqt+7ZYOJAGIXz L9cIOXxxw1xFU6ONlIiphjD3i/kQJ43u3E2TrT/TnpAGgyC8OxlCN47LsXix7szG9ags StEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=la5zkhz+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 10/26] target/microblaze: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E . Iglesias" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Edgar E. Iglesias Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 5 +- target/microblaze/cpu.c | 5 +- target/microblaze/helper.c | 142 +++++++++++++++++----------------- target/microblaze/op_helper.c | 19 ----- 4 files changed, 78 insertions(+), 93 deletions(-) -- 2.17.1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 792bbc97c7..8660c7673b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -375,8 +375,9 @@ static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) return MMU_KERNEL_IDX; } -int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #include "exec/cpu-all.h" diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 5596cd5485..0ea549910b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -304,9 +304,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = mb_cpu_set_pc; cc->gdb_read_register = mb_cpu_gdb_read_register; cc->gdb_write_register = mb_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; -#else + cc->tlb_fill = mb_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_transaction_failed = mb_cpu_transaction_failed; cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; #endif diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index bc753793ec..2d1d10e6cf 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -26,7 +26,78 @@ #define D(x) -#if defined(CONFIG_USER_ONLY) +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + +#ifndef CONFIG_USER_ONLY + uint32_t vaddr, paddr; + struct microblaze_mmu_lookup lu; + unsigned int hit; + int prot; + + if (mmu_idx == MMU_NOMMU_IDX) { + /* MMU disabled or not available. */ + address &= TARGET_PAGE_MASK; + prot = PAGE_BITS; + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + hit = mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx); + if (likely(hit)) { + vaddr = address & TARGET_PAGE_MASK; + paddr = lu.paddr + vaddr - lu.vaddr; + + qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", + mmu_idx, vaddr, paddr, lu.prot); + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* TLB miss. */ + if (probe) { + return false; + } + + qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", + mmu_idx, address); + + switch (lu.err) { + case ERR_PROT: + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; + env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + break; + case ERR_MISS: + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18; + env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10; + break; + default: + g_assert_not_reached(); + } + + if (cs->exception_index == EXCP_MMU) { + cpu_abort(cs, "recursive faults\n"); + } +#endif + + env->sregs[SR_EAR] = address; + cs->exception_index = EXCP_MMU; + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif + +#ifdef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs) { @@ -38,74 +109,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] = env->sregs[SR_PC]; } -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - cs->exception_index = 0xaa; - cpu_dump_state(cs, stderr, fprintf, 0); - return 1; -} - -#else /* !CONFIG_USER_ONLY */ - -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; - unsigned int hit; - int r = 1; - int prot; - - /* Translate if the MMU is available and enabled. */ - if (mmu_idx != MMU_NOMMU_IDX) { - uint32_t vaddr, paddr; - struct microblaze_mmu_lookup lu; - - hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx); - if (hit) { - vaddr = address & TARGET_PAGE_MASK; - paddr = lu.paddr + vaddr - lu.vaddr; - - qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", - mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); - r = 0; - } else { - env->sregs[SR_EAR] = address; - qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", - mmu_idx, address); - - switch (lu.err) { - case ERR_PROT: - env->sregs[SR_ESR] = rw == 2 ? 17 : 16; - env->sregs[SR_ESR] |= (rw == 1) << 10; - break; - case ERR_MISS: - env->sregs[SR_ESR] = rw == 2 ? 19 : 18; - env->sregs[SR_ESR] |= (rw == 1) << 10; - break; - default: - abort(); - break; - } - - if (cs->exception_index == EXCP_MMU) { - cpu_abort(cs, "recursive faults\n"); - } - - /* TLB miss. */ - cs->exception_index = EXCP_MMU; - } - } else { - /* MMU disabled or not available. */ - address &= TARGET_PAGE_MASK; - prot = PAGE_BITS; - tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); - r = 0; - } - return r; -} +#else void mb_cpu_do_interrupt(CPUState *cs) { diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index e23dcfdc20..b5dbb90d05 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -28,25 +28,6 @@ #define D(x) -#if !defined(CONFIG_USER_ONLY) - -/* Try to fill the TLB and return an exception if error. If retaddr is - * NULL, it means that the function was called in C code (i.e. not - * from generated code or from helper.c) - */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif - void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { int test = ctrl & STREAM_TEST; From patchwork Wed Apr 3 03:43:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161668 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2519737jan; Tue, 2 Apr 2019 20:59:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwXxzsylSlqwWQn7K+XKvvRU96P/B12v5qGeE1IzYgovUna3X2/RFMsSs8ptOuq/EThKUaF X-Received: by 2002:a25:56d4:: with SMTP id k203mr59689530ybb.475.1554263973506; Tue, 02 Apr 2019 20:59:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263973; cv=none; d=google.com; s=arc-20160816; b=dJ+z4tEOZWgHqZqvNI5703MQatTPqYn2ik6LE2TBmZn79Po4HqkvXkxL/XFyu/q5QM YASLYyw4lLrNVLpYhyBu2fU5KSiZnysxzuW7Bu+9E1nzYulQykhrk3ZzFd8BOuY2G0Pm 3sMQhiidOXWA4sG8RHkAJNakMp8Wwx5aDqEBgtIo5raMEYQHVAwCaZQbhfjT9Vm7UNoe i+BQ6vaJQsWf72qEkv4DT9ueMVpizk3YGUD1nUf5sqfstjpttm1VJbnK+MfztXcIU97H I8Q/Wo7zuT7thaYvfku7318muULgfSmgyhQloSRpHoRVOdYhDoTef6tAa2aW/2DQ0pVK nYmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hsT/4r55/BmYXvm+N7+ZWx+INVnPxar+m3RehQ8v76k=; b=yqpz8PcUnVNDHfsry6MCulRqvpf4CYwWy9IhzZ4TJdleJJB6r6TS9/L0L5831/lNJd 01UI6NCmAZ4r5L3ynILZgeRzxbotpZS2RSm9N5jGt+b0Wj4E/C7gjmKsqyflAngs+O5v rjxdYLw5S/kEaFhfuHwHZn10SPmTzkRXV+OwUNLJxzsUyrON9l3/3mDTuuOaYLZo2Yry PK0l5hF5mHvsYx+EgZaO4Ctnnt8NMXQDTVL24lBCsvWRS6Q6AMxTVEY9Myb0S9HKjIhN wTDjUlUGeOZJjySM3Vrtr7xCeftQVOTZFv80WLwtjL1l5GeTtXjA9jV4E7MzYoCp8wxa EVyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QWQGkT3A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 11/26] target/mips: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Aleksandar Markovic Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Note that env->active_tc.PC is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from do_raise_exception_err. Cc: Aleksandar Markovic Cc: Aleksandar Rikalo Signed-off-by: Richard Henderson --- target/mips/internal.h | 5 +- target/mips/cpu.c | 5 +- target/mips/helper.c | 115 +++++++++++++++++++--------------------- target/mips/op_helper.c | 15 ------ 4 files changed, 61 insertions(+), 79 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/mips/internal.h b/target/mips/internal.h index 8f6fc919d5..5ec9d0bd65 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -203,8 +203,9 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /* op_helper.c */ uint32_t float_class_s(uint32_t arg, float_status *fst); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e217fb3e36..ebdb834b97 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -197,9 +197,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; cc->gdb_read_register = mips_cpu_gdb_read_register; cc->gdb_write_register = mips_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = mips_cpu_handle_mmu_fault; -#else + cc->tlb_fill = mips_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access = mips_cpu_unassigned_access; cc->do_unaligned_access = mips_cpu_do_unaligned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; diff --git a/target/mips/helper.c b/target/mips/helper.c index c44cdca3b5..7fe0ba4754 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -874,85 +874,82 @@ refill: #endif #endif -int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) + int ret = TLBRET_NOMATCH; + +#ifndef CONFIG_USER_ONLY hwaddr physical; int prot; - int access_type; -#endif - int ret = 0; + int mips_access_type = ACCESS_INT; -#if 0 - log_cpu_state(cs, 0); -#endif qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", - __func__, env->active_tc.PC, address, rw, mmu_idx); + "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ - access_type = ACCESS_INT; - ret = get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); - switch (ret) { - case TLBRET_MATCH: + ret = get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); + if (ret == TLBRET_MATCH) { qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx " prot %d\n", __func__, address, physical, prot); - break; - default: - qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d\n", __func__, address, - ret); - break; - } - if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) -#endif - { -#if !defined(CONFIG_USER_ONLY) -#if !defined(TARGET_MIPS64) - if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { - /* - * Memory reads during hardware page table walking are performed - * as if they were kernel-mode load instructions. - */ - int mode = (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &= ~MIPS_HFLAG_KSU; - ret_walker = page_table_walk_refill(env, address, rw, mmu_idx); - env->hflags |= mode; - if (ret_walker) { - ret = get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); - if (ret == TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - return ret; - } - } - } -#endif -#endif - raise_mmu_exception(env, address, rw, ret); - ret = 1; + return true; } - return ret; + qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d\n", + __func__, address, ret); + +#ifndef TARGET_MIPS64 + if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { + /* + * Memory reads during hardware page table walking are performed + * as if they were kernel-mode load instructions. + */ + int mode = (env->hflags & MIPS_HFLAG_KSU); + bool ret_walker; + + env->hflags &= ~MIPS_HFLAG_KSU; + ret_walker = page_table_walk_refill(env, address, access_type, mmu_idx); + env->hflags |= mode; + + if (ret_walker) { + ret = get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); + if (ret == TLBRET_MATCH) { + tlb_set_page(cs, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + } + } +#endif + + if (probe) { + return false; + } +#endif /* !CONFIG_USER_ONLY */ + + raise_mmu_exception(env, address, access_type, ret); + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } -#if !defined(CONFIG_USER_ONLY) hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) { hwaddr physical; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5b93..6d86912958 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2669,21 +2669,6 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, do_raise_exception_err(env, excp, error_code, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} - void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int unused, unsigned size) From patchwork Wed Apr 3 03:43:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161658 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2516156jan; Tue, 2 Apr 2019 20:53:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkrTsdyHNYfo0XefD8m3OLk4PJE6V4OjJso8gOs4jJuQky2F9vYYmPXho0fpy25tTbL3Xt X-Received: by 2002:a25:2455:: with SMTP id k82mr23363699ybk.136.1554263593643; Tue, 02 Apr 2019 20:53:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263593; cv=none; d=google.com; s=arc-20160816; b=0ULm8qIYUuW+AO/lCtgoRGWkl/ehA2ku7NVMc3r/RYV57yYHxxDTE58EGvdXP5M5cr OY1wasQ0JNKIFVGCrnjRNbIM+3lW0DDobbbc40BMtUl2fhc5ocHNm79NF3E9mqW/wYeH /tWr/WUwLk3bopPjjp6qyr0AijGmGvT0j3iJrhuaeskXqyBTgmDpLNQS4BDBLCl2SiJQ XKj/JA29v/T2pSRmrxScihD3HoMcqCMDygItbfWOlZgeQ0UZP2AgvLfptzqGFA13Qa/P 5i76shC15MP4ftywUA6TQrhl4FnTl6xAgSl+9B3RI/z5+TjCWw5JLQS6XN4eC1hlzs+W +23w== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 12/26] target/moxie: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anthony Green Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Anthony Green Signed-off-by: Richard Henderson --- target/moxie/cpu.h | 5 ++-- target/moxie/cpu.c | 5 ++-- target/moxie/helper.c | 61 ++++++++++--------------------------------- 3 files changed, 19 insertions(+), 52 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index 080df4ee6f..a82c2caf30 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -140,7 +140,8 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc, *flags = 0; } -int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif /* MOXIE_CPU_H */ diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 46434e65ba..02b2b47574 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -112,9 +112,8 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) cc->do_interrupt = moxie_cpu_do_interrupt; cc->dump_state = moxie_cpu_dump_state; cc->set_pc = moxie_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = moxie_cpu_handle_mmu_fault; -#else + cc->tlb_fill = moxie_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug; cc->vmsd = &vmstate_moxie_cpu; #endif diff --git a/target/moxie/helper.c b/target/moxie/helper.c index f3d8ee7d6b..216cef057e 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,18 +26,10 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" -/* Try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - - ret = moxie_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - cpu_loop_exit_restore(cs, retaddr); - } + moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } void helper_raise_exception(CPUMoxieState *env, int ex) @@ -85,53 +77,29 @@ void helper_debug(CPUMoxieState *env) cpu_loop_exit(cs); } -#if defined(CONFIG_USER_ONLY) - -void moxie_cpu_do_interrupt(CPUState *cs) -{ - CPUState *cs = CPU(moxie_env_get_cpu(env)); - - cs->exception_index = -1; -} - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - MoxieCPU *cpu = MOXIE_CPU(cs); - - cs->exception_index = 0xaa; - cpu->env.debug1 = address; - cpu_dump_state(cs, stderr, fprintf, 0); - return 1; -} - -#else /* !CONFIG_USER_ONLY */ - -int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool moxie_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MoxieCPU *cpu = MOXIE_CPU(cs); CPUMoxieState *env = &cpu->env; MoxieMMUResult res; int prot, miss; - target_ulong phy; - int r = 1; address &= TARGET_PAGE_MASK; prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx); - if (miss) { - /* handle the miss. */ - phy = 0; - cs->exception_index = MOXIE_EX_MMU_MISS; - } else { - phy = res.phy; - r = 0; + miss = moxie_mmu_translate(&res, env, address, access_type, mmu_idx); + if (likely(!miss)) { + tlb_set_page(cs, address, res.phy, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; } - tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); - return r; -} + cs->exception_index = MOXIE_EX_MMU_MISS; + cpu_loop_exit_restore(cs, retaddr); +} void moxie_cpu_do_interrupt(CPUState *cs) { @@ -156,4 +124,3 @@ hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phy; } -#endif From patchwork Wed Apr 3 03:43:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161661 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2517881jan; Tue, 2 Apr 2019 20:56:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqzLceGbOlpBWR7DmeyDx1KkEBdufUcsghZiAQpnveDy5Bk/lVvYHoSq/X+ZwA/RibEEc0fd X-Received: by 2002:a0d:e892:: with SMTP id r140mr62346434ywe.373.1554263773819; Tue, 02 Apr 2019 20:56:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263773; cv=none; d=google.com; s=arc-20160816; b=Rphuu0iR2N/nbW1UE5L6v//orJojKFrTFwVD+bflpAl4PCtiuRdJCv7YduiRMiFxfJ zP03dkEqS1Q0BDy2s7Oo9JdQAODds6Y6SsuAxtPK/2IUi9w/WB2yXoUumPwFfj5HnJtH MlhmkTCR7C+oQkBif9IFZ3bKsymQNEyNqSzRBS3iylAVBVeCGCiPGWqETKQWFlYfoI5j zKbl8TC19x+YyK1tXIu1FxBTpWqeBn+e5KCXf3jQggXS6geVa13f/n92nIOzOZLkRNYO hpSNz6w5cLKiv9KE/DMLbPXvHAnjkr1UK90b0HliYk5TdgLoHb4jxySkaKkc0YFQLV+A mPLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=14DUdrN8vQ8XKZexpOz5wlHVON6RFAW8MGdiOZQ7yWU=; b=MKrqAFnrH5YcDX67kvfGTdEHqYcTfi4vElpKcGflH8Cxj0La1tjnfIjD/EX5ClXWgq UPecLMUP/+bPcszXv7ywORlEzHzY6i28HgZkIYpTj9Lk/sATfZ50hCweJiy3lFOLPftq ikerqRBlynfC79i3pA4oXgb7fNaVZ0JC3TPi2W7UR9EWIWok3H9OFZpF7RVE9h4HmYcU CM4iR9/R0GU55AXaCeV+/+FtCr0BRlekP5Dn/RFD2sOUXBKONoIw3sINdcpc/C3g03LM g6uCnOOsVUaJ9cJRlopdwDbjg7iAiqTfSaIdhGz+MNuWJL7HtEqhssv9aL9EKzUu33Fu qtdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sRKWGlSo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 13/26] target/nios2: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Chris Wulff Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Chris Wulff Cc: Marek Vasut Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 5 +- target/nios2/cpu.c | 5 +- target/nios2/helper.c | 181 ++++++++++++++++++++---------------------- target/nios2/mmu.c | 12 --- 4 files changed, 92 insertions(+), 111 deletions(-) -- 2.17.1 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 047f3764b7..b3e9595457 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -251,8 +251,9 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } -int nios2_cpu_handle_mmu_fault(CPUState *env, vaddr address, int size, - int rw, int mmu_idx); +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); static inline int cpu_interrupts_enabled(CPUNios2State *env) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fbfaa2ce26..186af4913d 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -200,9 +200,8 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->disas_set_info = nios2_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = nios2_cpu_handle_mmu_fault; -#else + cc->tlb_fill = nios2_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = nios2_cpu_do_unaligned_access; cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug; #endif diff --git a/target/nios2/helper.c b/target/nios2/helper.c index a8b8ec662a..d075ef1965 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -36,17 +36,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[R_EA] = env->regs[R_PC] + 4; } -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - cs->exception_index = 0xaa; - /* Page 0x1000 is kuser helper */ - if (address < 0x1000 || address >= 0x2000) { - cpu_dump_state(cs, stderr, fprintf, 0); - } - return 1; -} - #else /* !CONFIG_USER_ONLY */ void nios2_cpu_do_interrupt(CPUState *cs) @@ -190,89 +179,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) } } -static int cpu_nios2_handle_virtual_page( - CPUState *cs, target_ulong address, int rw, int mmu_idx) -{ - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - target_ulong vaddr, paddr; - Nios2MMULookup lu; - unsigned int hit; - hit = mmu_translate(env, &lu, address, rw, mmu_idx); - if (hit) { - vaddr = address & TARGET_PAGE_MASK; - paddr = lu.paddr + vaddr - lu.vaddr; - - if (((rw == 0) && (lu.prot & PAGE_READ)) || - ((rw == 1) && (lu.prot & PAGE_WRITE)) || - ((rw == 2) && (lu.prot & PAGE_EXEC))) { - - tlb_set_page(cs, vaddr, paddr, lu.prot, - mmu_idx, TARGET_PAGE_SIZE); - return 0; - } else { - /* Permission violation */ - cs->exception_index = (rw == 0) ? EXCP_TLBR : - ((rw == 1) ? EXCP_TLBW : - EXCP_TLBX); - } - } else { - cs->exception_index = EXCP_TLBD; - } - - if (rw == 2) { - env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D; - } else { - env->regs[CR_TLBMISC] |= CR_TLBMISC_D; - } - env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr = env->regs[CR_PTEADDR]; - env->regs[CR_BADADDR] = address; - return 1; -} - -int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - if (cpu->mmu_present) { - if (MMU_SUPERVISOR_IDX == mmu_idx) { - if (address >= 0xC0000000) { - /* Kernel physical page - TLB bypassed */ - address &= TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } else if (address >= 0x80000000) { - /* Kernel virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx); - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx); - } - } else { - if (address >= 0x80000000) { - /* Illegal access from user mode */ - cs->exception_index = EXCP_SUPERA; - env->regs[CR_BADADDR] = address; - return 1; - } else { - /* User virtual page */ - return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx); - } - } - } else { - /* No MMU */ - address &= TARGET_PAGE_MASK; - tlb_set_page(cs, address, address, PAGE_BITS, - mmu_idx, TARGET_PAGE_SIZE); - } - - return 0; -} - hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -308,4 +214,91 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } +#endif /* CONFIG_USER_ONLY */ + +bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + Nios2CPU *cpu = NIOS2_CPU(cs); + CPUNios2State *env = &cpu->env; + unsigned int excp = EXCP_TLBD; + +#ifndef CONFIG_USER_ONLY + target_ulong vaddr, paddr; + Nios2MMULookup lu; + unsigned int hit; + + if (!cpu->mmu_present) { + /* No MMU */ + address &= TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + if (MMU_SUPERVISOR_IDX == mmu_idx) { + if (address >= 0xC0000000) { + /* Kernel physical page - TLB bypassed */ + address &= TARGET_PAGE_MASK; + tlb_set_page(cs, address, address, PAGE_BITS, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + } else { + if (address >= 0x80000000) { + /* Illegal access from user mode */ + if (probe) { + return false; + } + cs->exception_index = EXCP_SUPERA; + env->regs[CR_BADADDR] = address; + cpu_loop_exit_restore(cs, retaddr); + } + } + + /* Virtual page. */ + hit = mmu_translate(env, &lu, address, access_type, mmu_idx); + if (hit) { + vaddr = address & TARGET_PAGE_MASK; + paddr = lu.paddr + vaddr - lu.vaddr; + + if (((access_type == MMU_DATA_LOAD) && (lu.prot & PAGE_READ)) || + ((access_type == MMU_DATA_STORE) && (lu.prot & PAGE_WRITE)) || + ((access_type == MMU_INST_FETCH) && (lu.prot & PAGE_EXEC))) { + tlb_set_page(cs, vaddr, paddr, lu.prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + + /* Permission violation */ + excp = (access_type == MMU_DATA_LOAD ? EXCP_TLBR : + access_type == MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX); + } + + if (probe) { + return false; + } + + if (access_type == MMU_INST_FETCH) { + env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D; + } else { + env->regs[CR_TLBMISC] |= CR_TLBMISC_D; + } + env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK; + env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr = env->regs[CR_PTEADDR]; #endif /* !CONFIG_USER_ONLY */ + + cs->exception_index = excp; + env->regs[CR_BADADDR] = address; + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 69b71cba4a..db85c8b7c4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -35,18 +35,6 @@ #define MMU_LOG(x) #endif -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = nios2_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - void mmu_read_debug(CPUNios2State *env, uint32_t rn) { switch (rn) { From patchwork Wed Apr 3 03:43:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161663 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2517983jan; Tue, 2 Apr 2019 20:56:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqybGKCnED5KXrFXz30PR4kfkIblMBOjAmhcwy6aAVBxl8hkMRWPKJj5G9rXBqLJr8LVbeIG X-Received: by 2002:a0d:df83:: with SMTP id i125mr44883991ywe.94.1554263784971; Tue, 02 Apr 2019 20:56:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263784; cv=none; d=google.com; s=arc-20160816; b=CW9doyn/xHhQJrqUD6vEYJo2YNPkVn3eUxwOg7Ee7j3IXn7cahrMuNuZYNj358nrnC EeJQG1v89vViyXIY78s6NsqJ3VaBcsfDeBJ8BPAeZjx7u2MiCoTVdn+RgdyRgUS0lfOG OaD+aTAMH9GQLMrkV6fMOAPQB0CZKnaFb5m7eHFr0ML19QTMbfCIFWqmAl+IMkp0nXnP nDCzhcUwIa89OB5cla+2bHl5A0nSx3AfnMjoTQp3N9k66TLvlx31TfbqeLcGWZpLpQ6+ zjjU6456H9d7KgyEsalFE3ZOBZhRC60e7LMRe389Gt8+Kxu7fA57+qnyQwTEgvPplrek 3W2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=384FujFXDMGyrNVbgb6dXYKV7liMukTd1wxhqjqEOUQ=; b=e89fPaJ8qq/b/JTuLzrhp527b6/RWp0DiL8IV8IpygmEIvq+PgpbEIUOnfyHXLEZLH mUWk+sUqWbTD7NhWPtKg5DLwdL468LU9NeKz8g0/5VSoWNv5WY/nX3Ft2EWB6tDJl5V2 lQfcVLHR+b0pGF0Arn3CfSJyFePwCUCLp6DFONNtoYu/Pqb//kCRlCCDKiPnFB87NnTK DmkZOzJfZLOXq2tuQNCDCF+3KvCmuQi+egbBELXUUwRY5yBcXAdYWLc/A3V8iGM4zhS5 p9OKnpBeFnsQc/xVzPlkS9O3QgFOYFY+zGXSzXYnMRU3nIsRf/6J120V2mwqrtZcj7aK QKBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cdyH4SeE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 14/26] target/openrisc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 5 ++-- target/openrisc/cpu.c | 5 ++-- target/openrisc/mmu.c | 65 ++++++++++++++++++++++--------------------- 3 files changed, 39 insertions(+), 36 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f1b31bc24a..cbd7c97230 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -345,8 +345,9 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); -int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); int print_insn_or1k(bfd_vma addr, disassemble_info *info); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 541b2a66c7..d38cd24275 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -148,9 +148,8 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; cc->gdb_write_register = openrisc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault; -#else + cc->tlb_fill = openrisc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; #endif diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index e7d5219e11..991f3fafe8 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -107,16 +107,42 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, cpu->env.lock_addr = -1; } -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { -#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); - raise_mmu_exception(cpu, address, EXCP_DPF); - return 1; -#else - g_assert_not_reached(); + int excp = EXCP_DPF; + +#ifndef CONFIG_USER_ONLY + int prot; + hwaddr phys_addr; + + if (mmu_idx == MMU_NOMMU_IDX) { + /* The mmu is disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); + excp = 0; + } else { + bool super = mmu_idx == MMU_SUPERVISOR_IDX; + int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC + : access_type == MMU_DATA_STORE ? PAGE_WRITE + : PAGE_READ); + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); + } + + if (likely(excp == 0)) { + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + phys_addr & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } #endif + + raise_mmu_exception(cpu, addr, excp); + cpu_loop_exit_restore(cs, retaddr); } #ifndef CONFIG_USER_ONLY @@ -156,29 +182,6 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int prot, excp; - hwaddr phys_addr; - - if (mmu_idx == MMU_NOMMU_IDX) { - /* The mmu is disabled; lookups never fail. */ - get_phys_nommu(&phys_addr, &prot, addr); - excp = 0; - } else { - bool super = mmu_idx == MMU_SUPERVISOR_IDX; - int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC - : access_type == MMU_DATA_STORE ? PAGE_WRITE - : PAGE_READ); - excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); - } - - if (unlikely(excp)) { - raise_mmu_exception(cpu, addr, excp); - cpu_loop_exit_restore(cs, retaddr); - } - - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr); } #endif From patchwork Wed Apr 3 03:43:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161659 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2516184jan; Tue, 2 Apr 2019 20:53:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqybGJvdwlmt3hgGTy6Zb6P1hvkHeXfFtR0v6Q7ARzgGdIQDRlEF1NngM0gIJvObYTEoJR46 X-Received: by 2002:a25:10c3:: with SMTP id 186mr60554657ybq.375.1554263595814; Tue, 02 Apr 2019 20:53:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263595; cv=none; d=google.com; s=arc-20160816; b=IweZf5YZIKuSDZoHi73ZpZJSl8gzNJj35EdAnnqeZlJjhED0eP9lxH1jYKGkrMkT/G LiaNqlWrnoy1IsGFtmGx621lhNOij0c4nH07oIFa7Nhq2MmaJysNHrx9dkJHo57WrURl ihabBhjcQMR8bJ8OJzYO4N0ythBBBCLQmha6MM5nkNpu83JW5jE3PWcKO6/6/QU4AOmI QvWXKDimW4Qmn4Zx3JVwAcDryj5ZYP/c6tqYJUjxNcF6KmGxvHT7xuqFOXynAMYNURo8 Ha8UFQ8LctKHXdAzKPrxKiVzsHDHc1A9xwkG+0+6T2nWQXMgOVbjFVnAV/ccOrtjeT6x Xrgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=INYoMOC2BML1R/tNbeYBbum+91nSf0ZPyhXaQqqzn14=; b=cf5Xw83itPDlm4B6S9oDFgbJxAXVMdSmzSoBfFZQWmanFfVampqfayon623LxUlZnp LIKiyca5EzGaCUA0OH1yMM86OxzzHfi0vwsZkn2hkZemaJrgsi9JzhyR/5XgqM48KVVR 37/WjBr0qq/1gNG3qMP0sBAkai6iqvCVBFLMybo7RJfwEZsHhjZ/3HTHzjXQIMEruxqg 1bUuo2Zh6kG9IVZ5ucQpUsni/ONCfnVPlaIkkim/1VUotittfxjrqjQs50nzzWfd7wLE /mgw3r2AuvM+RcPlsFpQqsIP1TGGAJx80xaVkyACL2ye8Te+Gv8PTVx5fyykMGME9IVx Q/kg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i0hOnnr0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 15/26] target/ppc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-ppc@nongnu.org Cc: David Gibson Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 7 +++---- target/ppc/mmu_helper.c | 19 +++++++++++++------ target/ppc/translate_init.inc.c | 5 ++--- target/ppc/user_only_helper.c | 14 ++++++++------ 4 files changed, 26 insertions(+), 19 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0707177584..da73d3ee5b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1297,10 +1297,9 @@ void ppc_translate_init(void); is returned if the signal was handled by the virtual CPU. */ int cpu_ppc_signal_handler (int host_signum, void *pinfo, void *puc); -#if defined(CONFIG_USER_ONLY) -int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); -#endif +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 4a6be4d63b..6865c0ca37 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3026,12 +3026,9 @@ void helper_check_tlb_flush_global(CPUPPCState *env) /*****************************************************************************/ -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); @@ -3044,7 +3041,17 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, ret = cpu_ppc_handle_mmu_fault(env, addr, access_type, mmu_idx); } if (unlikely(ret != 0)) { + if (probe) { + return false; + } raise_exception_err_ra(env, cs->exception_index, env->error_code, retaddr); } + return true; +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 0bd555eb19..39f37bba5b 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10545,9 +10545,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = ppc_cpu_gdb_read_register; cc->gdb_write_register = ppc_cpu_gdb_write_register; cc->do_unaligned_access = ppc_cpu_do_unaligned_access; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault; -#else + cc->tlb_fill = ppc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_ppc_cpu; #endif diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 2f1477f102..683c03390d 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -20,21 +20,24 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" -int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) + +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int exception, error_code; - if (rw == 2) { + if (access_type == MMU_INST_FETCH) { exception = POWERPC_EXCP_ISI; error_code = 0x40000000; } else { exception = POWERPC_EXCP_DSI; error_code = 0x40000000; - if (rw) { + if (access_type == MMU_DATA_STORE) { error_code |= 0x02000000; } env->spr[SPR_DAR] = address; @@ -42,6 +45,5 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, } cs->exception_index = exception; env->error_code = error_code; - - return 1; + cpu_loop_exit_restore(cs, retaddr); } From patchwork Wed Apr 3 03:43:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161665 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2518761jan; Tue, 2 Apr 2019 20:57:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqz2j/KgyRsXDeBZOPUCuf5OuMWXk3Xb6vm4JLtHDpMKx5CZz8Ip5d36afyS0liFl4dv2SRq X-Received: by 2002:a0d:e613:: with SMTP id p19mr57824135ywe.96.1554263868048; Tue, 02 Apr 2019 20:57:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263868; cv=none; d=google.com; s=arc-20160816; b=KFJfbN76V0HLQOXpWoW9bqgxQbNs73fyVyr7vvUiqp4K5EI85rbG5NNShOfZSPeA4T K2AhIc3DfPYmooFXJwDo03u1mdnMbBdCcf9En8dynnKbRilo+e7+MJVdHnslkj/iE8Xb BVd328H51JH6O3/7e4hlTLFggGHrjwHCXdTc3g+zs1Jch7ijdA9LH/aQIpX/jKPhnF9S 36Hcx83mOcElYJhYnryHR6sASwkKMZVlabrmukmyVYcvn5ALNhX8Lh72XB3lE8f5rwK0 k/rC4NYMhyfw0Cgbfib5yywfije8OYMshoA+kqFfo0uha9pEbNlLweJAIATczpHPHrM7 axOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=w70bbHQzT+7HnMGIXg0cJi7OJv7Pp3pD0PUOZFKz1Ws=; b=Ao7iyE5ZhkuLKQeLbiQeZskK00b3QACYeHbETO8KK9zPDK+1mTbWQltjcfFahlSDyi EUWjLujTVSpwnzzAIZXDVFWJJ4eP5JvJLt7+FYVTeLPWA+xrS+EXYVX/dr9yWzSCsZPr QUoTkTMfgr6YEe/ozqotLy1C0bLBy4Fp3GOjdTkxSDVn4ypmEcz9KaVKgrsNZLf7RFp6 Gx+HcVufxtWW2+VG6ex4vjptQBtdLfnikg3qEp4a6gJHrOSihiBFOTx+dTznEIvriyeJ rZ0ZNVaEiuVvySDVXMQneCm8w3k0kTH41JK6Bge6NvgTfSfM7GyYnbltnZ+4gBPgjd1B 0WGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="PS/U3kRJ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 16/26] target/riscv: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Cc: qemu-riscv@nongnu.org Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu.c | 5 ++--- target/riscv/cpu_helper.c | 46 ++++++++++++++++++--------------------- 3 files changed, 26 insertions(+), 30 deletions(-) -- 2.17.1 Reviewed-by: Alistair Francis diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 20bce8742e..40c1254408 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -261,8 +261,9 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d61bce6d55..e9f569c665 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -355,9 +355,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = riscv_cpu_handle_mmu_fault; -#else + cc->tlb_fill = riscv_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..2535435260 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -379,53 +379,49 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_raise_exception(env, cs->exception_index, retaddr); } -/* called by qemu's softmmu to fill the qemu tlb */ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret; - ret = riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret == TRANSLATE_FAIL) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - riscv_raise_exception(env, cs->exception_index, retaddr); - } + riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } - #endif -int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { +#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr pa = 0; int prot; -#endif int ret = TRANSLATE_FAIL; - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \ - %d\n", __func__, env->pc, address, rw, mmu_idx); + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); -#if !defined(CONFIG_USER_ONLY) - ret = get_physical_address(env, &pa, &prot, address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx + " prot %d\n", __func__, address, ret, pa, prot); + if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) { + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { ret = TRANSLATE_FAIL; } if (ret == TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); - } else if (ret == TRANSLATE_FAIL) { - raise_mmu_exception(env, address, rw); + return true; + } else if (probe) { + return false; + } else { + raise_mmu_exception(env, address, access_type); + riscv_raise_exception(env, cs->exception_index, retaddr); } #else - switch (rw) { + switch (access_type) { case MMU_INST_FETCH: cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; break; @@ -436,8 +432,8 @@ int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; break; } + cpu_loop_exit_restore(cs, retaddr); #endif - return ret; } /* From patchwork Wed Apr 3 03:43:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161671 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2521951jan; Tue, 2 Apr 2019 21:02:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqzfEiOt/Ffbz0RuIO6olsaBxl0mZ+FJtsYnV2NNriLgQcAGuGARjwTHLF0pclVEeE4pQ02C X-Received: by 2002:a5b:642:: with SMTP id o2mr59805445ybq.32.1554264143597; Tue, 02 Apr 2019 21:02:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554264143; cv=none; d=google.com; s=arc-20160816; b=pGCMH/mQbJ4YqSQbE/fbRpMMjo57stdfOvaKw1S2lnntyazi37Rcv22gWLwO4NJ0C0 +P+gWHEg2qVWU2gd6QSPSuWkW75RHeDPGb5SS0jDdkGLzALG0niDjeAL7k1cnAojvZT1 Md324fHz77fuJPmE1d1KRNK4FNO3skAqkhFt4AtKhwF6sgp3qouxDazOgEqWmdmEzCxv B7NZdS5w26m9DLS1S/RxYW2PN98fUGcuBfizZyTamTzRY39Hsy7S416UFzyT/n3t5shp lMUVLiBWAC0u4wWzr4/NiuYogPDApBBl4OHlUSYNhOa/zcbX1I3X5cMNIXmxZpaLoxzx 4Mkg== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 17/26] target/s390x: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: qemu-s390x@nongnu.org Cc: Cornelia Huck Cc: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h | 5 +- target/s390x/cpu.c | 5 +- target/s390x/excp_helper.c | 156 +++++++++++++++++++++---------------- target/s390x/mem_helper.c | 29 ------- 4 files changed, 94 insertions(+), 101 deletions(-) -- 2.17.1 diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 5f7901da5e..424e8ce406 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -263,8 +263,9 @@ ObjectClass *s390_cpu_class_by_name(const char *name); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); -int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 698dd9cb82..9dd94b1395 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -471,9 +471,8 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = s390_cpu_set_pc; cc->gdb_read_register = s390_cpu_gdb_read_register; cc->gdb_write_register = s390_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; -#else + cc->tlb_fill = s390_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; cc->vmsd = &vmstate_s390_cpu; cc->write_elf64_note = s390_cpu_write_elf64_note; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index bc781c14c3..aeeaeb523d 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -74,20 +74,14 @@ void s390_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - S390CPU *cpu = S390_CPU(cs); - - trigger_pgm_exception(&cpu->env, PGM_ADDRESSING, ILEN_AUTO); - /* On real machines this value is dropped into LowMem. Since this - is userland, simply put this someplace that cpu_loop can find it. */ - cpu->env.__excp_addr = address; - return 1; -} - #else /* !CONFIG_USER_ONLY */ +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} + static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) { switch (mmu_idx) { @@ -102,61 +96,6 @@ static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) } } -int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, - int rw, int mmu_idx) -{ - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - target_ulong vaddr, raddr; - uint64_t asc; - int prot; - - qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", - __func__, orig_vaddr, rw, mmu_idx); - - vaddr = orig_vaddr; - - if (mmu_idx < MMU_REAL_IDX) { - asc = cpu_mmu_idx_to_asc(mmu_idx); - /* 31-Bit mode */ - if (!(env->psw.mask & PSW_MASK_64)) { - vaddr &= 0x7fffffff; - } - if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) { - return 1; - } - } else if (mmu_idx == MMU_REAL_IDX) { - /* 31-Bit mode */ - if (!(env->psw.mask & PSW_MASK_64)) { - vaddr &= 0x7fffffff; - } - if (mmu_translate_real(env, vaddr, rw, &raddr, &prot)) { - return 1; - } - } else { - abort(); - } - - /* check out of RAM access */ - if (!address_space_access_valid(&address_space_memory, raddr, - TARGET_PAGE_SIZE, rw, - MEMTXATTRS_UNSPECIFIED)) { - qemu_log_mask(CPU_LOG_MMU, - "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", - __func__, (uint64_t)raddr, (uint64_t)ram_size); - trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); - return 1; - } - - qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", - __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); - - tlb_set_page(cs, orig_vaddr & TARGET_PAGE_MASK, raddr, prot, - mmu_idx, TARGET_PAGE_SIZE); - - return 0; -} - static void do_program_interrupt(CPUS390XState *env) { uint64_t mask, addr; @@ -577,3 +516,86 @@ void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, } #endif /* CONFIG_USER_ONLY */ + +bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + S390CPU *cpu = S390_CPU(cs); + +#ifndef CONFIG_USER_ONLY + CPUS390XState *env = &cpu->env; + target_ulong vaddr, raddr; + uint64_t asc; + int prot, fail; + + qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + vaddr = address; + + if (mmu_idx < MMU_REAL_IDX) { + asc = cpu_mmu_idx_to_asc(mmu_idx); + /* 31-Bit mode */ + if (!(env->psw.mask & PSW_MASK_64)) { + vaddr &= 0x7fffffff; + } + fail = mmu_translate(env, vaddr, access_type, asc, &raddr, &prot, true); + } else if (mmu_idx == MMU_REAL_IDX) { + /* 31-Bit mode */ + if (!(env->psw.mask & PSW_MASK_64)) { + vaddr &= 0x7fffffff; + } + fail = mmu_translate_real(env, vaddr, access_type, &raddr, &prot); + } else { + g_assert_not_reached(); + } + + /* check out of RAM access */ + if (!fail && + !address_space_access_valid(&address_space_memory, raddr, + TARGET_PAGE_SIZE, access_type, + MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(CPU_LOG_MMU, + "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", + __func__, (uint64_t)raddr, (uint64_t)ram_size); + trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); + fail = 1; + } + + if (!fail) { + qemu_log_mask(CPU_LOG_MMU, + "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", + __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); + tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot, + mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } +#else + trigger_pgm_exception(&cpu->env, PGM_ADDRESSING, ILEN_AUTO); + /* + * On real machines this value is dropped into LowMem. Since this + * is userland, simply put this someplace that cpu_loop can find it. + */ + cpu->env.__excp_addr = address; +#endif + + cpu_restore_state(cs, retaddr, true); + + /* + * Note that handle_mmu_fault sets ilen to either 2 (for code) + * or AUTO (for data). We can resolve AUTO now, as if it was + * set to UNWIND -- that will have been done via assignment + * in cpu_restore_state. Otherwise re-examine access_type. + */ + if (access_type == MMU_INST_FETCH) { + CPUS390XState *env = cs->env_ptr; + env->int_pgm_ilen = 2; + } + + cpu_loop_exit(cs); +} + diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index d54907696d..0c5ca36823 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -34,35 +34,6 @@ /*****************************************************************************/ /* Softmmu support */ -#if !defined(CONFIG_USER_ONLY) - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret = s390_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret != 0)) { - cpu_restore_state(cs, retaddr, true); - - /* - * Note that handle_mmu_fault sets ilen to either 2 (for code) - * or AUTO (for data). We can resolve AUTO now, as if it was - * set to UNWIND -- that will have been done via assignment - * in cpu_restore_state. Otherwise re-examine access_type. - */ - if (access_type == MMU_INST_FETCH) { - CPUS390XState *env = cs->env_ptr; - env->int_pgm_ilen = 2; - } - - cpu_loop_exit(cs); - } -} - -#endif /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER From patchwork Wed Apr 3 03:43:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161670 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2521728jan; Tue, 2 Apr 2019 21:02:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqwAhKNjIiVjh0xjCxTNsM5rYH7jMI9UJmZyyhtfZeuANJ2Ax3mpEJaDbJk9cNwaFxrmd5de X-Received: by 2002:a25:aa10:: with SMTP id s16mr6206370ybi.254.1554264126933; Tue, 02 Apr 2019 21:02:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554264126; cv=none; d=google.com; s=arc-20160816; b=JGXU7LhQNoGd8jjK7c95S/ZnDh5e91IaIem6Z7SFMRRvuGxqrdX9HB7e5RcNC3fWLQ B/lEGP4z4eq44oD2ebyEwla0Np8LKxs8qUiJrya3td0eqqGaFBxOLUjwGmQNBEfHaBTv ilh4IZOeUxg/0wvrlDNK5Ssurtwtj0Cux3roHuHlV+lAB3nQaKOVhMM9/I7z7niJSeL3 ksq6E0ml+iPQyzbILkBFMzlSRA73dbSL3NjwKIOAcWK/08FSrgWNFr3pb+IX4HDGeG6J z3s0CE4+kQPzajmEGhgOanqU8XMUNRvQtyQqLoERO9SaYb0wDvlalpOVLJ+jO+76/sRw 5xMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=GrrfMxS6BAo/qH+fRYyxefVrmp0PI4LpRg9xyz4wD40=; b=gigqpabQWmp05HzD0WAuhrupQeB1ADHfGMaGM7rMT2yZX0xvMbFRJueaPc7lQ0EE7O GQRZVQ+bHVjkxk/Oju0D+yZ+M3Owmtn7Rs8vNXHjh9HvUvStJBk1972asVZOP0KZqSPD lLCCPv1DSiK510uDiBTBhi9b7KQcgxcHkac3I5EdFUglGziqzgQLigip++UKa2Tv+nEP tILP/QlbifAJvxpYrkkbxihIEy+FxwEvzHOLUEcLw+ERQS45fKb/5WCK6xbEOTRR+nNx Ehl7OCCafAe01IYOZ+981W7z8b2EpuBU6VRtalTD10dn9iiu7s02mCs+samcW1CkXH8Q 7ldw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Yrnuyk8W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 18/26] target/sh4: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Aurelien Jarno Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 5 +- target/sh4/cpu.c | 5 +- target/sh4/helper.c | 197 ++++++++++++++++++++--------------------- target/sh4/op_helper.c | 12 --- 4 files changed, 101 insertions(+), 118 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 775b5743bf..80a256e0be 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -244,8 +244,9 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, void sh4_translate_init(void); int cpu_sh4_signal_handler(int host_signum, void *pinfo, void *puc); -int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); #if !defined(CONFIG_USER_ONLY) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index b9f393b7c7..886483caaa 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -238,9 +238,8 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; cc->gdb_read_register = superh_cpu_gdb_read_register; cc->gdb_write_register = superh_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = superh_cpu_handle_mmu_fault; -#else + cc->tlb_fill = superh_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = superh_cpu_do_unaligned_access; cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; #endif diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 2ff0cf4060..1df1e02a14 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -27,43 +27,6 @@ #include "hw/sh4/sh_intc.h" #endif -#if defined(CONFIG_USER_ONLY) - -void superh_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index = -1; -} - -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - - env->tea = address; - cs->exception_index = -1; - switch (rw) { - case 0: - cs->exception_index = 0x0a0; - break; - case 1: - cs->exception_index = 0x0c0; - break; - case 2: - cs->exception_index = 0x0a0; - break; - } - return 1; -} - -int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) -{ - /* For user mode, only U0 area is cacheable. */ - return !(addr & 0x80000000); -} - -#else /* !CONFIG_USER_ONLY */ - #define MMU_OK 0 #define MMU_ITLB_MISS (-1) #define MMU_ITLB_MULTIPLE (-2) @@ -79,6 +42,21 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) #define MMU_DADDR_ERROR_READ (-12) #define MMU_DADDR_ERROR_WRITE (-13) +#if defined(CONFIG_USER_ONLY) + +void superh_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index = -1; +} + +int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) +{ + /* For user mode, only U0 area is cacheable. */ + return !(addr & 0x80000000); +} + +#else /* !CONFIG_USER_ONLY */ + void superh_cpu_do_interrupt(CPUState *cs) { SuperHCPU *cpu = SUPERH_CPU(cs); @@ -458,69 +436,6 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical, return get_mmu_address(env, physical, prot, address, rw, access_type); } -int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - target_ulong physical; - int prot, ret, access_type; - - access_type = ACCESS_INT; - ret = - get_physical_address(env, &physical, &prot, address, rw, - access_type); - - if (ret != MMU_OK) { - env->tea = address; - if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { - env->pteh = (env->pteh & PTEH_ASID_MASK) | - (address & PTEH_VPN_MASK); - } - switch (ret) { - case MMU_ITLB_MISS: - case MMU_DTLB_MISS_READ: - cs->exception_index = 0x040; - break; - case MMU_DTLB_MULTIPLE: - case MMU_ITLB_MULTIPLE: - cs->exception_index = 0x140; - break; - case MMU_ITLB_VIOLATION: - cs->exception_index = 0x0a0; - break; - case MMU_DTLB_MISS_WRITE: - cs->exception_index = 0x060; - break; - case MMU_DTLB_INITIAL_WRITE: - cs->exception_index = 0x080; - break; - case MMU_DTLB_VIOLATION_READ: - cs->exception_index = 0x0a0; - break; - case MMU_DTLB_VIOLATION_WRITE: - cs->exception_index = 0x0c0; - break; - case MMU_IADDR_ERROR: - case MMU_DADDR_ERROR_READ: - cs->exception_index = 0x0e0; - break; - case MMU_DADDR_ERROR_WRITE: - cs->exception_index = 0x100; - break; - default: - cpu_abort(cs, "Unhandled MMU fault"); - } - return 1; - } - - address &= TARGET_PAGE_MASK; - physical &= TARGET_PAGE_MASK; - - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; -} - hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { SuperHCPU *cpu = SUPERH_CPU(cs); @@ -745,7 +660,6 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, if (needs_tlb_flush) { tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); } - } else { int index = (addr & 0x00003f00) >> 8; tlb_t * entry = &s->utlb[index]; @@ -885,3 +799,84 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } + +bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + int ret; + +#ifdef CONFIG_USER_ONLY + ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE : + access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION : + MMU_DTLB_VIOLATION_READ); +#else + target_ulong physical; + int prot, sh_access_type; + + sh_access_type = ACCESS_INT; + ret = get_physical_address(env, &physical, &prot, address, + access_type, sh_access_type); + + if (ret == MMU_OK) { + address &= TARGET_PAGE_MASK; + physical &= TARGET_PAGE_MASK; + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + } + if (probe) { + return false; + } + + if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) { + env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK); + } +#endif + + env->tea = address; + switch (ret) { + case MMU_ITLB_MISS: + case MMU_DTLB_MISS_READ: + cs->exception_index = 0x040; + break; + case MMU_DTLB_MULTIPLE: + case MMU_ITLB_MULTIPLE: + cs->exception_index = 0x140; + break; + case MMU_ITLB_VIOLATION: + cs->exception_index = 0x0a0; + break; + case MMU_DTLB_MISS_WRITE: + cs->exception_index = 0x060; + break; + case MMU_DTLB_INITIAL_WRITE: + cs->exception_index = 0x080; + break; + case MMU_DTLB_VIOLATION_READ: + cs->exception_index = 0x0a0; + break; + case MMU_DTLB_VIOLATION_WRITE: + cs->exception_index = 0x0c0; + break; + case MMU_IADDR_ERROR: + case MMU_DADDR_ERROR_READ: + cs->exception_index = 0x0e0; + break; + case MMU_DADDR_ERROR_WRITE: + cs->exception_index = 0x100; + break; + default: + cpu_abort(cs, "Unhandled MMU fault"); + } + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 4f825bae5a..599731966b 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -41,18 +41,6 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_loop_exit_restore(cs, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = superh_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} - #endif void helper_ldtlb(CPUSH4State *env) From patchwork Wed Apr 3 03:43:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161662 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2517920jan; Tue, 2 Apr 2019 20:56:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqyrEeSR2NBw4/CEGpjYZXMBmXwBGS1RKG36mEKqcOB+Vcv2YN/+eJYom7GvhO0q2q9SZ6dm X-Received: by 2002:a25:504e:: with SMTP id e75mr12788445ybb.68.1554263776950; Tue, 02 Apr 2019 20:56:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263776; cv=none; d=google.com; s=arc-20160816; b=rFXqqvX0J6qLbpQFkzSU8ujMLPfkJThVpTr61oIGzDX+WMNUnuWOcyX296/jlixB9k kyUuc9BjMxI5Ay5FoV8+SzAEoqOit/2oSyCjMk7xHVJDBm6BAHySQGYyJbV/O2eTix2W cZ6iTkJxBn26iDmyfhTiumuNZsOnqtUUV/cNF9N5VBVC3Vk80NOcadQPZv8UBp9GjyXH OC6Y5Q5Sp8r4dkPv7wItMwCL73mpXwMtkqESRFNOXe2QJ1EyiYFvKsX3jbLq4RVIhOrh G0CyOffjf4CgqvBTfg8vX54E1Z8tpEpPV8l/jsKXy5lp2+1K/i4w4lkrw2J3Ag1//Ndw Zqdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UklP9VelN2cs0kBnRd6fHc4X8KepPl0VqL+sEcPMx0Q=; b=xpwbUdTY7Bu03GfAFH3TM49KQbiz6U7+mMm9gceWIOE/K9a1ukVFhVlT4aLBzJxlDf Ypt9wsy1Z4O1+05U3ti2MqVhsKf+WyiQiEu+I+lzW5s4feQmir95NXQvO2pmZw50tRy6 RZe2nn24l419qF+CLXuR6na6CudN5UeO6PNg0VOyFnzjkXIKox80vpHnMthDmHgDC5XL HLOT9Oa5TtDYQiyhRoqz5acn7DHEB78r1mnLnRgegCYvFEPyyOQPTz67ePXuhhjHFfmy WFyfmUvNOJ0zjkNNbBlak3KQn+z6cJ9KEvSr88yUlnMU6kV4KT87rPnwCSmMo3u40e7a WH/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j9mJfA9S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 19/26] target/sparc: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Artyom Tarasenko Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 5 +- target/sparc/cpu.c | 5 +- target/sparc/ldst_helper.c | 15 ---- target/sparc/mmu_helper.c | 175 +++++++++++++++++++------------------ 4 files changed, 93 insertions(+), 107 deletions(-) -- 2.17.1 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4972ebcfd4..44336e5899 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -580,8 +580,9 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); /* mmu_helper.c */ -int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4a4445bdf5..016a70717e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -880,9 +880,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; cc->gdb_read_register = sparc_cpu_gdb_read_register; cc->gdb_write_register = sparc_cpu_gdb_write_register; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault; -#else + cc->tlb_fill = sparc_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access = sparc_cpu_unassigned_access; cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 5bc090213c..88196a3ad9 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1924,19 +1924,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, #endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } - -/* try to fill the TLB and return an exception if error. If retaddr is - NULL, it means that the function was called in C code (i.e. not - from generated code or from helper.c) */ -/* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - cpu_loop_exit_restore(cs, retaddr); - } -} #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 135a9c9d9b..b0fdabbea3 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -24,28 +24,7 @@ /* Sparc MMU emulation */ -#if defined(CONFIG_USER_ONLY) - -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - - if (rw & 2) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; -#ifdef TARGET_SPARC64 - env->dmmu.mmuregs[4] = address; -#else - env->mmuregs[4] = address; -#endif - } - return 1; -} - -#else +#ifndef CONFIG_USER_ONLY #ifndef TARGET_SPARC64 /* @@ -85,10 +64,10 @@ static const int perm_table[2][8] = { } }; -static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, - target_ulong address, int rw, int mmu_idx, - target_ulong *page_size) +static int get_physical_address1(CPUSPARCState *env, hwaddr *physical, + int *prot, int *access_index, + target_ulong address, int rw, int mmu_idx, + target_ulong *page_size) { int access_perms = 0; hwaddr pde_ptr; @@ -206,51 +185,41 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, return error_code; } -/* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +static int get_physical_address(CPUSPARCState *env, hwaddr *physical, + int *prot, int *access_index, + target_ulong address, int rw, int mmu_idx, + target_ulong *page_size) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - hwaddr paddr; - target_ulong vaddr; - target_ulong page_size; - int error_code = 0, prot, access_index; + int error_code; + CPUState *cs = CPU(sparc_env_get_cpu(env)); - address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - vaddr = address; - if (error_code == 0) { - qemu_log_mask(CPU_LOG_MMU, - "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " - TARGET_FMT_lx "\n", address, paddr, vaddr); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + error_code = get_physical_address1(env, physical, prot, access_index, + address, rw, mmu_idx, page_size); + + if (error_code && ((env->mmuregs[0] & MMU_NF) || env->psret == 0)) { + /* + * No fault mode: if a mapping is available, just override + * permissions. If no mapping is available, redirect accesses to + * neverland. Fake/overridden mappings will be flushed when + * switching to normal mode. + */ + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; } if (env->mmuregs[3]) { /* Fault status register */ env->mmuregs[3] = 1; /* overflow (not read before another fault) */ } - env->mmuregs[3] |= (access_index << 5) | error_code | 2; + env->mmuregs[3] |= (*access_index << 5) | error_code | 2; env->mmuregs[4] = address; /* Fault address register */ - if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { - /* No fault mode: if a mapping is available, just override - permissions. If no mapping is available, redirect accesses to - neverland. Fake/overridden mappings will be flushed when - switching to normal mode. */ - prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); - return 0; + if (rw & 2) { + cs->exception_index = TT_TFAULT; } else { - if (rw & 2) { - cs->exception_index = TT_TFAULT; - } else { - cs->exception_index = TT_DFAULT; - } - return 1; + cs->exception_index = TT_DFAULT; } + + return error_code; } target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) @@ -711,34 +680,6 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, } } -/* Perform address translation */ -int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - target_ulong vaddr; - hwaddr paddr; - target_ulong page_size; - int error_code = 0, prot, access_index; - - address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, - address, rw, mmu_idx, &page_size); - if (error_code == 0) { - vaddr = address; - - trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, - env->dmmu.mmu_primary_context, - env->dmmu.mmu_secondary_context); - - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); - return 0; - } - /* XXX */ - return 1; -} - void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env) { unsigned int i; @@ -865,3 +806,63 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } #endif + +/* Perform address translation */ +bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + +#ifdef CONFIG_USER_ONLY + if (access_type == MMU_INST_FETCH) { + cs->exception_index = TT_TFAULT; + } else { + cs->exception_index = TT_DFAULT; + } +# ifdef TARGET_SPARC64 + env->dmmu.mmuregs[4] = address; +# else + env->mmuregs[4] = address; +# endif +#else + hwaddr paddr; + target_ulong vaddr; + target_ulong page_size; + int error_code = 0, prot, access_index; + + address &= TARGET_PAGE_MASK; + error_code = get_physical_address(env, &paddr, &prot, &access_index, + address, access_type, mmu_idx, + &page_size); + vaddr = address; + if (error_code == 0) { +# ifdef TARGET_SPARC64 + trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, + env->dmmu.mmu_primary_context, + env->dmmu.mmu_secondary_context); +# else + qemu_log_mask(CPU_LOG_MMU, + "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " + TARGET_FMT_lx "\n", address, paddr, vaddr); +# endif + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + return true; + } + + if (probe) { + return false; + } +#endif + + cpu_loop_exit_restore(cs, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); +} +#endif From patchwork Wed Apr 3 03:43:52 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 20/26] target/tilegx: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/tilegx/cpu.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index bfe9be59b5..be50976c6f 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -24,6 +24,8 @@ #include "qemu-common.h" #include "hw/qdev-properties.h" #include "linux-user/syscall_defs.h" +#include "exec/exec-all.h" + static void tilegx_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) @@ -111,8 +113,9 @@ static void tilegx_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) +static bool tilegx_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { TileGXCPU *cpu = TILEGX_CPU(cs); @@ -122,7 +125,7 @@ static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, cpu->env.signo = TARGET_SIGSEGV; cpu->env.sigcode = 0; - return 1; + cpu_loop_exit_restore(cs, retaddr); } static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -152,7 +155,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt; cc->dump_state = tilegx_cpu_dump_state; cc->set_pc = tilegx_cpu_set_pc; - cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault; + cc->tlb_fill = tilegx_cpu_tlb_fill; cc->gdb_num_core_regs = 0; cc->tcg_initialize = tilegx_tcg_init; } From patchwork Wed Apr 3 03:43:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161667 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2519590jan; Tue, 2 Apr 2019 20:59:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqx/jgQTfUNEfqb39Omtj5mMMdcO4C/Q9xDwK68ldrbL5AHKPncAG92SDTBIQz2IoYebf7ij X-Received: by 2002:a25:758a:: with SMTP id q132mr18401558ybc.73.1554263958047; Tue, 02 Apr 2019 20:59:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263958; cv=none; d=google.com; s=arc-20160816; b=o8dvSXMB3EDD7LMdV+gAw+4oDiBMHq+HnP371jqa6iOJ4tLMZ4jhZjBRt7OcH6AGq0 j4YFZsq+y17DzqiAxZQBl0XpIjSCRTxj189CWW4fYd8fYQl8AFJ3+LYu2Lsis8kHhg0Q 6azixxsZXSuOT2la/1pgGDujvs5EKuUNf/dvrGRKrEHADXEywTNO7o1VtfbnrMO+nuRn fy0/+pVDvyxt0wkLpF37aMlj7k7N3+Dwzw4iY447JS6JWZHkYyfK965E2sFV3ivgS3Dt uD17p0FZsOP6A5U1z2nZ3CgkeE6tmHBRUFWoM7xhG3wgAV07FCYa0DxH5AkisgFUz3rY 6DfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=1va7KWEJPOsYlljyzZctOZk62WDcs6x8O8MJIgG/rEE=; b=DWEhoLbBvrYRWWk1B1mcrdTu49zZ4agR77c/6qHQdHnO64ptyLBEoi9SuP4jXXuwWF 1zTmXSKKAhzp3O+vX9R+O0ozQdN6PI6k0huFQK7a8kAsxTMtbUCFK3LXDSKN1HZxDABq s2dfaXaUoXp0m131J+5dujpq1TqaChsYxf/CKykXfwvpR+xXwB3fZOuwH5wEDhRc1hSb Yn7b5n3QqWJU5EM1eb/LzDly28oXw+97HM2quO38rFxTcYFGUCVpyPYsSFX7M4b+HsM2 JZaQBw1bpEQz/DKuoVqoTCbffarepIFz4L2YWcI0VX39D3hNVuE02l4WvHBamXOI1jal Lw/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x+JCjURI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PATCH 21/26] target/tricore: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/tricore/cpu.h | 6 +++--- target/tricore/cpu.c | 1 + target/tricore/helper.c | 27 +++++++++++++++++++-------- target/tricore/op_helper.c | 26 -------------------------- 4 files changed, 23 insertions(+), 37 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 00e69dc154..5c0b8cb94c 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -418,8 +418,8 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ -int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address, - int rw, int mmu_idx); -#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); #endif /* TRICORE_CPU_H */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e8d37e4040..ea1199d27e 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -166,6 +166,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb; cc->get_phys_page_attrs_debug = tricore_cpu_get_phys_page_attrs_debug; cc->tcg_initialize = tricore_tcg_init; + cc->tlb_fill = tricore_cpu_tlb_fill; } #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 0769046993..3c99a8c22b 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -49,8 +49,9 @@ static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, { } -int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, - int rw, int mmu_idx) +bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType rw, int mmu_idx, + bool probe, uintptr_t retaddr) { TriCoreCPU *cpu = TRICORE_CPU(cs); CPUTriCoreState *env = &cpu->env; @@ -63,20 +64,30 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, address, rw, access_type); - qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, physical, prot); + + qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, (target_ulong)address, ret, physical, prot); if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) { + return true; + } else { + assert(ret < 0); + if (probe) { + return false; + } raise_mmu_exception(env, address, rw, ret); - ret = 1; + cpu_loop_exit_restore(cs, retaddr); } +} - return ret; +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } static void tricore_cpu_list_entry(gpointer data, gpointer user_data) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index ed9dc0c83e..601e92f92a 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2793,29 +2793,3 @@ uint32_t helper_psw_read(CPUTriCoreState *env) { return psw_read(env); } - - -static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs = CPU(tricore_env_get_cpu(env)); - cs->exception_index = exception; - env->error_code = error_code; - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, pc); -} - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - ret = cpu_tricore_handle_mmu_fault(cs, addr, access_type, mmu_idx); - if (ret) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} From patchwork Wed Apr 3 03:43:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161666 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2519517jan; Tue, 2 Apr 2019 20:59:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdjSroE0sxYvJ1uvy+EdSsmKb9SZq2TP+cx7DEgpEndIWRJX3YZaiEqre9+lQMYpwlowCZ X-Received: by 2002:a25:1954:: with SMTP id 81mr61623385ybz.120.1554263951207; Tue, 02 Apr 2019 20:59:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263951; cv=none; d=google.com; s=arc-20160816; b=iBbZ/8YXago9zZJc6kC12wUo4rIWzG1egaf0O4SP4y9D+NbBXnhgWeGIRFViMGgGQN 9b5tspfDvacqrnaP9f/wQlqWa28/19pSn6n/ogL8pmzH23CYtRtsnjIPDdZouypVSgAO Evoz004NkpzzjVSXsy+fLZDiq9ZdUHwbNZLAAzTfEOusPf6m0YbUdL9k5Vk0ujrFiXQY 8yvG7tAWRobk8YKH+wTOqAQaI1DFIC8tVtOTd75nLEn5ddw/mKNv9TswXkId/7MzPyGo ctlZ7pbJAzJUQdFL4m+bL0DDC5S6xF8fHNQ30PSeU9OEKmbLLrcGIGFP0yhecrbGX4we 85rw== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::52c Subject: [Qemu-devel] [PATCH 22/26] target/unicore32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guan Xuetao Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Guan Xuetao Signed-off-by: Richard Henderson --- target/unicore32/cpu.h | 5 +++-- target/unicore32/cpu.c | 5 +---- target/unicore32/helper.c | 23 ----------------------- target/unicore32/op_helper.c | 14 -------------- target/unicore32/softmmu.c | 19 +++++++++++++++---- 5 files changed, 19 insertions(+), 47 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 735d3ae9dc..dfec908cad 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -179,8 +179,9 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc } } -int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 2b49d1ca40..3f57c508a0 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -138,11 +138,8 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault; -#else + cc->tlb_fill = uc32_cpu_tlb_fill; cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; -#endif cc->tcg_initialize = uc32_translate_init; dc->vmsd = &vmstate_uc32_cpu; } diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index a5ff2ddb74..0d4914b48d 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -215,29 +215,6 @@ void helper_cp1_putc(target_ulong x) } #endif -#ifdef CONFIG_USER_ONLY -void switch_mode(CPUUniCore32State *env, int mode) -{ - UniCore32CPU *cpu = uc32_env_get_cpu(env); - - if (mode != ASR_MODE_USER) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); - } -} - -void uc32_cpu_do_interrupt(CPUState *cs) -{ - cpu_abort(cs, "NO interrupt in user mode\n"); -} - -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) -{ - cpu_abort(cs, "NO mmu fault in user mode\n"); - return 1; -} -#endif - bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index e0a15882d3..797ba60dc9 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -242,17 +242,3 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = uc32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 00c7e0d028..13678df4d7 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -215,8 +215,9 @@ do_fault: return code; } -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { UniCore32CPU *cpu = UNICORE32_CPU(cs); CPUUniCore32State *env = &cpu->env; @@ -257,7 +258,11 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); - return 0; + return true; + } + + if (probe) { + return false; } env->cp0.c3_faultstatus = ret; @@ -267,7 +272,13 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, } else { cs->exception_index = UC32_EXCP_DTRAP; } - return ret; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) From patchwork Wed Apr 3 03:43:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161669 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2521352jan; Tue, 2 Apr 2019 21:01:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqzOcb0KyllnCOFP4xcbZLuGa1ZJ+WxF6gIYumk+4KRF1ooIxfdjx8FWX7njjYuMvR2JWuT8 X-Received: by 2002:a25:ba8f:: with SMTP id s15mr36928727ybg.411.1554264098678; Tue, 02 Apr 2019 21:01:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554264098; cv=none; d=google.com; s=arc-20160816; b=UHfyXI8vdV8QhMT5AcVEMFX5whC29v2+OeKlsuD0RRlz75OB4yyXpvtG1pCVb3zK/v nxs817va/HwDNcsapYnq2b9z89aAMXz1gSbLC1uX+Qx0onlrKtNntYc9nelmLeFZCzCA Wmm6PlZoHaPFzzvayEJfgrtS6y+Rn4FYwNAdxzCBNPLnIzyd+51latHQBPcqyz92dUTZ KCiUhgjp7GQ41UoWDFs5iZTmavzmNr1ZfvhDl0/NXJlPurvScC/t65FGg0shHItS5uVr E/NiHdhOOL/9RxhWVwN0zGxZydQA1k4c0kejsOChPnR1n0icEXsAhiVOSVug7XIexZY6 EL+Q== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id x73si9838411ywx.177.2019.04.02.21.01.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 02 Apr 2019 21:01:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QPorBkBz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:55641 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBX5m-0000rv-5m for patch@linaro.org; Wed, 03 Apr 2019 00:01:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWpY-0003Fp-EA for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWpX-0000Qa-5j for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:52 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:38336) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWpW-0000Pc-Ru for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:51 -0400 Received: by mail-pl1-x643.google.com with SMTP id g37so7314978plb.5 for ; Tue, 02 Apr 2019 20:44:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jZbhKXF2K9UWgdUAfPksCUR+9PeJ8LRUYBa5SdhmbKM=; b=QPorBkBzHz3p+wTcfg68whDENocovgCVMjOsqlSfrO2j356WUcbciIyO0nuH22NvJf 0cN2AVN6N2Wnu6w+KFMSwqOund99FHVF5dSpBfGGi9j8urmiurfABpcxI/ajGCGJNkv1 moNlqixys0AtnJnqUfow9nCUTt3zXhlp4PtI3evZMksVe4/ni1fOJC8NWPj+3G77zlyk y8mo6i6gjt9SDVE1Gvgv6h0d9LDOr+IOkWFj8F8/zUThd8rhAkcnpvdFbXD7+D+Gvs4e gL9CIASF6la2Fq7U09yPmsq5ru5KDELBwihWdcVbVTPdYyyD+ca2DxKQDYEfOCM1DBEy uoyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jZbhKXF2K9UWgdUAfPksCUR+9PeJ8LRUYBa5SdhmbKM=; b=n8yr2WWhvgkI/p/gWNXXr89kD2EtRrXHoVgOcYQ25m+OdCEamYNKZ8VrscyM9Mjmzm MG6/UXhq9kSJ9mUn691QbunDNmCuWkBeYmzz3bEolh8HIapfkG+i++Lt08HGiB6A8U9k kGPT11munuWYltc+f3J9V6/48wd2e351hEeFW3+iTqEPTBqu4RsBqDW5cUXV00Bb4Bap RG0GfCLbmJnznV44YgUF0SMONfM4Q/7vqK/QfghFmj4NAv8v6wOr4ksWxCUYwoITTS+a iai+MXzNQU/4bxTJFGyW5n6BzcGP+DQIDT4GjCdNi317nyjo8xjU4KDy8LLsIpyVnBfk s9GQ== X-Gm-Message-State: APjAAAUvq4XmfDG78ZKn2DiaztYMfnpgtFfXe+Et7/wCbyghoy7OJmNa iNT/33mEbouUE1EsnB7BV5Q3gpWWh3UwYw== X-Received: by 2002:a17:902:2bab:: with SMTP id l40mr74192882plb.273.1554263089663; Tue, 02 Apr 2019 20:44:49 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:55 +0700 Message-Id: <20190403034358.21999-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 23/26] target/xtensa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 5 +-- target/xtensa/cpu.c | 5 ++- target/xtensa/helper.c | 74 +++++++++++++++++++++--------------------- 3 files changed, 42 insertions(+), 42 deletions(-) -- 2.17.1 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4d8152682f..8ac6f8eeca 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -552,8 +552,9 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) #define ENV_OFFSET offsetof(XtensaCPU, env) -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, - int mmu_idx); +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe4260..da1236377e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,9 +181,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = xtensa_cpu_gdb_read_register; cc->gdb_write_register = xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint = true; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = xtensa_cpu_handle_mmu_fault; -#else + cc->tlb_fill = xtensa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed = xtensa_cpu_do_transaction_failed; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f4867a9b56..3dcab54fbf 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -237,24 +237,49 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf) } } -#ifdef CONFIG_USER_ONLY - -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; + target_ulong vaddr = address; + int ret; - qemu_log_mask(CPU_LOG_INT, - "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", - __func__, rw, address, size); - env->sregs[EXCVADDR] = address; - env->sregs[EXCCAUSE] = rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE; - cs->exception_index = EXC_USER; - return 1; +#ifdef CONFIG_USER_ONLY + ret = (access_type == MMU_DATA_STORE ? + STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); +#else + uint32_t paddr; + uint32_t page_size; + unsigned access; + + ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx, + &paddr, &page_size, &access); + + qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", + __func__, vaddr, access_type, mmu_idx, paddr, ret); + + if (ret == 0) { + tlb_set_page(cs, vaddr & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, + access, mmu_idx, page_size); + return true; + } + if (probe) { + return false; + } +#endif + + cpu_restore_state(cs, retaddr, true); + HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } -#else +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, retaddr); +} void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -272,31 +297,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, } } -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx, - &paddr, &page_size, &access); - - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); - - if (ret == 0) { - tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); - } else { - cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); - } -} - void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, From patchwork Wed Apr 3 03:43:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161675 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2524729jan; Tue, 2 Apr 2019 21:05:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqzDf8pR+RSeZP58pz7JQURHJFSMEV7noT9HMCsG8kO1stmxyujjE4SjdoxTiaG7iOAqS+V4 X-Received: by 2002:a81:30d1:: with SMTP id w200mr63718367yww.360.1554264359152; Tue, 02 Apr 2019 21:05:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554264359; cv=none; d=google.com; s=arc-20160816; b=rkdqkQE0/NDzQQ1gBF52/U/yIYim6QziUySyVCdc2y59GYI+PYFco5bNH/iYvFkiD/ cjCoHKEkMJmDqiJ3PuPsnQOCHrD/uH0ngCEQPCSfZjq5oj4I79J/d7vCyRVwoi2Pit6N NLve6WA1xUSlGBXWaTXuLK/ZLdvhAuCG1dVPGag8mSvsCM1gcBRX9Ty+/cOZNxRCtcgE uGkHm69thgo158oQywzSFetGEC9ZYRls0jNIQhMz1dGIM8/bZaTfgcdWmX95rwD4gQbI Ay7kkDhorUypOXmCdw7i8fVonSBu75j42Zf1XsnpBN0bj1KvM77onlnnS5gU/RkLUB9d ak2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HlWqoUysPYNFvoG+1YizFTttQsq6OpAAy6382msLO5k=; b=zED6BEfEg8KuTiyK4GeHWBrecPNYZwmxEfHIpUXqKPcqgmUtv+EkkjfXVepoLk37/3 xmq6OFzwqiKx+YVQr5yES6ZLr9Gon4IxQMeTPfXCajXTLeBg14nKh6oHVPG6lfmZHoB9 0qtyYscJZTQAVgylt9a6LGOJZU672OwFfcv6EJ8Qsfnp61v2Wt3+QTMQIPvJ3/zfdpbN W2LdOtC/yJJJem9FW1zXroB9e7+jhGEWduCFe2BeYAfSXkqInXgp8BmkZpa4fyWA+3nx n/iKa1p7rko0D1OmpV1oySyEpABgY0ZalVo7Qs1TRKG20rHFO9UWrNMYOr334Y4JHl7V kvVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rypGNvlS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 24/26] tcg: Use CPUClass::tlb_fill in cputlb.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also which also isolates the asserts implied. Remove the named tlb_fill function from all of the targets. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 9 --------- accel/tcg/cputlb.c | 19 +++++++++++++++++++ target/alpha/helper.c | 8 -------- target/arm/helper.c | 8 -------- target/cris/helper.c | 6 ------ target/hppa/mem_helper.c | 6 ------ target/i386/excp_helper.c | 8 -------- target/lm32/helper.c | 6 ------ target/m68k/helper.c | 8 -------- target/microblaze/helper.c | 8 -------- target/mips/helper.c | 6 ------ target/moxie/helper.c | 6 ------ target/nios2/helper.c | 8 -------- target/openrisc/mmu.c | 6 ------ target/ppc/mmu_helper.c | 6 ------ target/riscv/cpu_helper.c | 6 ------ target/s390x/excp_helper.c | 6 ------ target/sh4/helper.c | 8 -------- target/sparc/mmu_helper.c | 8 -------- target/tricore/helper.c | 6 ------ target/unicore32/softmmu.c | 6 ------ target/xtensa/helper.c | 6 ------ 22 files changed, 19 insertions(+), 145 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 97b90cb0db..66e67caad7 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -474,15 +474,6 @@ static inline void assert_no_pages_locked(void) */ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs); - -/* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must - * be discarded and looked up again (e.g. via tlb_entry()). - */ -void tlb_fill(CPUState *cpu, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - #endif #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 88cc8389e9..7f59d815db 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -855,6 +855,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) return ram_addr; } +/* + * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the + * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must + * be discarded and looked up again (e.g. via tlb_entry()). + */ +static void tlb_fill(CPUState *cpu, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + bool ok; + + /* + * This is not a probe, so only valid return is success; failure + * should result in exception + longjmp to the cpu loop. + */ + ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr); + g_assert(ok); +} + static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index e54197d5fb..726104a308 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -272,14 +272,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #endif } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - void alpha_cpu_do_interrupt(CPUState *cs) { AlphaCPU *cpu = ALPHA_CPU(cs); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0fc4abc651..db8c825a4b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12404,14 +12404,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #endif } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/cris/helper.c b/target/cris/helper.c index 69464837c8..b5159b8357 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -123,12 +123,6 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit(cs); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void crisv10_cpu_do_interrupt(CPUState *cs) { CRISCPU *cpu = CRIS_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index f61b0fdb9f..75b7082e0a 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -261,12 +261,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, return true; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) -{ - hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); -} - /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) { diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 6f59b7bafc..79635d7539 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -700,11 +700,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, return true; #endif } - -#if !defined(CONFIG_USER_ONLY) -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 1db9a5562e..20ea17ba23 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -44,12 +44,6 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { LM32CPU *cpu = LM32_CPU(cs); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9768b4517f..2e34c684ba 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -893,14 +893,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - uint32_t HELPER(bitrev)(uint32_t x) { x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 2d1d10e6cf..650897a20b 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -89,14 +89,6 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - #ifdef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs) diff --git a/target/mips/helper.c b/target/mips/helper.c index 7fe0ba4754..520f89407c 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -944,12 +944,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) { hwaddr physical; diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 216cef057e..f5c1d4181c 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,12 +26,6 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void helper_raise_exception(CPUMoxieState *env, int ex) { CPUState *cs = CPU(moxie_env_get_cpu(env)); diff --git a/target/nios2/helper.c b/target/nios2/helper.c index d075ef1965..34ad6987b7 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -294,11 +294,3 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->regs[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 991f3fafe8..4e190514ca 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -178,10 +178,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr); -} #endif diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 6865c0ca37..b8b44b2323 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3049,9 +3049,3 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, } return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2535435260..41d6db41c3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -378,12 +378,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; riscv_raise_exception(env, cs->exception_index, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} #endif bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index aeeaeb523d..ec03d9f7d3 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -76,12 +76,6 @@ void s390_cpu_do_interrupt(CPUState *cs) #else /* !CONFIG_USER_ONLY */ -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx) { switch (mmu_idx) { diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 1df1e02a14..074c74f337 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -872,11 +872,3 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index b0fdabbea3..ae9b7a0eb3 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -858,11 +858,3 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 3c99a8c22b..157c8caf4b 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -84,12 +84,6 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - static void tricore_cpu_list_entry(gpointer data, gpointer user_data) { ObjectClass *oc = data; diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 13678df4d7..27f218abf0 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -275,12 +275,6 @@ bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { error_report("function uc32_cpu_get_phys_page_debug not " diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 3dcab54fbf..62d8dd1227 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -275,12 +275,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, retaddr); -} - void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Wed Apr 3 03:43:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161672 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2523205jan; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 25/26] tcg: Remove CPUClass::handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This hook is now completely replaced by tlb_fill. Signed-off-by: Richard Henderson --- include/qom/cpu.h | 3 --- accel/tcg/user-exec.c | 13 +++---------- 2 files changed, 3 insertions(+), 13 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 7e96a0aed3..8afcf0c427 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -118,7 +118,6 @@ struct TranslationBlock; * This always includes at least the program counter; some targets * will need to do more. If this hook is not implemented then the * default is to call @set_pc(tb->pc). - * @handle_mmu_fault: Callback for handling an MMU fault. * @tlb_fill: Callback for handling a softmmu tlb miss or user-only * address fault. For system mode, if the access is valid, call * tlb_set_page and return true; if the access is invalid, and @@ -198,8 +197,6 @@ typedef struct CPUClass { Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); - int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, - int mmu_index); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f13c0b2b67..d79bed0266 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -63,7 +63,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, { CPUState *cpu = current_cpu; CPUClass *cc; - int ret; unsigned long address = (unsigned long)info->si_addr; MMUAccessType access_type; @@ -162,15 +161,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, helper_retaddr = 0; cc = CPU_GET_CLASS(cpu); - if (cc->tlb_fill) { - access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); - g_assert_not_reached(); - } else { - ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX); - g_assert(ret > 0); - cpu_loop_exit_restore(cpu, pc); - } + access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; + cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + g_assert_not_reached(); } #if defined(__i386__) From patchwork Wed Apr 3 03:43:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161674 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2523448jan; Tue, 2 Apr 2019 21:04:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjNpKVN3LzPYFIkDnB0hFg/GciiW2gNg5RRIazbf2TBK1C7tyd2RNi3+ANIr+jDuL4bjTd X-Received: by 2002:a81:234a:: with SMTP id j71mr64193918ywj.352.1554264253306; Tue, 02 Apr 2019 21:04:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554264253; cv=none; d=google.com; s=arc-20160816; b=tY5MkNVO6c5Sru1M1Ug4ludwcV1XN0q5QcmH5L1Y8Jqpuqut5kSp7C7EX5yZkHeGsO EdYQjNSJ78qFyUaLdM0H+8wt0zDT3HI/oo58/NKumow5DpxXwAmVUhHlvBwZKpaTRj2y P/Vps4zC2kXwrU3nOJxsuFF2QCGVDB0RcgoSJzPpmm999rue32zdv8bY+OUqmKB3eCK+ gK7zrBC9p38huj+ZDoAOWhv7woMlvgL2pNrHDlPn9tj3rQjIGfdgNMiHGiBQPHghonW1 uSb9BtnOQpAV8WqZBLQooPF1pg4duPOEclscNIfYfBRqFnUZNzg3MACSRQe79fBTeMib 27fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=eSmixxW4uQkmpintF6uPGofmBAlQammZR2m74ngSc30=; b=ZLfQPIT7kQTlcm5nnysdQkXESdL3JEBZN0NbcU680BL3DETrbz5hTJp8K9ng71Oh9F zV35YUINiHKgmaPN50SglxZ7D5U3lGSYAJgpMNTka8VrbciHWvuqZHR89iY3RqUM3Tuh vK3sl8MrBISI1XVN2AHUYMbBtYRqCg5AjUuNz1zsueB+8L1r6MEB55q6iyGlOdFBA54d G/kcTjVV/5Bjy9ALYonDtqMns4VvVyf5ne67Ci9xSHqZ+PXABppHcFL2TkSUj2BSVR1T wEV5dytIm5P4iooPAYZbv2JwOsNiGU3Ydwt8fOmKJeX//SfQAMcxkCPiEFJfFCYzjapE WrSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AgoLDyYK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 26/26] tcg: Use tlb_fill probe from tlb_vaddr_to_host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most of the existing users would continue around a loop which would fault the tlb entry in via a normal load/store. But for SVE we have a true non-faulting case which requires the new probing form of tlb_fill. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 40 ++++-------------------- accel/tcg/cputlb.c | 69 ++++++++++++++++++++++++++++++++++++----- target/arm/sve_helper.c | 6 +--- 3 files changed, 68 insertions(+), 47 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d78041d7a0..be8c3f4da2 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -440,43 +440,15 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, * This is the equivalent of the initial fast-path code used by * TCG backends for guest load and store accesses. */ +#ifdef CONFIG_USER_ONLY static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - int access_type, int mmu_idx) + MMUAccessType access_type, int mmu_idx) { -#if defined(CONFIG_USER_ONLY) return g2h(addr); -#else - CPUTLBEntry *tlbentry = tlb_entry(env, mmu_idx, addr); - abi_ptr tlb_addr; - uintptr_t haddr; - - switch (access_type) { - case 0: - tlb_addr = tlbentry->addr_read; - break; - case 1: - tlb_addr = tlb_addr_write(tlbentry); - break; - case 2: - tlb_addr = tlbentry->addr_code; - break; - default: - g_assert_not_reached(); - } - - if (!tlb_hit(tlb_addr, addr)) { - /* TLB entry is for a different page */ - return NULL; - } - - if (tlb_addr & ~TARGET_PAGE_MASK) { - /* IO access */ - return NULL; - } - - haddr = addr + tlbentry->addend; - return (void *)haddr; -#endif /* defined(CONFIG_USER_ONLY) */ } +#else +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx); +#endif #endif /* CPU_LDST_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7f59d815db..959b6d4ded 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1006,6 +1006,16 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, } } +static inline target_ulong tlb_read_ofs(CPUTLBEntry *entry, size_t ofs) +{ +#if TCG_OVERSIZED_GUEST + return *(target_ulong *)((uintptr_t)entry + ofs); +#else + /* ofs might correspond to .addr_write, so use atomic_read */ + return atomic_read((target_ulong *)((uintptr_t)entry + ofs)); +#endif +} + /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, @@ -1016,14 +1026,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp; - - /* elt_ofs might correspond to .addr_write, so use atomic_read */ -#if TCG_OVERSIZED_GUEST - cmp = *(target_ulong *)((uintptr_t)vtlb + elt_ofs); -#else - cmp = atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); -#endif + target_ulong cmp = tlb_read_ofs(vtlb, elt_ofs); if (cmp == page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1107,6 +1110,56 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, } } +void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx) +{ + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + uintptr_t tlb_addr, page; + size_t elt_ofs; + + switch (access_type) { + case MMU_DATA_LOAD: + elt_ofs = offsetof(CPUTLBEntry, addr_read); + break; + case MMU_DATA_STORE: + elt_ofs = offsetof(CPUTLBEntry, addr_write); + break; + case MMU_INST_FETCH: + elt_ofs = offsetof(CPUTLBEntry, addr_code); + break; + default: + g_assert_not_reached(); + } + + page = addr & TARGET_PAGE_MASK; + tlb_addr = tlb_read_ofs(entry, elt_ofs); + + if (!tlb_hit_page(tlb_addr, page)) { + uintptr_t index = tlb_index(env, mmu_idx, addr); + + if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page)) { + CPUState *cs = ENV_GET_CPU(env); + CPUClass *cc = CPU_GET_CLASS(cs); + + if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) { + /* Non-faulting page table read failed. */ + return NULL; + } + + /* TLB resize via tlb_fill may have moved the entry. */ + entry = tlb_entry(env, mmu_idx, addr); + } + tlb_addr = tlb_read_ofs(entry, elt_ofs); + } + + if (tlb_addr & ~TARGET_PAGE_MASK) { + /* IO access */ + return NULL; + } + + return (void *)(addr + entry->addend); +} + /* Probe for a read-modify-write atomic operation. Do not allow unaligned * operations, or io operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index bc847250dd..fd434c66ea 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4598,11 +4598,7 @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, const target_ulong addr, * in the real world, obviously.) * * Then there are the annoying special cases with watchpoints... - * - * TODO: Add a form of tlb_fill that does not raise an exception, - * with a form of tlb_vaddr_to_host and a set of loads to match. - * The non_fault_vaddr_to_host would handle everything, usually, - * and the loads would handle the iomem path for watchpoints. + * TODO: Add a form of non-faulting loads using cc->tlb_fill(probe=true). */ host = tlb_vaddr_to_host(env, addr + mem_off, MMU_DATA_LOAD, mmu_idx); split = max_for_page(addr, mem_off, mem_max);