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[209.51.188.17]) by mx.google.com with ESMTPS id f42-20020a05622a1a2a00b003a4ea208149si10196568qtb.252.2022.12.30.03.37.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Dec 2022 03:37:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DBTZKCrq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pBDfR-0006EU-Se; Fri, 30 Dec 2022 06:35:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pBDfQ-0006E3-Q2 for qemu-devel@nongnu.org; Fri, 30 Dec 2022 06:35:16 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pBDfP-0003pk-6V for qemu-devel@nongnu.org; Fri, 30 Dec 2022 06:35:16 -0500 Received: by mail-wm1-x330.google.com with SMTP id ja17so15006959wmb.3 for ; Fri, 30 Dec 2022 03:35:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UOZfJuKjGnXyKynHrF0ryyVy+OVxkYOdTY6ayMGkBgk=; b=DBTZKCrqACtUO10TYcUd+HHcB8Ps4HcfHIsmuWpBIbGRaqi7NLiap7mXT/ieFhugrD cANS0EBLjBDYMaCI3s4ZDInps2efuEi4BGL/spIZTa5qm87KBaomho7LiJnpJwdCi4mJ jN3vHmzgnq8qklxPx5q6RRAPBOEjLPQE3JttJcC0rpzLGy0Zv/I9bz9HLxTHYyYZZTND opN0PUXSIW1yHOUkb7GZOhenp6SAL29UyAE630gXTKSWfQUMlyxE8qH1fWN2mNws6xet 6NGIo/pFPNO0vJWFZnhOvUSEO8Bw8LzDEgebp4JUv0XlcH5ifNnDZr5LoYUlxUtAC2Uh wLdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UOZfJuKjGnXyKynHrF0ryyVy+OVxkYOdTY6ayMGkBgk=; b=rr7DU5CBMptN2duFU7OX5LnOEM8kkbMsTTiLbdbf10WulZGzjruC8VZI7WNcKz6Q2K YwGgP6E6ok0nRYN0J+2Sxhlb5M8oB0LybZOzZ29/gSbYqZ61RO8CpHciemBFUorZBZM+ bM3EeQ/g7BDH+ePP623Tm48He6MnLaj6Dn86DP3V8cmui+4mamBPtCzauwpGhw7y7ZfF 8z5LZZq4u2ckhsEuzeyZAV5z5syHFXaBkV78l7OFz5JY2bRT/IXN8f9YRD5JaPpQ+u19 0Ps/+q5yJkGsRYuLyXb2lUywmKgU5C9tzMrrrRQLGQeCdyr9fIVSJQFtae9MFBGIQJaA AHrw== X-Gm-Message-State: AFqh2kq7ZSIMueQupKCRkbqjC8bVOS3XljayCcrLZjn7ZUr4386sr5PI 0m3cDfrrDrN3SLH+1YtQwfuytX+GIw8peDQH X-Received: by 2002:a05:600c:4d25:b0:3d2:27ba:dde0 with SMTP id u37-20020a05600c4d2500b003d227badde0mr22902840wmp.33.1672400113415; Fri, 30 Dec 2022 03:35:13 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id iz17-20020a05600c555100b003d1e1f421bfsm31857528wmb.10.2022.12.30.03.35.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 30 Dec 2022 03:35:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Troy Lee , Beraldo Leal , Peter Maydell , Wainer dos Santos Moschetta , Andrew Jeffery , Chin-Ting Kuo , Peter Delevoryas , Steven Lee , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin , Peter Delevoryas , Peter Delevoryas , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Cleber Rosa Subject: [PATCH v2 01/11] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize' Date: Fri, 30 Dec 2022 12:34:54 +0100 Message-Id: <20221230113504.37032-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230113504.37032-1-philmd@linaro.org> References: <20221230113504.37032-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid confusing two different things: - the WDT I/O region size ('iosize') - at which offset the SoC map the WDT ('offset') While it is often the same, we can map smaller region sizes at larger offsets. Here we are interested in the I/O region size, so rename as 'iosize'. Reviewed-by: Peter Delevoryas Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed_ast10x0.c | 2 +- hw/arm/aspeed_ast2600.c | 2 +- hw/arm/aspeed_soc.c | 2 +- hw/watchdog/wdt_aspeed.c | 8 ++++---- include/hw/watchdog/wdt_aspeed.h | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 4d0b9b115f..122b3fd3f3 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -325,7 +325,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) return; } aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, - sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); + sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); } /* GPIO */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index cd75465c2b..a79e05ddbd 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -472,7 +472,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) return; } aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, - sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); + sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); } /* RAM */ diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index b05b9dd416..2c0924d311 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -393,7 +393,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) return; } aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, - sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); + sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); } /* RAM */ diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index d753693a2e..958725a1b5 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -309,7 +309,7 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); dc->desc = "ASPEED 2400 Watchdog Controller"; - awc->offset = 0x20; + awc->iosize = 0x20; awc->ext_pulse_width_mask = 0xff; awc->reset_ctrl_reg = SCU_RESET_CONTROL1; awc->wdt_reload = aspeed_wdt_reload; @@ -346,7 +346,7 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); dc->desc = "ASPEED 2500 Watchdog Controller"; - awc->offset = 0x20; + awc->iosize = 0x20; awc->ext_pulse_width_mask = 0xfffff; awc->reset_ctrl_reg = SCU_RESET_CONTROL1; awc->reset_pulse = aspeed_2500_wdt_reset_pulse; @@ -369,7 +369,7 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); dc->desc = "ASPEED 2600 Watchdog Controller"; - awc->offset = 0x40; + awc->iosize = 0x40; awc->ext_pulse_width_mask = 0xfffff; /* TODO */ awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; awc->reset_pulse = aspeed_2500_wdt_reset_pulse; @@ -392,7 +392,7 @@ static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data) AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); dc->desc = "ASPEED 1030 Watchdog Controller"; - awc->offset = 0x80; + awc->iosize = 0x80; awc->ext_pulse_width_mask = 0xfffff; /* TODO */ awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; awc->reset_pulse = aspeed_2500_wdt_reset_pulse; diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index dfa5dfa424..db91ee6b51 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -40,7 +40,7 @@ struct AspeedWDTState { struct AspeedWDTClass { SysBusDeviceClass parent_class; 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Fri, 30 Dec 2022 03:35:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Troy Lee , Beraldo Leal , Peter Maydell , Wainer dos Santos Moschetta , Andrew Jeffery , Chin-Ting Kuo , Peter Delevoryas , Steven Lee , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin , Peter Delevoryas , Peter Delevoryas , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Cleber Rosa Subject: [PATCH v2 02/11] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers Date: Fri, 30 Dec 2022 12:34:55 +0100 Message-Id: <20221230113504.37032-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230113504.37032-1-philmd@linaro.org> References: <20221230113504.37032-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When booting the Zephyr demo in [1] we get: aspeed.io: unimplemented device write (size 4, offset 0x185128, value 0x030f1ff1) <-- aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 0x03fffff1) This corresponds to this Zephyr code [2]: static int aspeed_wdt_init(const struct device *dev) { const struct aspeed_wdt_config *config = dev->config; struct aspeed_wdt_data *const data = dev->data; uint32_t reg_val; /* disable WDT by default */ reg_val = sys_read32(config->ctrl_base + WDT_CTRL_REG); reg_val &= ~WDT_CTRL_ENABLE; sys_write32(reg_val, config->ctrl_base + WDT_CTRL_REG); sys_write32(data->rst_mask1, config->ctrl_base + WDT_SW_RESET_MASK1_REG); <------ sys_write32(data->rst_mask2, config->ctrl_base + WDT_SW_RESET_MASK2_REG); return 0; } The register definitions are [3]: #define WDT_RELOAD_VAL_REG 0x0004 #define WDT_RESTART_REG 0x0008 #define WDT_CTRL_REG 0x000C #define WDT_TIMEOUT_STATUS_REG 0x0010 #define WDT_TIMEOUT_STATUS_CLR_REG 0x0014 #define WDT_RESET_MASK1_REG 0x001C #define WDT_RESET_MASK2_REG 0x0020 #define WDT_SW_RESET_MASK1_REG 0x0028 <------ #define WDT_SW_RESET_MASK2_REG 0x002C #define WDT_SW_RESET_CTRL_REG 0x0024 Currently QEMU only cover a MMIO region of size 0x20: #define ASPEED_WDT_REGS_MAX (0x20 / 4) Change to map the whole 'iosize' which might be bigger, covering the other registers. The MemoryRegionOps read/write handlers will report the accesses as out-of-bounds guest-errors, but the next commit will report them as unimplemented. [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07 [2] https://github.com/AspeedTech-BMC/zephyr/commit/2e99f10ac27b [3] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31 Reviewed-by: Peter Delevoryas Signed-off-by: Philippe Mathieu-Daudé --- hw/watchdog/wdt_aspeed.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 958725a1b5..eefca31ae4 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -260,6 +260,7 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); AspeedWDTState *s = ASPEED_WDT(dev); + AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev); assert(s->scu); @@ -271,7 +272,7 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) s->pclk_freq = PCLK_HZ; memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, - TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); + TYPE_ASPEED_WDT, awc->iosize); sysbus_init_mmio(sbd, &s->iomem); } From patchwork Fri Dec 30 11:34:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637870 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359670pvb; Fri, 30 Dec 2022 03:38:02 -0800 (PST) X-Google-Smtp-Source: AMrXdXuVKTVgdTz1AOcEq8pRyBmgJ2kKHSygviAugMQEvFdzgJ11ATED0j2I30URhCrNS8tPTGQ4 X-Received: by 2002:ac8:4e16:0:b0:3a9:8c90:dcec with SMTP id c22-20020ac84e16000000b003a98c90dcecmr36213824qtw.68.1672400282532; Fri, 30 Dec 2022 03:38:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672400282; cv=none; d=google.com; s=arc-20160816; b=fvRjJpjryFROhXHFUy8t5FbTMf2C2Y68L6CtQ53OaLfjgS4XpMFwcaMuUWupm24RjH tNxhRp8Ilx9GKnEmNbwlxPD+KAsKIv2vxzcH799KCd4R++KWmXwBMm05cxNM6JXLtvOv cvKZbgGvOVeyyHGN2IjSGtqE1jVZxhBi4by0MBOurO2Et5DlFhOXLX4ZatW/dxnUMmRD UTkQAPSGIrnt4VNz+ilP6bYHaxsSiWvz+pI6EUVm6OzIXbnjr0SBF1y4YdTWgpSE37Be gGXGUfZ+My8izWzQcFG0IuW1QBQ7XBG7h34X382t2t626eP1XnVHMV5whJxAQo1Miw9l rmaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=70DGxBuGEM6E1qaNTyKpqAEgNBdsVXtKZ3vAYEiZW0c=; b=O0c4G1GhMtmxA+HmQgZXxreW7+kZFJjiv8ZdPRw7884cMKpKY5Um4EfpgqsQ8MR7zb /kIaVXrnuPescwI6MrIuD1kxlRJCrRVgcF1hSYq6WNCmTtehtEa1yOITKDZdDwSqBWB5 kxe2inTQwFy9w3y7fvxemOPcCZhHR/2Zi+qA1M4uDtFFX100+eWsmcm2OEEsnWKbAS6P Vl8B6Y6HNIVLvDqFKEWhmvAz6idSjBOvFlXzoT7MMLGjqzOYXGSDF8xh4k+U0jg/pdsO VAkvcCnAH2B86oTaVU+CUci7heaCRkw0pgbZeGJLlPV63MJD0+XzEZX5ZeU6bxrl4Hir vDqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m0Fagbiy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Since guests can righteously access them, log the access at 'unimplemented' level instead of 'guest-errors'. [*] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas --- hw/watchdog/wdt_aspeed.c | 13 +++++++++++++ include/hw/watchdog/wdt_aspeed.h | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index eefca31ae4..d267aa185c 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -42,6 +42,11 @@ #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) #define WDT_RESET_MASK1 (0x1c / 4) +#define WDT_RESET_MASK2 (0x20 / 4) + +#define WDT_SW_RESET_CTRL (0x24 / 4) +#define WDT_SW_RESET_MASK1 (0x28 / 4) +#define WDT_SW_RESET_MASK2 (0x2c / 4) #define WDT_TIMEOUT_STATUS (0x10 / 4) #define WDT_TIMEOUT_CLEAR (0x14 / 4) @@ -83,6 +88,10 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) return s->regs[WDT_RESET_MASK1]; case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: + case WDT_RESET_MASK2: + case WDT_SW_RESET_CTRL: + case WDT_SW_RESET_MASK1: + case WDT_SW_RESET_MASK2: qemu_log_mask(LOG_UNIMP, "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -190,6 +199,10 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: + case WDT_RESET_MASK2: + case WDT_SW_RESET_CTRL: + case WDT_SW_RESET_MASK1: + case WDT_SW_RESET_MASK2: qemu_log_mask(LOG_UNIMP, "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", __func__, offset); diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index db91ee6b51..e90ef86651 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -21,7 +21,7 @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT) #define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" #define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030" -#define ASPEED_WDT_REGS_MAX (0x20 / 4) +#define ASPEED_WDT_REGS_MAX (0x30 / 4) struct AspeedWDTState { /*< private >*/ From patchwork Fri Dec 30 11:34:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637868 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359535pvb; Fri, 30 Dec 2022 03:37:37 -0800 (PST) X-Google-Smtp-Source: AMrXdXsX064oVH4MzBQ6WAmngJuUgqKLJOXsB6Kw0p3z36rvWVOesgS3Ty0h7d0iEqpwYZlek8hj X-Received: by 2002:ac8:524c:0:b0:3a9:7dd5:6a33 with SMTP id y12-20020ac8524c000000b003a97dd56a33mr49831501qtn.64.1672400257738; Fri, 30 Dec 2022 03:37:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672400257; cv=none; d=google.com; s=arc-20160816; b=IAePSarN11urxDEdsOfaTLQtNq5HfCNNgpnGijF4iJNQoWI/iPuvIzuOkWQuF/CUm3 24Es6TkTTdleNcLZc1qEdmmUKJLb3Ng9zM14+obUCOHt51bT5fAR5Bo0DrwcEs/bUkbn MisqLMvSgh9CQXtif0JfeppLrwnh0TXqfYWLXANW4akUODzRxqfRUYBlk/l+ejlRA6Nr vJfmG0VWqqPIwm4zJLaTvmHQ+vY8HBdKn+xuyfD0KisdUXTVVb+Dz146nP4ArN8wIVyF rlTSAophEtulpX5tCItgg00vAVTxVILza+TZDMZm1/CAHjzXGrV4mDDpzMif9VzcJUWO Fuww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YI/G5H9E5YA8omUhdoABDbtm2oFm0oJUgcY9rScXwCA=; b=HIU9T3cY47aYzpZLhOLlSz+I6vuofP7G/+9zxCBB3Tr2UEN8oI7T8dfpYuqO1S7mpK F1uVbKOZzIT2zXNk0zCiXPM9j84HSZWps1eEyiJwRzDMp6knv/2HX4BwvqN+XuO5HenM bF5D9pw3w8t4dIPJx1IMGhjMsUwNbfuemu/9rW4+O34fgVElcbb6KR5hfLCXBPokAMpG r6nsFTZk63VOjk4NZtG3Kf/etHUEJi8e3GkpGBcGydeuugjOKTQOXbEu5RV7B8gJFqZN 7Usw65yX067UqAChSMk479oX1RnEoYJ1TT4+Lx4LNXxweYl3s0FfrPESEn6Pg47Ud5AW 7tnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SVFtgJ2L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast10x0.c | 3 ++- hw/arm/aspeed_ast2600.c | 3 ++- hw/arm/aspeed_soc.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 122b3fd3f3..3500294df7 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -10,6 +10,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" @@ -348,7 +349,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) sc->name = "ast1030-a1"; sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); sc->silicon_rev = AST1030_A1_SILICON_REV; - sc->sram_size = 0xc0000; + sc->sram_size = 768 * KiB; sc->spis_num = 2; sc->ehcis_num = 0; sc->wdts_num = 4; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index a79e05ddbd..72df72a540 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -8,6 +8,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" @@ -619,7 +620,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) sc->name = "ast2600-a3"; sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); sc->silicon_rev = AST2600_A3_SILICON_REV; - sc->sram_size = 0x16400; + sc->sram_size = 89 * KiB; sc->spis_num = 2; sc->ehcis_num = 2; sc->wdts_num = 4; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 2c0924d311..677342c9ed 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -517,7 +517,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) sc->name = "ast2400-a1"; sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); sc->silicon_rev = AST2400_A1_SILICON_REV; - sc->sram_size = 0x8000; + sc->sram_size = 32 * KiB; sc->spis_num = 1; sc->ehcis_num = 1; sc->wdts_num = 2; @@ -544,7 +544,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) sc->name = "ast2500-a1"; sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); sc->silicon_rev = AST2500_A1_SILICON_REV; - sc->sram_size = 0x9000; + sc->sram_size = 36 * KiB; sc->spis_num = 2; sc->ehcis_num = 2; sc->wdts_num = 3; From patchwork Fri Dec 30 11:34:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637867 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359461pvb; Fri, 30 Dec 2022 03:37:24 -0800 (PST) X-Google-Smtp-Source: AMrXdXtrlhpoJJgPx0X0YSmo477sC4JHr4QR7zUC21B/CyhOxW6coUe/JYQWcitGrrhXZK7X2tDF X-Received: by 2002:a0c:f444:0:b0:4c7:7a7e:805f with SMTP id h4-20020a0cf444000000b004c77a7e805fmr44856430qvm.3.1672400244748; Fri, 30 Dec 2022 03:37:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672400244; cv=none; d=google.com; s=arc-20160816; b=ItJKgOGqC+3MO6RCNz6/dba1V3kNdaAOFIIAzJ7u5oNzTz5Fw/0Enlo/3zfJelT3qx mQU4KJwlp1FtBIyBjVBuWQs6dQeAlCnyyJADZ7zDj0xefn53C8amb5Wp0EJoB642GgGA K9bjNQgjtmyXCLApMbAhiMG/NJd5YmSWpb1Mk07+6SywqO0nwwROYrIYIKHTX4J8jVFT u0yTa5nQIiqA6Fs7rQsfFV8Xrp45L7F4tWQCvTm8hAlwdssDL6vR9mOnzCS4pS4UAugt /JDbUWTEt5HPqH+B7mVm7QySUn6RBG60e39fbmPPqZgnYmoJaZzz+HHBKo3VdNkholt2 AakQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Se9+ZKwl8LvQU91mt3B0+Vzbdjcyd4fnlDtudgozX50=; b=GfcQGs8wYjqsAb2/0aXEWD0TT8+UTxVMmYWAYZX6MiZP0KO6ft02mpwlwh2dYA1pgc ELHWWiUKfvKN/PW1EzkwoBAPNFqwi0APQ28gLWtgOpfsw8g5udP0AYHD5ySVdbU8oE7j R/6hnYUbdvFkWhwyOP4MFruImHAupEOprAq3z45j3LA5zAadnKn1huT4FM+zYN2vM3An 6vkcgHYcx9dw4ApMloPHaICafR7nk2FgmJ6ZnGww9LJle3OtKn/0TJZz4HvZtA8al3jd +8d4D0UDkGiQmvdiqW0VMi1DaOy4T7TMhLWJbCxJuRV5ap7jy1XgyVcfF5u8jtWlWyhv NWPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R1gIu1qQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 30 Dec 2022 03:35:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Troy Lee , Beraldo Leal , Peter Maydell , Wainer dos Santos Moschetta , Andrew Jeffery , Chin-Ting Kuo , Peter Delevoryas , Steven Lee , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin , Peter Delevoryas , Peter Delevoryas , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Cleber Rosa Subject: [PATCH v2 05/11] hw/misc/aspeed_hace: Do not crash if address_space_map() failed Date: Fri, 30 Dec 2022 12:34:58 +0100 Message-Id: <20221230113504.37032-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230113504.37032-1-philmd@linaro.org> References: <20221230113504.37032-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org address_space_map() can fail: uart:~$ hash test sha256_test tv[0]: Segmentation fault: 11 Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault. gen_acc_mode_iov (req_len=0x7ffff18b7778, id=, iov=0x7ffff18b7780, s=0x555556ce0bd0) at ../hw/misc/aspeed_hace.c:171 171 if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) { (gdb) bt #0 gen_acc_mode_iov (req_len=0x7ffff18b7778, id=, iov=0x7ffff18b7780, s=0x555556ce0bd0) at ../hw/misc/aspeed_hace.c:171 #1 do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true) at ../hw/misc/aspeed_hace.c:224 #2 0x00005555559bdbb8 in aspeed_hace_write (opaque=, addr=12, data=262488, size=) at ../hw/misc/aspeed_hace.c:358 This change doesn't fix much, but at least the guest can't crash QEMU anymore. Instead it is still usable: uart:~$ hash test sha256_test tv[0]:hash_final error sha384_test tv[0]:hash_final error sha512_test tv[0]:hash_final error [00:00:06.278,000] hace_global: HACE poll timeout [00:00:09.324,000] hace_global: HACE poll timeout [00:00:12.261,000] hace_global: HACE poll timeout uart:~$ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas Reviewed-by: Cédric Le Goater --- hw/misc/aspeed_hace.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index ac21be306c..12a761f1f5 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -193,6 +193,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, size_t digest_len = 0; int niov = 0; int i; + void *haddr; if (sg_mode) { uint32_t len = 0; @@ -217,9 +218,13 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, addr &= SG_LIST_ADDR_MASK; plen = len & SG_LIST_LEN_MASK; - iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, - MEMTXATTRS_UNSPECIFIED); - + haddr = address_space_map(&s->dram_as, addr, &plen, false, + MEMTXATTRS_UNSPECIFIED); + if (haddr == NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + iov[i].iov_base = haddr; if (acc_mode) { niov = gen_acc_mode_iov(s, iov, i, &plen); @@ -230,10 +235,14 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, } else { hwaddr len = s->regs[R_HASH_SRC_LEN]; + haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], + &len, false, MEMTXATTRS_UNSPECIFIED); + if (haddr == NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + iov[0].iov_base = haddr; iov[0].iov_len = len; - iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], - &len, false, - MEMTXATTRS_UNSPECIFIED); i = 1; if (s->iov_count) { From patchwork Fri Dec 30 11:34:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637874 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359982pvb; Fri, 30 Dec 2022 03:38:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXsd+okxMe0gYCDHORNXMqpzm8hLpcDzdSpe3zMq5WSGO/ywsplVArniZPFDeTDcoL319wgF X-Received: by 2002:a05:6214:1147:b0:531:7d2b:e655 with SMTP id b7-20020a056214114700b005317d2be655mr20644965qvt.22.1672400337056; Fri, 30 Dec 2022 03:38:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672400337; cv=none; d=google.com; s=arc-20160816; b=dGhi0d7nEeY2xktydOW4BBwWay+AHWG16VWmEnsrbvwl2aLgnWjz1080i8VxEMSGOR 7bGzAzqWaGiydwNa4jSZQnNpIn5jVpA/H3XyO8KS/1+gWvEpwU/ONgfsp0kjP3qm1fkQ UyCLc3iiD4fM7/ub5GZEtIUk17nDSbJFUVJa/AevHTM8nlnj1AM/3vBoxYW8dsREGu0k zy3SgNeCO5EHctsAotB9Ml83cnReDNa7Ai1lubuKcyyNT75A/Nc6UL73VbqonW8oBy6/ Pa/d9ac6F5O39sPZgzaj2qUJ/39AsdX9kWwAM20wAsLOXCb4hD2unn5h1kmLAk9U0pGp hPWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Plah9DX/B8cMIAreIJs9xue2YE22a54QEeEtYXjwY1s=; b=tBfcJqVqJVlyOkdonNx5U7q7LscUaq+YavSUDsbxBWPFeUSBJnJm0jnobZ9j/VgQb1 RuMt9fSMBLvEt/TNK6Sr/nAY3D34Yr70J59jEcwEg6dqE7E/67KDEzItO3sp0K8TJfYM Kbla6q6AyoRgnpt6qx2lfbtGic3s0821iSIRFFx4kDnEik+Js/2Y9xTr9BQJJOLdc3I1 0UPlCFxhNObucbOvfP5AcPo1nkU6rOKikdHeBgglcgbAtngh6w38qnKpTNaSB9gSMn+C YftBfASAFzS0zJhzPtMNg0EbDTypfrQPmW4+2uer+x/PzO0YfKISsFLWmmmBhowg40Ef 5QVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HY9kUyV1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07 [2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast10x0.c | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/aspeed_soc.h | 11 +++++++++++ 2 files changed, 46 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 3500294df7..d7dbc1a801 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -28,10 +28,15 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { [ASPEED_DEV_FMC] = 0x7E620000, [ASPEED_DEV_SPI1] = 0x7E630000, [ASPEED_DEV_SPI2] = 0x7E640000, + [ASPEED_DEV_UDC] = 0x7E6A2000, [ASPEED_DEV_SCU] = 0x7E6E2000, + [ASPEED_DEV_JTAG0] = 0x7E6E4000, + [ASPEED_DEV_JTAG1] = 0x7E6E4100, [ASPEED_DEV_ADC] = 0x7E6E9000, + [ASPEED_DEV_ESPI] = 0x7E6EE000, [ASPEED_DEV_SBC] = 0x7E6F2000, [ASPEED_DEV_GPIO] = 0x7E780000, + [ASPEED_DEV_SGPIOM] = 0x7E780500, [ASPEED_DEV_TIMER1] = 0x7E782000, [ASPEED_DEV_UART1] = 0x7E783000, [ASPEED_DEV_UART2] = 0x7E78D000, @@ -79,12 +84,17 @@ static const int aspeed_soc_ast1030_irqmap[] = { [ASPEED_DEV_LPC] = 35, [ASPEED_DEV_PECI] = 38, [ASPEED_DEV_FMC] = 39, + [ASPEED_DEV_ESPI] = 42, [ASPEED_DEV_PWM] = 44, [ASPEED_DEV_ADC] = 46, [ASPEED_DEV_SPI1] = 65, [ASPEED_DEV_SPI2] = 66, [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ + [ASPEED_DEV_UDC] = 9, + [ASPEED_DEV_SGPIOM] = 51, + [ASPEED_DEV_JTAG0] = 27, + [ASPEED_DEV_JTAG1] = 53, }; static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) @@ -155,6 +165,15 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented, TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "sgpiom", &s->sgpiom, + TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "jtag[0]", &s->jtag[0], + TYPE_UNIMPLEMENTED_DEVICE); + object_initialize_child(obj, "jtag[1]", &s->jtag[1], + TYPE_UNIMPLEMENTED_DEVICE); } static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) @@ -337,6 +356,22 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) sc->memmap[ASPEED_DEV_GPIO]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); + + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", + sc->memmap[ASPEED_DEV_PWM], 0x100); + + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi", + sc->memmap[ASPEED_DEV_ESPI], 0x800); + + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc", + sc->memmap[ASPEED_DEV_UDC], 0x1000); + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom", + sc->memmap[ASPEED_DEV_SGPIOM], 0x100); + + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", + sc->memmap[ASPEED_DEV_JTAG0], 0x20); + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", + sc->memmap[ASPEED_DEV_JTAG1], 0x20); } static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 8389200b2d..9a5e3c0bac 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -44,6 +44,7 @@ #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 4 #define ASPEED_UARTS_NUM 13 +#define ASPEED_JTAG_NUM 2 struct AspeedSoCState { /*< private >*/ @@ -87,6 +88,11 @@ struct AspeedSoCState { UnimplementedDeviceState video; UnimplementedDeviceState emmc_boot_controller; UnimplementedDeviceState dpmcu; + UnimplementedDeviceState pwm; + UnimplementedDeviceState espi; + UnimplementedDeviceState udc; + UnimplementedDeviceState sgpiom; + UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; }; #define TYPE_ASPEED_SOC "aspeed-soc" @@ -174,6 +180,11 @@ enum { ASPEED_DEV_DPMCU, ASPEED_DEV_DP, ASPEED_DEV_I3C, + ASPEED_DEV_ESPI, + ASPEED_DEV_UDC, + ASPEED_DEV_SGPIOM, + ASPEED_DEV_JTAG0, + ASPEED_DEV_JTAG1, }; qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); From patchwork Fri Dec 30 11:35:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637865 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359188pvb; Fri, 30 Dec 2022 03:36:32 -0800 (PST) X-Google-Smtp-Source: AMrXdXuP+S3Wpj1Ijq2X2T1RAJrd4rGLsT/UBEDUvj6QlHg9/tlexgUn5i1BMyv72Eo11l/GTC7s X-Received: by 2002:ac8:4153:0:b0:3a7:ee95:cc44 with SMTP id e19-20020ac84153000000b003a7ee95cc44mr43361561qtm.43.1672400191941; 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Fri, 30 Dec 2022 03:35:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Troy Lee , Beraldo Leal , Peter Maydell , Wainer dos Santos Moschetta , Andrew Jeffery , Chin-Ting Kuo , Peter Delevoryas , Steven Lee , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin , Peter Delevoryas , Peter Delevoryas , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Cleber Rosa Subject: [PATCH v2 07/11] hw/arm/aspeed_ast10x0: Map I3C peripheral Date: Fri, 30 Dec 2022 12:35:00 +0100 Message-Id: <20221230113504.37032-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230113504.37032-1-philmd@linaro.org> References: <20221230113504.37032-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since I don't have access to the datasheet, the relevant values were found in: https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Reviewed-by: Peter Delevoryas Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index d7dbc1a801..6c6d33d4a0 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -54,6 +54,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { [ASPEED_DEV_WDT] = 0x7E785000, [ASPEED_DEV_LPC] = 0x7E789000, [ASPEED_DEV_PECI] = 0x7E78B000, + [ASPEED_DEV_I3C] = 0x7E7A0000, [ASPEED_DEV_I2C] = 0x7E7B0000, }; @@ -89,6 +90,7 @@ static const int aspeed_soc_ast1030_irqmap[] = { [ASPEED_DEV_ADC] = 46, [ASPEED_DEV_SPI1] = 65, [ASPEED_DEV_SPI2] = 66, + [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */ [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ [ASPEED_DEV_UDC] = 9, @@ -130,6 +132,8 @@ static void aspeed_soc_ast1030_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); object_initialize_child(obj, "i2c", &s->i2c, typename); + object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); @@ -240,6 +244,18 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); } + /* I3C */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); + for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), + sc->irqmap[ASPEED_DEV_I3C] + i); + /* The AST1030 I3C controller has one IRQ per bus. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); + } + /* PECI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { return; From patchwork Fri Dec 30 11:35:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637866 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359413pvb; Fri, 30 Dec 2022 03:37:14 -0800 (PST) X-Google-Smtp-Source: AMrXdXtcCzvqURlhKHKpfO7sfLDpbICWKC9u5IHsujKe7GwtamHKG+LnzYszbrH9OHUSLHwncU73 X-Received: by 2002:a05:6214:5e92:b0:4c6:2229:1c9c with SMTP id mm18-20020a0562145e9200b004c622291c9cmr41481317qvb.25.1672400233829; Fri, 30 Dec 2022 03:37:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672400233; 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Name it 'secure sram'. Note, the SRAM base address was already present but unused (the 'SBC' index is used for the MMIO peripheral). Interestingly using CFLAGS=-Winitializer-overrides reports: ../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides] [ASPEED_DEV_SBC] = 0x7E6F2000, ^~~~~~~~~~ ../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here [ASPEED_DEV_SBC] = 0x79000000, ^~~~~~~~~~ This fixes with Zephyr: uart:~$ rsa test rsa test vector[0]: [00:00:26.156,000] os: ***** BUS FAULT ***** [00:00:26.157,000] os: Precise data bus error [00:00:26.157,000] os: BFAR Address: 0x79000000 [00:00:26.158,000] os: r0/a1: 0x79000000 r1/a2: 0x00000000 r2/a3: 0x00001800 [00:00:26.158,000] os: r3/a4: 0x79001800 r12/ip: 0x00000800 r14/lr: 0x0001098d [00:00:26.158,000] os: xpsr: 0x81000000 [00:00:26.158,000] os: Faulting instruction address (r15/pc): 0x0001e1bc [00:00:26.158,000] os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0 [00:00:26.158,000] os: Current thread: 0x38248 (shell_uart) [00:00:26.165,000] os: Halting system Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas --- hw/arm/aspeed_ast10x0.c | 11 ++++++++++- include/hw/arm/aspeed_soc.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 6c6d33d4a0..e74e2660ce 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -22,7 +22,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { [ASPEED_DEV_SRAM] = 0x00000000, - [ASPEED_DEV_SBC] = 0x79000000, + [ASPEED_DEV_SECSRAM] = 0x79000000, [ASPEED_DEV_IOMEM] = 0x7E600000, [ASPEED_DEV_PWM] = 0x7E610000, [ASPEED_DEV_FMC] = 0x7E620000, @@ -222,6 +222,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], &s->sram); + memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram", + sc->secsram_size, &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], + &s->secsram); /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -401,6 +409,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); sc->silicon_rev = AST1030_A1_SILICON_REV; sc->sram_size = 768 * KiB; + sc->secsram_size = 9 * KiB; sc->spis_num = 2; sc->ehcis_num = 0; sc->wdts_num = 4; diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 9a5e3c0bac..bd1e03e78a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -71,6 +71,7 @@ struct AspeedSoCState { AspeedSMCState spi[ASPEED_SPIS_NUM]; EHCISysBusState ehci[ASPEED_EHCIS_NUM]; AspeedSBCState sbc; + MemoryRegion secsram; UnimplementedDeviceState sbc_unimplemented; AspeedSDMCState sdmc; AspeedWDTState wdt[ASPEED_WDTS_NUM]; @@ -105,6 +106,7 @@ struct AspeedSoCClass { const char *cpu_type; uint32_t silicon_rev; uint64_t sram_size; + uint64_t secsram_size; int spis_num; int ehcis_num; int wdts_num; @@ -143,6 +145,7 @@ enum { ASPEED_DEV_SCU, ASPEED_DEV_ADC, ASPEED_DEV_SBC, + ASPEED_DEV_SECSRAM, ASPEED_DEV_EMMC_BC, ASPEED_DEV_VIDEO, ASPEED_DEV_SRAM, From patchwork Fri Dec 30 11:35:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637872 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359967pvb; Fri, 30 Dec 2022 03:38:55 -0800 (PST) X-Google-Smtp-Source: AMrXdXvkibafE1r7U0PaL7HBpMSGcT/+Ae5LY51o+7lG4xLrWPExwCHW32f/RouztevVquYlkWxu X-Received: by 2002:a05:6214:2c1f:b0:4f0:b5da:7952 with SMTP id lc31-20020a0562142c1f00b004f0b5da7952mr46857008qvb.27.1672400334937; Fri, 30 Dec 2022 03:38:54 -0800 (PST) ARC-Seal: i=1; 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p4-20020a05600c358400b003d9719a8f7dmr15338125wmq.35.1672400156394; Fri, 30 Dec 2022 03:35:56 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id b22-20020a05600c4e1600b003c6d21a19a0sm28195721wmq.29.2022.12.30.03.35.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 30 Dec 2022 03:35:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Troy Lee , Beraldo Leal , Peter Maydell , Wainer dos Santos Moschetta , Andrew Jeffery , Chin-Ting Kuo , Peter Delevoryas , Steven Lee , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin , Peter Delevoryas , Peter Delevoryas , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Cleber Rosa Subject: [PATCH v2 09/11] hw/arm/aspeed_ast10x0: Map HACE peripheral Date: Fri, 30 Dec 2022 12:35:02 +0100 Message-Id: <20221230113504.37032-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230113504.37032-1-philmd@linaro.org> References: <20221230113504.37032-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since I don't have access to the datasheet, the relevant values were found in: https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Before on Zephyr: uart:~$ hash test sha256_test tv[0]:hash_final error sha384_test tv[0]:hash_final error sha512_test tv[0]:hash_final error [00:00:06.278,000] hace_global: HACE poll timeout [00:00:09.324,000] hace_global: HACE poll timeout [00:00:12.261,000] hace_global: HACE poll timeout uart:~$ crypto aes256_cbc_vault aes256_cbc vault key 1 [00:00:06.699,000] hace_global: aspeed_crypto_session_setup [00:00:06.699,000] hace_global: data->cmd: 1c2098 [00:00:06.699,000] hace_global: crypto_data_src: 93340 [00:00:06.699,000] hace_global: crypto_data_dst: 93348 [00:00:06.699,000] hace_global: crypto_ctx_base: 93300 [00:00:06.699,000] hace_global: crypto_data_len: 80000040 [00:00:06.699,000] hace_global: crypto_cmd_reg: 11c2098 [00:00:09.743,000] hace_global: HACE_STS: 0 [00:00:09.743,000] hace_global: HACE poll timeout [00:00:09.743,000] crypto: CBC mode ENCRYPT - Failed [00:00:09.743,000] hace_global: aspeed_crypto_session_free uart:~$ After: uart:~$ hash test sha256_test tv[0]:PASS tv[1]:PASS tv[2]:PASS tv[3]:PASS tv[4]:PASS sha384_test tv[0]:PASS tv[1]:PASS tv[2]:PASS tv[3]:PASS tv[4]:PASS tv[5]:PASS sha512_test tv[0]:PASS tv[1]:PASS tv[2]:PASS tv[3]:PASS tv[4]:PASS tv[5]:PASS uart:~$ crypto aes256_cbc_vault aes256_cbc vault key 1 Was waiting for: 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10 But got: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [00:00:05.771,000] hace_global: aspeed_crypto_session_setup [00:00:05.772,000] hace_global: data->cmd: 1c2098 [00:00:05.772,000] hace_global: crypto_data_src: 93340 [00:00:05.772,000] hace_global: crypto_data_dst: 93348 [00:00:05.772,000] hace_global: crypto_ctx_base: 93300 [00:00:05.772,000] hace_global: crypto_data_len: 80000040 [00:00:05.772,000] hace_global: crypto_cmd_reg: 11c2098 [00:00:05.772,000] hace_global: HACE_STS: 1000 [00:00:05.772,000] crypto: Output length (encryption): 80 [00:00:05.772,000] hace_global: aspeed_crypto_session_free [00:00:05.772,000] hace_global: aspeed_crypto_session_setup [00:00:05.772,000] hace_global: data->cmd: 1c2018 [00:00:05.772,000] hace_global: crypto_data_src: 93340 [00:00:05.772,000] hace_global: crypto_data_dst: 93348 [00:00:05.772,000] hace_global: crypto_ctx_base: 93300 [00:00:05.772,000] hace_global: crypto_data_len: 80000040 [00:00:05.772,000] hace_global: crypto_cmd_reg: 11c2018 [00:00:05.772,000] hace_global: HACE_STS: 1000 [00:00:05.772,000] crypto: Output length (decryption): 64 [00:00:05.772,000] crypto: CBC mode DECRYPT - Mismatch between plaintext and decrypted cipher text [00:00:05.774,000] hace_global: aspeed_crypto_session_free uart:~$ Reviewed-by: Peter Delevoryas Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast10x0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index e74e2660ce..7a7443a95b 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -29,6 +29,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { [ASPEED_DEV_SPI1] = 0x7E630000, [ASPEED_DEV_SPI2] = 0x7E640000, [ASPEED_DEV_UDC] = 0x7E6A2000, + [ASPEED_DEV_HACE] = 0x7E6D0000, [ASPEED_DEV_SCU] = 0x7E6E2000, [ASPEED_DEV_JTAG0] = 0x7E6E4000, [ASPEED_DEV_JTAG1] = 0x7E6E4100, @@ -166,6 +167,9 @@ static void aspeed_soc_ast1030_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); + snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); + object_initialize_child(obj, "hace", &s->hace, typename); + object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented, TYPE_UNIMPLEMENTED_DEVICE); @@ -359,6 +363,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) } aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); + /* HACE */ + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, + sc->memmap[ASPEED_DEV_HACE]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); + /* Watch dog */ for (i = 0; i < sc->wdts_num; i++) { AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); From patchwork Fri Dec 30 11:35:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637871 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359724pvb; Fri, 30 Dec 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QEMU only implements a M4, which is good enough. Add a TODO note in case the M4F is added. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast10x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 7a7443a95b..a3bcbef24a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -421,7 +421,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) dc->realize = aspeed_soc_ast1030_realize; sc->name = "ast1030-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); + sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ sc->silicon_rev = AST1030_A1_SILICON_REV; sc->sram_size = 768 * KiB; sc->secsram_size = 9 * KiB; From patchwork Fri Dec 30 11:35:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 637873 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3359972pvb; Fri, 30 Dec 2022 03:38:55 -0800 (PST) X-Google-Smtp-Source: AMrXdXs/M5dyO5ldDbg5B9UW1Xo2LtvLeliX9JiG0wn25Vl+5VQyM53m0bdOxyIKh+hHUaLp5EVK X-Received: by 2002:ac8:13cb:0:b0:3a8:2e73:24c9 with SMTP id i11-20020ac813cb000000b003a82e7324c9mr43038215qtj.46.1672400335273; Fri, 30 Dec 2022 03:38:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672400335; cv=none; d=google.com; s=arc-20160816; b=UzHKDuyUeQa+3u0jlOdQCGGt4v8tKJ9ikeu0oR82Ow6uLoz6JIbwQ5dinF+ivi2NPQ UaakQ4moG+HiH+atNXuH9KmSDOadNDzgTz2DYPDwGwM4NNsbt16x3ikYPZvf7rLYadGm lzssFp8nN458fl3+hIvEmDXJJJJYxUPKJ8fpKQ/9AQ5R/LAajjMdkiTcFlbFbWWwB8dW Cy4p/XYgOzO4aNt9GM+qPVtnOOGWqsZZU7YMsYVgj+83UEHjkPWlGBg0AMTEgMoPAk9Y qIb5wkVkqAKe6mR0o0P9U08cE52xrGYaFNDLRh4gKhMUkX+Mc50OxU2dxUno/YSxk3oj Jd7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5mn36Svw49kff47DGBREJk9PPKNIMvzg29Q4dzWpTCM=; b=WGvHKg6oE3KF0n3pAG+S87OtXU03jooeaQgBTb3x2tUHOfzyFicQ2y8PfK/11RAc9J Bmy6KZFkd1tu4tttadsCQIm4MxFg9GvybcWS3i0lDA9+9TZsn0GumdER9EXRAFxI4HbY jLW8Rn7SClHM7eh42n56QMJiH2rl0wU69zaw+o/CgKb0QL9aIc25PgvVXVA3XZYNsr9+ errrnW7gVxAaikKZjG7Vd3ERR3ZFAtRnPebjFwf8FD1ntDojSo6yGl99zzD7PChVvYeR vnVtLPmgoh2TYDLx8AuMi4kh0xrIZexqLj5nxHOgfwZLqarL/PyWh8FqXopbT8J51str mv1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zOjpkTE1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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i7-20020adffc07000000b00288ebd8dc1fmr5110501wrr.55.1672400167252; Fri, 30 Dec 2022 03:36:07 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id c10-20020a5d414a000000b0024242111a27sm20631548wrq.75.2022.12.30.03.36.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 30 Dec 2022 03:36:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Troy Lee , Beraldo Leal , Peter Maydell , Wainer dos Santos Moschetta , Andrew Jeffery , Chin-Ting Kuo , Peter Delevoryas , Steven Lee , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin , Peter Delevoryas , Peter Delevoryas , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Cleber Rosa Subject: [PATCH v2 11/11] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board Date: Fri, 30 Dec 2022 12:35:04 +0100 Message-Id: <20221230113504.37032-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230113504.37032-1-philmd@linaro.org> References: <20221230113504.37032-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a very quick test that runs some commands in a Zephyr shell: $ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado (2/2) tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephyros_1_07: console: *** Booting Zephyr OS build v00.01.07 *** console: ast1030_evb demo console: SOC: AST1030-A1 console: uart:~$ kernel stacks console: 0x36910 wdt_background (real size 1024): unused 988 usage 36 / 1024 (3 %) console: 0x36ad8 shell_uart (real size 4096): unused 3084 usage 1012 / 4096 (24 %) console: 0x2edb8 ADC0 (real size 400): unused 260 usage 140 / 400 (35 %) console: 0x2f0f0 ADC1 (real size 400): unused 260 usage 140 / 400 (35 %) console: 0x3b098 sysworkq (real size 1024): unused 860 usage 164 / 1024 (16 %) console: 0x36cc0 usbdworkq (real size 1024): unused 860 usage 164 / 1024 (16 %) console: 0x36bd8 usbworkq (real size 1024): unused 860 usage 164 / 1024 (16 %) console: 0x36a10 logging (real size 768): unused 548 usage 220 / 768 (28 %) console: 0x36ef8 idle 00 (real size 320): unused 268 usage 52 / 320 (16 %) console: 0x47800 IRQ 00 (real size 2048): unused 1504 usage 544 / 2048 (26 %) console: uart:~$ otp info scu console: SCU BIT reg_protect Description console: ____________________________________________________________________ console: 0x500 0x0 0x0 Disable ARM CM4 CPU boot (TXD5) console: 0x500 0x1 0x0 /Reserved console: 0x500 0x2 0x0 \ " console: 0x500 0x3 0x0 Address offset of single chip ABR mode console: 0x500 0x4 0x0 /Reserved console: 0x500 0x5 0x0 | " console: 0x500 0x6 0x0 | " console: 0x500 0x7 0x0 | " console: 0x500 0x8 0x0 | " console: 0x500 0x9 0x0 | " console: 0x500 0xA 0x0 | " console: 0x500 0xB 0x0 | " console: 0x500 0xC 0x0 | " console: 0x500 0xD 0x0 | " console: 0x500 0xE 0x0 | " console: 0x500 0xF 0x0 | " console: 0x500 0x10 0x0 \ " console: 0x500 0x11 0x0 Disabl3 ARM JTAG debug console: 0x500 0x12 0x0 /Reserved console: 0x500 0x13 0x0 | " console: 0x500 0x14 0x0 | " console: 0x500 0x15 0x0 | " console: 0x500 0x16 0x0 | " console: 0x500 0x17 0x0 | " console: 0x500 0x18 0x0 | " console: 0x500 0x19 0x0 | " console: 0x500 0x1A 0x0 | " console: 0x500 0x1B 0x0 | " console: 0x500 0x1C 0x0 | " console: 0x500 0x1D 0x0 | " console: 0x500 0x1E 0x0 | " console: 0x500 0x1F 0x0 \ " console: 0x510 0x0 0x0 /Reserved console: 0x510 0x1 0x0 | " console: 0x510 0x2 0x0 | " console: 0x510 0x3 0x0 \ " console: 0x510 0x4 0x0 Disable debug interfaces console: 0x510 0x5 0x0 /Reserved console: 0x510 0x6 0x0 | " console: 0x510 0x7 0x0 \ " console: 0x510 0x8 0x0 Enable boot from Uart5 by Pin Strap console: 0x510 0x9 0x0 /Reserved console: 0x510 0xA 0x0 \ " console: 0x510 0xB 0x0 Enable boot SPI ABR console: 0x510 0xC 0x0 Boot SPI ABR Mode console: 0x510 0xD 0x0 /Boot SPI flash size console: 0x510 0xE 0x0 | " console: 0x510 0xF 0x0 \ " console: 0x510 0x10 0x0 /Reserved console: 0x510 0x11 0x0 | " console: 0x510 0x12 0x0 | " console: 0x510 0x13 0x0 | " console: 0x510 0x14 0x0 | " console: 0x510 0x15 0x0 \ " console: 0x510 0x16 0x0 Enable boot SPI auxiliary control pins console: 0x510 0x19 0x0 /Reserved console: 0x510 0x1A 0x0 | " console: 0x510 0x1B 0x0 | " console: 0x510 0x1C 0x0 | " console: 0x510 0x1D 0x0 | " console: 0x510 0x1E 0x0 | " console: 0x510 0x1F 0x0 \ " console: 0x510 0x1E 0x0 Enable dedicate GPIO strap pins console: 0x510 0x1F 0x0 Enable Secure Boot by Pin Strap console: uart:~$ hwinfo devid console: Length: 8 console: ID: 0x0000018000000180 console: uart:~$ crypto aes256_cbc_vault console: aes256_cbc vault key 1 console: Was waiting for: console: 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a console: ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51 console: 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef console: f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10 console: But got: console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 console: uart:~$ random get console: 0x862460d console: uart:~$ i2c scan I2C_0 console: 0 1 2 3 4 5 6 7 8 9 a b c d e f console: 00: -- -- -- -- -- -- -- -- -- -- -- -- console: 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- console: 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- console: 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- console: 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- console: 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- console: 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- console: 70: -- -- -- -- -- -- -- -- console: 1 devices found on I2C_0 console: uart:~$ kernel uptime console: Uptime: 9897 ms console: uart:~$ kernel reboot warm console: *** Booting Zephyr OS build v00.01.07 *** PASS (1.08 s) Ref: https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.07/Aspeed_Zephy_SDK_User_Guide_v00.01.07.pdf Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Delevoryas Reviewed-by: Cédric Le Goater --- tests/avocado/machine_aspeed.py | 41 ++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py index 1fc385e1c8..11f5b17eb9 100644 --- a/tests/avocado/machine_aspeed.py +++ b/tests/avocado/machine_aspeed.py @@ -22,10 +22,11 @@ class AST1030Machine(QemuSystemTest): timeout = 10 - def test_ast1030_zephyros(self): + def test_ast1030_zephyros_1_04(self): """ :avocado: tags=arch:arm :avocado: tags=machine:ast1030-evb + :avocado: tags=os:zephyr """ tar_url = ('https://github.com/AspeedTech-BMC' '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip') @@ -41,6 +42,44 @@ def test_ast1030_zephyros(self): exec_command_and_wait_for_pattern(self, "help", "Available commands") + def test_ast1030_zephyros_1_07(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:ast1030-evb + :avocado: tags=os:zephyr + """ + tar_url = ('https://github.com/AspeedTech-BMC' + '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip') + tar_hash = '40ac87eabdcd3b3454ce5aad11fedc72a33ecda2' + tar_path = self.fetch_asset(tar_url, asset_hash=tar_hash) + archive.extract(tar_path, self.workdir) + kernel_file = self.workdir + "/ast1030-evb-demo/zephyr.bin" + self.vm.set_console() + self.vm.add_args('-kernel', kernel_file, + '-nographic') + self.vm.launch() + wait_for_console_pattern(self, "Booting Zephyr OS") + for shell_cmd in [ + 'kernel stacks', + 'otp info conf', + 'otp info scu', + 'hwinfo devid', + 'crypto aes256_cbc_vault', + 'random get', + 'jtag JTAG1 sw_xfer high TMS', + 'adc ADC0 resolution 12', + 'adc ADC0 read 42', + 'adc ADC1 read 69', + 'i2c scan I2C_0', + 'i3c attach I3C_0', + 'hash test', + 'kernel uptime', + 'kernel reboot warm', + 'kernel uptime', + 'kernel reboot cold', + 'kernel uptime', + ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$") + class AST2x00Machine(QemuSystemTest): timeout = 90