From patchwork Tue Jan 3 19:21:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 639399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B34EDC4708D for ; Tue, 3 Jan 2023 19:27:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233920AbjACT0S (ORCPT ); Tue, 3 Jan 2023 14:26:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239026AbjACTZ7 (ORCPT ); Tue, 3 Jan 2023 14:25:59 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FC3715F17 for ; Tue, 3 Jan 2023 11:24:10 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id p1-20020a05600c1d8100b003d8c9b191e0so24323676wms.4 for ; Tue, 03 Jan 2023 11:24:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tNI2i3/QTr9mwnzcqdEPuyaMkTpSlzmqI4PslyM1ul8=; b=qxSx5Fdwyf6bGTwoSuKdFNu4We3RKaOJPn7Ac30vum4PG/t47eHgGpXzJL6FD+IB2A oyyTrURLu0BvXc3L+5p9gWWHmLUNITzTdzM/aLaEa6MEJtVNvxfgeGKLjSJ6Vb3jw+Jo 6EOQj7WuyEN7C09aPrZKqlk4u9XymrPmpQ/1LxSQ9UcvAKpc4Reeoa3Ea75GTAUXYqc/ GUOZNri9v01AYlnh3UNoFQtEMftB5URL524PL/tOpEpka/ZrD3LbsvRg1SGY11rgm4y/ cF4elqJpQdEtS17VqAY6bNBp64yKBtsVx8Nim3onJJq91WV/9T25MhjPl/+BnuKZFAxY VqDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tNI2i3/QTr9mwnzcqdEPuyaMkTpSlzmqI4PslyM1ul8=; b=iHMYCcPqMxj4X6qnkMRAlpyR4YJTYTpbSZi0LRNGNOyo/Y7pdLYCC9Qeoa7lk1impd 45dKkGdIdQuvjtSZDdK8WCCIOSSCPRRqKQ7fIJXicXYRNiwVb/GEvdcVumLzlV8HuvBH Hs0fCy850ncTDNgyJo0mCyiSKAg8W4cChcMIIOglZbOtSsbuHGhf3ttSV6hvCnr0EPow T6i56CZKzHI8xaSzv6hPFGJTlk5cGIFyVXk9RNnfWvgKYnzyRWPxMM1BtN7bNAa7XLe7 MMw8GUOhD5MVqPIxxFZukRyDcRKWqUHasTPBLeLeC4HRsSxRTxDNcnPIev7ASghx/CH+ NEjQ== X-Gm-Message-State: AFqh2kolwyObPJ0cqHFAlE8cJYC40pSdBRLYGCsQuq+4KY4xa7P3NSVK WCZMvV5x6g5w4y6Dy2mZlQj31A== X-Google-Smtp-Source: AMrXdXuqrH46ThsHvmVdCI+/tUXQjRojKpHrtlChbtGv9OLDKNAUKqs8rJfbW8EBGNiYp0b8sQzBRA== X-Received: by 2002:a05:600c:3495:b0:3c6:e62e:2e74 with SMTP id a21-20020a05600c349500b003c6e62e2e74mr32353682wmq.15.1672773848985; Tue, 03 Jan 2023 11:24:08 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm70803660wms.2.2023.01.03.11.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 11:24:08 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Krzysztof Kozlowski Subject: [PATCH v7 1/4] dt-bindings: clock: Add SM8550 TCSR CC clocks Date: Tue, 3 Jan 2023 21:21:55 +0200 Message-Id: <20230103192158.1155197-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103192158.1155197-1-abel.vesa@linaro.org> References: <20230103192158.1155197-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 55 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 ++++++ 2 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 000000000000..2b72ab82041a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h + +properties: + compatible: + items: + - const: qcom,sm8550-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr", "syscon"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bindings/clock/qcom,sm8550-tcsr.h new file mode 100644 index 000000000000..091cb76f953a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif From patchwork Tue Jan 3 19:21:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 639398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3D22C54EBD for ; Tue, 3 Jan 2023 19:27:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238712AbjACT0T (ORCPT ); Tue, 3 Jan 2023 14:26:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239044AbjACT0A (ORCPT ); Tue, 3 Jan 2023 14:26:00 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98E5415F2A for ; Tue, 3 Jan 2023 11:24:11 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id fm16-20020a05600c0c1000b003d96fb976efso22091340wmb.3 for ; Tue, 03 Jan 2023 11:24:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AC7xaypPibvzJOcPS3LFlREzrhHc51KAqqlF1uf2uTY=; b=d7ajR2Alr5X2wqmACbKstggnV32tdaqHcARBUg1uBx/Q+YRk9qvReJGa8dB3RDnTvc 4G3AcAQORXUyI5VO2xaqJtoQaYwOfVmz+b0kZHvMMfLivgWcMkIQBeemqCHLt5rHf4h+ OwGj/pMlL8f6sQPDjwbW8dpDj+4QYh5A33bn0yHudEuSuAW1CH41shXcr07Ua6R1Lp1T XKO2L90Opf0bN5PNby8i3xPoOchmYo6YlsuVAN34aJ1u9qeH9323ttiq0OXmkGtZmRgi Y1DV1z5B5P0041bMRSYIHFAeKLfPWQWNBQaNM7dGKQvu4jIS34kWz8q0w3B4UXImzq3g tb/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AC7xaypPibvzJOcPS3LFlREzrhHc51KAqqlF1uf2uTY=; b=vTGYNaXqoRDnEk3LlQ6dWAKbgBJ2ds+tpgB0ZQrGzurUP0bN4dxM082L5e0iq79TlY Tmn80Inl7LcIVvvRUcoTg+pmHm+JFnwySgeBl78ZJcZ+56hGmYlPqLTXtPaVumVxXlGD 2A3yHxpqKLq1Dhl/f0cMazJQ2XZXbF+IxsTt63I4bH3GoJ5c49O0hzg92BuYfO0as3tq 9bwoB5v26L8sJpMrLDwbi5rreXGOj3iFRjUNlewLBto5fcRHNKjrwXzYDz5adu3UD8wX y9n1uthJ5NVorEc8AbsDfLv4UqD63WSV8mZR1HoQ7PpRBzgDbsdaHFR/WPZYpTYwpJ1o CWAA== X-Gm-Message-State: AFqh2kqgO0UcbYoGgyVFcLIKZ4sRHdvuziFT/3q1zWXI/c412ie5qmwB UaxKvhPmbuaVlh6YWncD+wenzg== X-Google-Smtp-Source: AMrXdXt7f1MuH6TCbsWh8bb+QHK2GsGaVmkzehB0jLTRKEoWCuIWrMXD/VQ2jAaDLdVcBxzuwRKaAQ== X-Received: by 2002:a7b:c449:0:b0:3d1:e1f4:21dc with SMTP id l9-20020a7bc449000000b003d1e1f421dcmr32261409wmi.14.1672773850108; Tue, 03 Jan 2023 11:24:10 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm70803660wms.2.2023.01.03.11.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 11:24:09 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Krzysztof Kozlowski Subject: [PATCH v7 2/4] dt-bindings: clock: Add RPMHCC for SM8550 Date: Tue, 3 Jan 2023 21:21:56 +0200 Message-Id: <20230103192158.1155197-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103192158.1155197-1-abel.vesa@linaro.org> References: <20230103192158.1155197-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings and update documentation for clock rpmh driver on SM8550. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index cf25ba0419e2..6d7d699aaff9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk clocks: maxItems: 1 From patchwork Tue Jan 3 19:21:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 638765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7C91C54EBE for ; Tue, 3 Jan 2023 19:27:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238864AbjACT0U (ORCPT ); Tue, 3 Jan 2023 14:26:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239082AbjACT0C (ORCPT ); Tue, 3 Jan 2023 14:26:02 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A188915F30 for ; Tue, 3 Jan 2023 11:24:12 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id ay2-20020a05600c1e0200b003d22e3e796dso24358228wmb.0 for ; Tue, 03 Jan 2023 11:24:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DaSJH6qwzBFLaleOV9/RDtj1DHcWd7lA30T3AWhdsIk=; b=FQhvuOHBlauFAqrbw32tVa3t4AjkSwzq9fnMkCTbgzd5mMQmlMUVfydcVqTBuaETxv 69bIXwH03MOOwddsGlbKCkjZfIA+V5K7OXscxkDtnPyrHVWzXivnOsKBPcOqARe4JPF3 ysIH2rSIFhSStel3zLoMAo60KdOURs/D2IhL0g/uhkuttYRHOADPXlis0XD/AZc2Y6yn liqxr3FY2Ht80Iodd9Re1TqI7z0q1tfECmfi2IaWxPZ698XorJU2UydFtUhEgjsxFGrd Urc9sChOrTf3+b4UeTsj5Oz0s4n8m2afDDpmu4E2o66qr5Xoy0wAFh4TrTtBBZOJYagA uGfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DaSJH6qwzBFLaleOV9/RDtj1DHcWd7lA30T3AWhdsIk=; b=kwo9SDiTe1UVVPzUHEeMCBiS8bdYb4Oa5xY2EC5o0GHOboiXgX1G6IupWpN6aTjOax 149nq1/vRO1VwYSorIUKsqOljIW1LePD+n0rjQ+bpk7QXZHwuVBrJnH7db41jeDKMQPP ixTZUoaDot0dRsBBQ8XK7IUnYI7n47oOoPczK4fJaTW242gvjcocm2us4ZiXNlIp9A5c 9yCM+62B5LLApWQXcnFJgaYO7bLKEkNrDYfQfz7oKZ8jBF0Ej865Bm+KgDwERjDDt+om v3B9HwFl5WRj6dkwExDv20OKE5hqchX4eXVshAPeXc2BmC+aoqbuVhKaGQeiHpShayiK ECDg== X-Gm-Message-State: AFqh2kopHlSZgyBBq5mRI3i41VEYh8Chxz9jTRO8tKEkntO6bxXForn6 op1EWlfRZVO+qPDdUvVNPxmdgQ== X-Google-Smtp-Source: AMrXdXsHtJIvXP8sGI8IG18GWiNokmeyBijOoocrUpPlsePdq6TvsYyqkjVVcgCZQAll5jbdmVTcXQ== X-Received: by 2002:a05:600c:600a:b0:3d1:ed41:57c0 with SMTP id az10-20020a05600c600a00b003d1ed4157c0mr35322859wmb.30.1672773851282; Tue, 03 Jan 2023 11:24:11 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm70803660wms.2.2023.01.03.11.24.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 11:24:10 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v7 3/4] clk: qcom: rpmh: Add support for SM8550 rpmh clocks Date: Tue, 3 Jan 2023 21:21:57 +0200 Message-Id: <20230103192158.1155197-4-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103192158.1155197-1-abel.vesa@linaro.org> References: <20230103192158.1155197-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds the RPMH clocks present in SM8550 SoC. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 586a810c682c..7db5a53d73f0 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -366,6 +366,16 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); +DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); +DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); +DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); +DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); +DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); + +DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); +DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); +DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); + DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); DEFINE_CLK_RPMH_BCM(ce, "CE0"); @@ -576,6 +586,31 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = { .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), }; +static struct clk_hw *sm8550_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm8550 = { + .clks = sm8550_rpmh_clocks, + .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), +}; + static struct clk_hw *sc7280_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, @@ -742,6 +777,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, + { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, { } }; 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Tue, 03 Jan 2023 11:24:12 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm70803660wms.2.2023.01.03.11.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 11:24:11 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v7 4/4] clk: qcom: Add TCSR clock driver for SM8550 Date: Tue, 3 Jan 2023 21:21:58 +0200 Message-Id: <20230103192158.1155197-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103192158.1155197-1-abel.vesa@linaro.org> References: <20230103192158.1155197-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The TCSR clock controller found on SM8550 provides refclks for PCIE, USB and UFS. Add clock driver for it. This patch is based on initial code downstream. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 7 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-sm8550.c | 192 +++++++++++++++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 drivers/clk/qcom/tcsrcc-sm8550.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 70d43f0a8919..b9f5505d68f0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -797,6 +797,13 @@ config SM_GPUCC_8350 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_TCSRCC_8550 + tristate "SM8550 TCSR Clock Controller" + select QCOM_GDSC + help + Support for the TCSR clock controller on SM8550 devices. + Say Y if you want to use peripheral devices such as SD/UFS. + config SM_VIDEOCC_8150 tristate "SM8150 Video Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f18c446a97ea..f5ce429c724c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o +obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c new file mode 100644 index 000000000000..2c67ee71c196 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_pcie_0_clkref_en = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_1_clkref_en = { + .halt_reg = 0x15114, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15114, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_clkref_en = { + .halt_reg = 0x15110, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15110, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_ufs_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_pad_clkref_en = { + .halt_reg = 0x15104, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15104, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_ufs_pad_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_clkref_en = { + .halt_reg = 0x15118, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15118, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_clkref_en = { + .halt_reg = 0x15108, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x15108, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb3_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_sm8550_clocks[] = { + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr, + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, + [TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_sm8550_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x2f000, + .fast_io = true, +}; + +static const struct qcom_cc_desc tcsr_cc_sm8550_desc = { + .config = &tcsr_cc_sm8550_regmap_config, + .clks = tcsr_cc_sm8550_clocks, + .num_clks = ARRAY_SIZE(tcsr_cc_sm8550_clocks), +}; + +static const struct of_device_id tcsr_cc_sm8550_match_table[] = { + { .compatible = "qcom,sm8550-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table); + +static int tcsr_cc_sm8550_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &tcsr_cc_sm8550_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap); +} + +static struct platform_driver tcsr_cc_sm8550_driver = { + .probe = tcsr_cc_sm8550_probe, + .driver = { + .name = "tcsr_cc-sm8550", + .of_match_table = tcsr_cc_sm8550_match_table, + }, +}; + +static int __init tcsr_cc_sm8550_init(void) +{ + return platform_driver_register(&tcsr_cc_sm8550_driver); +} +subsys_initcall(tcsr_cc_sm8550_init); + +static void __exit tcsr_cc_sm8550_exit(void) +{ + platform_driver_unregister(&tcsr_cc_sm8550_driver); +} +module_exit(tcsr_cc_sm8550_exit); + +MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver"); +MODULE_LICENSE("GPL");