From patchwork Tue Jan 3 15:04:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 639418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E0C8C3DA7D for ; Tue, 3 Jan 2023 15:05:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237822AbjACPFA (ORCPT ); Tue, 3 Jan 2023 10:05:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237815AbjACPEq (ORCPT ); Tue, 3 Jan 2023 10:04:46 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A989511C1C for ; Tue, 3 Jan 2023 07:04:45 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id d15so32844906pls.6 for ; Tue, 03 Jan 2023 07:04:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=03EcVfcgn594UPANtn877VRHUEcrNy316gwc2wdWerc=; b=tAwja7qo6FA2QF9L8ZZa7e1lkzKJIkHyamwXHR8tc68vLGODBiKjEwpCCvC3tVNHto GJ25c8hpVSOWLPbOOef61/cw7aE7hz4j2AS/p07Xr9ZabWXVpPx6SMVrZm7VIqp4AnR1 ZR+oSg5R22/Q7d1APEIpAhzuwtEFPtFGajKBXLK4BJGmVDSTprTOk8rh+LigIGcwhnHp GJSUHSv0l4LndZ1lXBm1zGKaEcCxOp9n3JC3tBiEWGt3BdyTl1wQekbWmH3CGnIBbFQg 66lXT7/e7JpToyvPe/SqolNVQ5+Z9jdllB+XTXg5KVxqkXLYjIeMIGf+ii9e54kqDwgT O6Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=03EcVfcgn594UPANtn877VRHUEcrNy316gwc2wdWerc=; b=MeJsAbjLWAteSXuIcONgi/m3/n/UUWvB1JD/fIvtzItYkGn7m9jGcW2t78kCOkopX+ AomUmoOZKVRt9PNUT9pfXKyzjSEuuc70y9Q+3QomUgg7HoUJ/JyTwLz6kll4s/lLVzs9 9RQceQbSHJC/5a+eD2iQDHvZ0MYgGk8gxVRIdvLDDAxUPRfMoCSw+GBH61zN4qXCXLGS sHg8EyrnTTaqMCUr48dwRBAjMczC8SR13Ng0EHyUk9r1uJNM6JhSVrSTONLzEvfakU4O S71cOwsTzBAX+1hHKV95g4ue3NHRuMPZRFEGoSkESp9QnWv2ZyLiHKbJP5Pjv/CAU0o6 eMuQ== X-Gm-Message-State: AFqh2kpw/WVqsl0Rtz1ZVjmmnJMJR27P7gQT+iMLlxPkK5JiSppOuF59 P7mcokwIlQD4b83m6k1S01uPAMn/BfS1/OhqGLI= X-Google-Smtp-Source: AMrXdXvIFIE4chcolI2qPMy9u0aChMMw3jLshK+Aq/mEXy7smiHsERS9+ufNo/GRVN/x/LXdVAie5Q== X-Received: by 2002:a17:90b:485:b0:20d:bd5e:d54a with SMTP id bh5-20020a17090b048500b0020dbd5ed54amr46844701pjb.21.1672758284721; Tue, 03 Jan 2023 07:04:44 -0800 (PST) Received: from localhost.localdomain ([2401:4900:1c5e:e3b5:c341:16de:ce17:b857]) by smtp.gmail.com with ESMTPSA id 8-20020a17090a0f0800b0021952b5e9bcsm20952300pjy.53.2023.01.03.07.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 07:04:44 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_schowdhu@quicinc.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH v2 1/2] dt-bindings: soc: qcom: eud: Add SM6115 / SM4250 binding Date: Tue, 3 Jan 2023 20:34:18 +0530 Message-Id: <20230103150419.3923421-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230103150419.3923421-1-bhupesh.sharma@linaro.org> References: <20230103150419.3923421-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property required by the driver on these SoCs. Cc: Souradeep Chowdhury Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index c98aab209bc5d..1dffe14868735 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,12 +18,22 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: + minItems: 2 items: - description: EUD Base Register Region - description: EUD Mode Manager Register + - description: TCSR Check Register + + reg-names: + minItems: 2 + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-check-base interrupts: description: EUD interrupt From patchwork Tue Jan 3 15:04:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 638782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 415AEC46467 for ; Tue, 3 Jan 2023 15:05:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233544AbjACPFB (ORCPT ); Tue, 3 Jan 2023 10:05:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237948AbjACPEv (ORCPT ); Tue, 3 Jan 2023 10:04:51 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A982411A10 for ; Tue, 3 Jan 2023 07:04:50 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id n12so20247556pjp.1 for ; Tue, 03 Jan 2023 07:04:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N13vpL6q9P0WudTM1gFfahAVjoJ4UnTdBTjpXvHDPN4=; b=fAhuk6kMp791OWqVdI0FD/kqqSvppMpzbLNlO8XgrHygfFi+VOJiX6JfcTBC4UZ9dG kPCbEGi9xotF2PfePRt9GR7ZsNe43J0DY6xqF2dzRgmBcNqbX/dsH3bj1iN8VbBLXy69 nE0WwAn/6EC0ht2IPyIE+L+JG+KYmyhqcDAdiW773VASGgZAVEw8mIECSZm7/DY9lby1 Y4f1Ao0hfkuMOGK+YSGKvn+aNqoKQoQ1bv+SvAWrW+On4kH5MSTbbWhRGDc/RVs3eMqm EVxBaTsX0n+YptQmI7YtFUH4dOK8EN1O/kxzz8bLw40cdNAYI+Pd6hQ7SEnRAzQnFkZA tffw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N13vpL6q9P0WudTM1gFfahAVjoJ4UnTdBTjpXvHDPN4=; b=iPPqjtyyu/dOH0ivRtuEvdtAjkDBdj79fn9NQR5rUcm5JiTmUllPBIbE9i7470WyKV rMEx9Q0xpHulkLRiHnskGbMumks6a4SX8zGSHd01mxnNOrMU/SOL3h9L8uQpUxL+RGK9 4j1BrRwxPXXlYrRovxHjajUMbLJMwK4LNeGqVXqq2O1lYwZHuTRjuUbnJil3qv3dKQx4 yR0VsT5SQW9F6LXR544N00s/BracP6EGLAuxEVe9uSOmSBQerUzP5RS5dtGxDRdNM1Dg 0qZbkadmYLnaBdIr+gRZvPpB01DaPVOIJ0TanLpAeNjzMGVWEMrJTYvjGIVqlQpLxzg0 k9rg== X-Gm-Message-State: AFqh2kr3fByoP3l8QzinGpytA7uGsXU5BNP0Neq3bPtn8kH4AUrBJc6C uIpwBcGrlpZYFtmbHwrjjro+sJFGBiQnnXRqXHE= X-Google-Smtp-Source: AMrXdXu/v7kZRf/c0WyJrK50QNP+TUaXV7Kd2o6twyvDsRq1+UHAWhoNwU9BGEPmL6OajdvAk7vVlg== X-Received: by 2002:a17:90a:8a08:b0:223:3642:f74f with SMTP id w8-20020a17090a8a0800b002233642f74fmr53242910pjn.0.1672758289750; Tue, 03 Jan 2023 07:04:49 -0800 (PST) Received: from localhost.localdomain ([2401:4900:1c5e:e3b5:c341:16de:ce17:b857]) by smtp.gmail.com with ESMTPSA id 8-20020a17090a0f0800b0021952b5e9bcsm20952300pjy.53.2023.01.03.07.04.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 07:04:49 -0800 (PST) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org Cc: quic_schowdhu@quicinc.com, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH v2 2/2] usb: misc: eud: Add driver support for SM6115 / SM4250 Date: Tue, 3 Jan 2023 20:34:19 +0530 Message-Id: <20230103150419.3923421-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230103150419.3923421-1-bhupesh.sharma@linaro.org> References: <20230103150419.3923421-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SM6115 / SM4250 SoC EUD support in qcom_eud driver. On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Cc: Souradeep Chowdhury Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 1 + drivers/usb/misc/qcom_eud.c | 49 ++++++++++++++++++++++++++++++++++--- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index a5f7652db7da1..ed4ae32ff1577 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -140,6 +140,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" depends on ARCH_QCOM || COMPILE_TEST + select QCOM_SCM select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index b7f13df007646..a96ca28a4899b 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -30,15 +32,24 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +struct eud_soc_data { + bool secure_eud_en; + bool tcsr_check_enable; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_data *eud_data; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + phys_addr_t mode_mgr_phys_base; + phys_addr_t tcsr_check_phys_base; + }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +57,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->eud_data->secure_eud_en) + qcom_scm_io_writel(priv->mode_mgr_phys_base + EUD_REG_EUD_EN2, BIT(0)); + else + writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +69,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->eud_data->secure_eud_en) + qcom_scm_io_writel(priv->mode_mgr_phys_base + EUD_REG_EUD_EN2, 0); + else + writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,12 +197,15 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; + chip->eud_data = of_device_get_match_data(&pdev->dev); + chip->dev = &pdev->dev; chip->role_sw = usb_role_switch_get(&pdev->dev); @@ -200,10 +222,25 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + chip->mode_mgr = devm_platform_get_and_ioremap_resource(pdev, 1, &res); if (IS_ERR(chip->mode_mgr)) return PTR_ERR(chip->mode_mgr); + if (chip->eud_data->secure_eud_en) + chip->mode_mgr_phys_base = res->start; + + if (chip->eud_data->tcsr_check_enable) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, "failed to get tcsr reg base\n"); + + chip->tcsr_check_phys_base = res->start; + + ret = qcom_scm_io_writel(chip->tcsr_check_phys_base, BIT(0)); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } + chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, handle_eud_irq_thread, IRQF_ONESHOT, NULL, chip); @@ -230,8 +267,14 @@ static int eud_remove(struct platform_device *pdev) return 0; } +static const struct eud_soc_data sm6115_eud_data = { + .secure_eud_en = true, + .tcsr_check_enable = true, +}; + static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_data }, { } }; MODULE_DEVICE_TABLE(of, eud_dt_match);