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Thu, 5 Jan 2023 19:14:06 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.167.28]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Np7j93S2nz1RvLy; Thu, 5 Jan 2023 19:14:05 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v3 02/43] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Date: Fri, 6 Jan 2023 13:13:16 +1000 Message-Id: <20230106031357.777790-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> References: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=363443eaf=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson We were matching a signed 13-bit range, not a 12-bit range. Expand the commentary within the function and be explicit about all of the ranges. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 81a83e45b1..191197853f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) if ((ct & TCG_CT_CONST_ZERO) && val == 0) { return 1; } - if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { + /* + * Sign extended from 12 bits: [-0x800, 0x7ff]. + * Used for most arithmetic, as this is the isa field. + */ + if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { return 1; } - if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { + /* + * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. + * Used for subtraction, where a constant must be handled by ADDI. + */ + if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { return 1; } - if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) { + /* + * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. + * Used by addsub2, which may need the negative operation, + * and requires the modified constant to be representable. + */ + if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { return 1; } return 0; From patchwork Fri Jan 6 03:13:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 639682 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp557477pvb; Thu, 5 Jan 2023 19:25:44 -0800 (PST) X-Google-Smtp-Source: AMrXdXufFV8Qyh2Js7UraIe/mtcSEXfhcYtvT66RHhzz6GG10FSvvpMDWAjT3+pVgsJy44iCBXp6 X-Received: by 2002:ac8:4a93:0:b0:3a7:ec9b:e00b with SMTP id l19-20020ac84a93000000b003a7ec9be00bmr72940224qtq.68.1672975544505; Thu, 05 Jan 2023 19:25:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672975544; cv=none; d=google.com; s=arc-20160816; b=GbIW0OPjDwo29ayIaQAvNKvA7Gi8b4QXWxSFmnm1s4vp4v4EpteXm0KfSUHptJoLdd KOUEiZgnFT/lpVwWvVYSj2GjgVXAlCj3PUbKPJbqUY7SfqddNaX30GnBHzaPEWmoiHpP RQkvbiUHXVtYpyK/xzsY+LZ8vmweHPfw1av9t5NuNIxsFg55yMneYp321Pg+scHTGKIf /sijST2W8ehYNmJtSgZray6MQP55l8c3BHNd2HwMxGzSPu3jMJZh6scwca3k7+H/jlBQ f/YEUbMJAKO5v75klStB27nG0dv9Y1ulSjpSc3/C9DqynCDhNhOk9xMHpGAImSJKmISX VYSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=fAjOW6m8qjTK+dJoVF8LPAKwYwq64fWEQwayude7M44=; b=048KUWrEOGJBjcagskezz9TLfxBs0U4/XiqRKRZo7JCJQEp38AHZ8pKwjzqYkYWxf4 3VU8X2PkzHaLxgfBXXuThVk5Yq4a2hhwb6Kl/UA0rbbIhnF2dysJx0IIpftCpR9qa+ZJ ezShmvT6L/Cr5Y8i8RtlRB99Kq//l0jWuQHoVcczIHrlMLgcAxd1APB5S3pNVEL2A3WE b1PJYk0S9+oc3Q/EfUTvSnnGXS32+RSbYQsOZLInUuJ7+/jFmoscaIySVR20ujW2zOZv qtadoFx0wUe7OU80r2UszPdU0EB4KaXaEAKDzYb1+zhumcBJAoeyCU6CiN3fUgKx3RJY JjoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=g2WCqfWi; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b=cAy1nbxO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 5 Jan 2023 19:14:08 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.167.28]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Np7jC1Tr9z1RvTp; Thu, 5 Jan 2023 19:14:07 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v3 03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Date: Fri, 6 Jan 2023 13:13:17 +1000 Message-Id: <20230106031357.777790-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> References: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=363443eaf=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson There was a typo using opc_addi instead of opc_add with the two registers. While we're at it, simplify the gating test to al == bl to improve dynamic scheduling even when the output register does not overlap the inputs. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 191197853f..2a84c57bec 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -700,9 +700,15 @@ static void tcg_out_addsub2(TCGContext *s, if (cbl) { tcg_out_opc_imm(s, opc_addi, rl, al, bl); tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); - } else if (rl == al && rl == bl) { + } else if (al == bl) { + /* + * If the input regs overlap, this is a simple doubling + * and carry-out is the input msb. This special case is + * required when the output reg overlaps the input, + * but we might as well use it always. + */ tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); - tcg_out_opc_reg(s, opc_addi, rl, al, bl); + tcg_out_opc_reg(s, opc_add, rl, al, al); } else { tcg_out_opc_reg(s, opc_add, rl, al, bl); tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, From patchwork Fri Jan 6 03:13:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 639684 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp559552pvb; Thu, 5 Jan 2023 19:33:40 -0800 (PST) X-Google-Smtp-Source: AMrXdXuau5aIHdpRDSdGbZaeEPS7qTuDTWw6c1zr+3LLNLnB0rMiD/HxloE7Kc2swiia2OChhPG4 X-Received: by 2002:a0c:c683:0:b0:531:e1dd:c4d0 with SMTP id d3-20020a0cc683000000b00531e1ddc4d0mr12138938qvj.37.1672976020709; Thu, 05 Jan 2023 19:33:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672976020; cv=none; d=google.com; s=arc-20160816; b=eSWWmHR5K/xg6fy09AaNZYjBHlnAZvhPC680Ns+rCnvF64shhHQFDhRd4nBAaAWWpP SzbG93KK3PlXGlIVqeq99fOnfUqg03vF74T/iMKz03P/gtfCm+ZxUWCPTSvorNlQznIx lpiNfvO09R/USdWoo9siM7PoiXoav56IOXYtkIX8xQD+nejqzy5XlV9Z6BQAd+i01CZ4 c9abK4rWRfvNIdD47VbmMV1rsWwF/SMHl9VGOfofr23+zG5jJuQqkpY9A97qB1bFF7MR FjxwZ6MXz0qsexy5T+hRhqiQT5FYepmkgORI82paGAXPABpI2SnSThIEBcceUwijbOtK ixcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=L+ny14Ho9Lb9GMMafw22bddYzOnRzAd9u7koV+v0olc=; b=nbv5V+e3Ocvh5ijJ9YJPm1wpTMYjNbnGjJvdUNr4AaUsmKnviKrNx1IhAKR2GIOgi9 +3Ov+sVQzx37wqnQLfzNsB1IPLvjSyyjiRUVoHcfXX+hBjYoggHSmqrv6LzM2CQq5OQ6 dj4VnWh/g9SlBuQaSpLejMrr2ZzK1NbNbNPpjEjbGior29vfd93OVU2Y/xLHWftEx3HG kBElCoF8rYlKw0W3vPsYC8z5NaloLAy7H9nhqW99IB3OKfOGx8wEA+clytMXocNR+/B3 v4fOPiaDL3D365Y97Kg6gvse6si1gilUUAXpbWDgZg2geYPk07IucJLkX4O1a1C7yW8w jDhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=F1Q8rczy; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b=PpdZBxYy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 5 Jan 2023 19:14:10 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.167.28]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Np7jF0QXQz1Rwrq; Thu, 5 Jan 2023 19:14:08 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v3 04/43] tcg/riscv: Fix base register for user-only qemu_ld/st Date: Fri, 6 Jan 2023 13:13:18 +1000 Message-Id: <20230106031357.777790-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> References: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=363443eaf=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set base after each step of the address arithmetic instead of before. Return the base register used from tcg_out_tlb_load, so as to keep that register choice localized to that function. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 39 +++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2a84c57bec..e3b608034f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -923,9 +923,9 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) tcg_debug_assert(ok); } -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, + TCGReg addrh, MemOpIdx oi, + tcg_insn_unit **label_ptr, bool is_load) { MemOp opc = get_memop(oi); unsigned s_bits = opc & MO_SIZE; @@ -975,6 +975,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, addrl = TCG_REG_TMP0; } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); + return TCG_REG_TMP0; } static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, @@ -1177,7 +1178,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base = TCG_REG_TMP0; + TCGReg base; data_regl = *args++; data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); @@ -1187,23 +1188,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } a_bits = get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, a_bits); } + base = addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base = TCG_REG_TMP0; + } if (guest_base != 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); + base = TCG_REG_TMP0; } tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); #endif @@ -1249,7 +1252,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base = TCG_REG_TMP0; + TCGReg base; data_regl = *args++; data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); @@ -1259,23 +1262,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } a_bits = get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_regl, a_bits); } + base = addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base = TCG_REG_TMP0; + } if (guest_base != 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); + base = TCG_REG_TMP0; } tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); #endif From patchwork Fri Jan 6 03:13:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 639680 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp556659pvb; Thu, 5 Jan 2023 19:22:30 -0800 (PST) X-Google-Smtp-Source: AMrXdXsjaE9Lb/j+iKjPMOhU1nz3i6wilGgdfF6ddsoPR/AK5MhUbFBjDxKty6/yyQvaqVHKZZEv X-Received: by 2002:a0c:fba2:0:b0:531:e436:8e92 with SMTP id m2-20020a0cfba2000000b00531e4368e92mr12374913qvp.22.1672975350578; Thu, 05 Jan 2023 19:22:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672975350; cv=none; d=google.com; s=arc-20160816; b=Tw1huFkZLvF3cGap02MDNMUyABc77gx6StPbKkZ10r2i8BFnd5IEBpQFQuJG5SWtOd Ons9wcZutTTj8XWgj0gHq3pUrAoFjHAEzzwb8opPlwAnkYMHEqJww7EIYX6rSTXxYp7M Woql38DEPDRw3D0MYDI0uuBz4rU8NTgbE4kjVmVZZ6/VWI8ffZ2jLXO7sphUgNnpjEuR SXQsZ0ij0FG4aTL1M/HeVJHd1Y/QilOcV30/QW/sGlDtXNeYIYXFCxt5LmIvyi7i0uni p8bIBJM1DJ1QL4fSxcbsV7kkHNzpPCbZznO4Jp5lO00YbXjAJku62MUwcZqSYM7kiaCI WJgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=E/UFlvEJuy5SMJDOC861oXE3EQVR7305wMbCOx6laiQ=; b=yx3WS+X6TR2V/wOujAYQ3fbeW/respoJn4LlLzdKllLgyzY2gZo+HyoTuv/VvAg1ST wb/d1xDV1qBq/OXNooNowFrb4CEaWDxEnQ51Iu8z4vSqXN7mIDod/Lwn/SStNe5En6lo tTj9I8QAaa2WTZD0L3oqADHKR4yoy3qcYH/0NL5SArbPzjFhjhk3JWfARIU9IHR2rDNq Slh5OvpWJv68LTtecB4dWVqwyDQ5MfLw5kujLj1+Hh5GsMRzo4a5weefCjFPxalS+rUz vek3n7850ih6vS5FIHy2b1GIZ/6Te2jDqb5VZsGHqRUkVxeH5N196R22kVuRQH4ZvI7M ArKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=YEKyvweB; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b=jMFI1lFt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 5 Jan 2023 19:14:46 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.167.28]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Np7jw4kKwz1RvTp; Thu, 5 Jan 2023 19:14:44 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , qemu-stable@nongnu.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL v3 24/43] target/riscv: Set pc_succ_insn for !rvc illegal insn Date: Fri, 6 Jan 2023 13:13:38 +1000 Message-Id: <20230106031357.777790-25-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> References: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=363443eaf=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis --- target/riscv/translate.c | 12 ++++-------- tests/tcg/Makefile.target | 2 ++ tests/tcg/riscv64/Makefile.target | 6 ++++++ tests/tcg/riscv64/test-noc.S | 32 +++++++++++++++++++++++++++++++ 4 files changed, 44 insertions(+), 8 deletions(-) create mode 100644 tests/tcg/riscv64/test-noc.S diff --git a/target/riscv/translate.c b/target/riscv/translate.c index cd5eb25ee8..160aefc3df 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1096,14 +1096,10 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) ctx->virt_inst_excp = false; /* Check for compressed insn */ if (insn_len(opcode) == 2) { - if (!has_ext(ctx, RVC)) { - gen_exception_illegal(ctx); - } else { - ctx->opcode = opcode; - ctx->pc_succ_insn = ctx->base.pc_next + 2; - if (decode_insn16(ctx, opcode)) { - return; - } + ctx->opcode = opcode; + ctx->pc_succ_insn = ctx->base.pc_next + 2; + if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { + return; } } else { uint32_t opcode32 = opcode; diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 75257f2b29..14bc013181 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -117,6 +117,8 @@ endif %: %.c $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) +%: %.S + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) else # For softmmu targets we include a different Makefile fragement as the # build options for bare programs are usually pretty different. They diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target index b5b89dfb0e..cc3ed65ffd 100644 --- a/tests/tcg/riscv64/Makefile.target +++ b/tests/tcg/riscv64/Makefile.target @@ -4,3 +4,9 @@ VPATH += $(SRC_PATH)/tests/tcg/riscv64 TESTS += test-div TESTS += noexec + +# Disable compressed instructions for test-noc +TESTS += test-noc +test-noc: LDFLAGS = -nostdlib -static +run-test-noc: QEMU_OPTS += -cpu rv64,c=false +run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false diff --git a/tests/tcg/riscv64/test-noc.S b/tests/tcg/riscv64/test-noc.S new file mode 100644 index 0000000000..e29d60c8b3 --- /dev/null +++ b/tests/tcg/riscv64/test-noc.S @@ -0,0 +1,32 @@ +#include + + .text + .globl _start +_start: + .option norvc + li a0, 4 /* SIGILL */ + la a1, sa + li a2, 0 + li a3, 8 + li a7, __NR_rt_sigaction + scall + + .option rvc + li a0, 1 + j exit + .option norvc + +pass: + li a0, 0 +exit: + li a7, __NR_exit + scall + + .data + /* struct kernel_sigaction sa = { .sa_handler = pass }; */ + .type sa, @object + .size sa, 32 +sa: + .dword pass + .zero 24 +