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[209.51.188.17]) by mx.google.com with ESMTPS id t28-20020a05622a181c00b003ae7148c300si2819887qtc.701.2023.01.10.09.25.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Jan 2023 09:25:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KP7J3iaA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFHjY-0003pQ-E2; Tue, 10 Jan 2023 11:44:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFHjX-0003ok-Bn for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:44:19 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFHjV-00067k-KC for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:44:19 -0500 Received: by mail-wm1-x329.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so7564958wma.1 for ; Tue, 10 Jan 2023 08:44:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u1UvOGw1kKWk2oCncOSRw+9G4LoKd5mu7gj6ezPK4v8=; b=KP7J3iaAZ3p0trPjScaTftxGfKhSe3lCN9IT9MhIY8TwBgmm0j3PkUVDpDYA83Az9C ZVMWvpyOxZ5JA+qZFXie+kpd6fdZAGLr9QBoG7oOwZculXwRIiidGh9dVLE8imGtpE1y c0ch2FBpHvUgS+RrHwg18uABHPD3jDbkz2Unve3EG+J+rpAB/dLThXazNSQYM/deX4sb IMvJpqhxkK3739pRbnj1vUk1GhPIHYeXcQsRmtb61gYUR9E5/DT88Zk7e50STVMpMClu DqgDUQSwn0BaMsYjsUPAoyylAN2861l9tl2cG3FliPIk5KRiCcNMcPkCvJniFXFcH7Nq +PIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u1UvOGw1kKWk2oCncOSRw+9G4LoKd5mu7gj6ezPK4v8=; b=5daKJcGSLUSCSlNAX1/swl34ZV1A3seGnNanQ+hHEAtCFvzAZDu+KGNrJwpkjDGIZo b/gAhmp6DmAHfcAnSsQJ8xxbdTLzztP72R9CBxYyzcrRkEvgXtG1U3v9IxZGOc38M9hU LUXymVkZF8UvZMjd8PXxatM1ZhrtKDJRUHS9dcgAn+a/UkXN9NNjI5Uvxwp8xT2EC6jy GmPMijoU/424QnuOyj/qdSMeIjvyicG4ptRQ/eYh9v+Ak6uDzGZ2EUC3mZaYuHsQKS+o uHgLzcsbm4x5TBluKQ4XBpF8bsqCj9edeaDao1V2TDxDPuvy1mTY8VWqYPVdQeYnRvLO kbNg== X-Gm-Message-State: AFqh2kqAqH9wa5QzHVHA5+Stf6Y6IKI8sKMx3kmkyVZFsFeZlfuI+VvJ jaAOEWTDgyb1JTkTm/rrf6WV13CEJV5qOyDw X-Received: by 2002:a1c:7c14:0:b0:3d1:f74d:4f60 with SMTP id x20-20020a1c7c14000000b003d1f74d4f60mr53524556wmc.22.1673369055791; Tue, 10 Jan 2023 08:44:15 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id m18-20020a05600c4f5200b003c6b70a4d69sm17665984wmq.42.2023.01.10.08.44.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jan 2023 08:44:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 01/18] hw/arm: Move various units to softmmu_ss[] Date: Tue, 10 Jan 2023 17:43:49 +0100 Message-Id: <20230110164406.94366-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230110164406.94366-1-philmd@linaro.org> References: <20230110164406.94366-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_ss[] units are built twice: once for 32-bit word size and once for 64-bit. The following units don't require any word size knowledge and can be moved to softmmu_ss[] (where they are built once): - smmu-common.c - exynos4_boards.c - bcm2835_peripherals.c - tosa.c Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 92f9f6e000..4babaa8dfc 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -3,7 +3,6 @@ arm_ss.add(files('boot.c'), fdt) arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) -arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) @@ -18,7 +17,6 @@ arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) -arm_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) @@ -38,7 +36,7 @@ arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) -arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) +arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) @@ -59,8 +57,13 @@ arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) -arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c', 'smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) +softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) +softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) +softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) +softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) + hw_arch += {'arm': arm_ss} From patchwork Tue Jan 10 16:43:50 2023 Content-Type: text/plain; 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Include this header in order to avoid when refactoring headers: ../hw/arm/boot.c:281:5: error: implicit declaration of function 'address_space_stl_notdirty' is invalid in C99 [-Werror,-Wimplicit-function-declaration] address_space_stl_notdirty(as, info->smp_bootreg_addr, ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/boot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3d7d11f782..f5bfb922b1 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -25,6 +25,7 @@ #include "qemu/config-file.h" #include "qemu/option.h" #include "qemu/units.h" +#include "exec/cpu-all.h" /* Kernel boot protocol is specified in the kernel docs * Documentation/arm/Booting and Documentation/arm64/booting.txt From patchwork Tue Jan 10 16:43:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640847 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2807149pvb; Tue, 10 Jan 2023 08:54:27 -0800 (PST) X-Google-Smtp-Source: AMrXdXtOD5VulxpJ1dom5n7DvVvpReilWNB94pQVusLV9KQnMuUo49ffF8zuW15oCkFEPu3cH9UC X-Received: by 2002:a05:622a:1b1e:b0:3a7:ef7b:6aac with SMTP id bb30-20020a05622a1b1e00b003a7ef7b6aacmr91220567qtb.11.1673369667140; Tue, 10 Jan 2023 08:54:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673369667; cv=none; d=google.com; s=arc-20160816; b=afxpBG7j1Ctsp7HP8FpOgFM2O7fEkXUqdYFJobRe6yjAPG3Tyqj7GqvNSegGSZe7tR 4T+28u/hnlWhwRzAenEopVxuSp+NSXIWSlwyd8wVSxW9iRxucbYGTdOF9JQcCXc9bVuo QnjD8Svqn/VQcdXH2yXHvVJ01sngutJ5zEmOTkHOKBmKdvLQ06Pl56VknjB98qtW+Lqt xUM8NGl/XawZzv8Gbbfz5xraAzb7ZW8L4k/EGXLJMqz9r0RBzlOxX49DAbNtobgHQIYK Iqwoeusi96qzMLxR2AHfNVxU/twNeZp0boiLglBCvC7MTkpqpa+c744rcxNFNLpuzNty zH3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mv6b5BVX+E5dEjhJ+rRg+doFrBJfje2G5RxYlkiYMSQ=; b=GkJ4izcMw4Ef8HaOLAUqIlvXGhGBcjYP3OnCiN/02B+d1MB094ZfzHy7hBsf3QPktq GazHKBfTvonFcGrAVSgfRgDCt6B0GHTkBSeccWoMpXoWv/ALM5A/CKXIQxSWlIucEiuV AC3F6PhjHL6wIOeFjeVIjSzkVWJWu8pNcRUWyz5uAZB0Xv/rWW5FnTvRTHOckdgpWVgW 1MJlu6pshtzFDb3hoQPdkc8d+z2jEpjisr9P3uI6Sp4rvqBbGmzc7sCkWH8OrZGXY0iJ 3JcGHFrWNc7jfrwy2mRfKNluegVPiIdoDaRA1zzkK5mr0EU9TpzuvaCLgGNGtK8L0bes jPNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EGwEFMa5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Include this file in order to avoid when refactoring headers: ../target/arm/cpregs.h:241:27: error: unknown type name 'CPUARMState' typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpregs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7e78c2c05c..63b645907e 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -21,6 +21,8 @@ #ifndef TARGET_ARM_CPREGS_H #define TARGET_ARM_CPREGS_H +#include "target/arm/cpu.h" + /* * ARMCPRegInfo type field bits: */ From patchwork Tue Jan 10 16:43:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640857 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2839517pvb; Tue, 10 Jan 2023 09:57:43 -0800 (PST) X-Google-Smtp-Source: AMrXdXt7co1aXVXG8IJE9JdkW4iKWP9cADGOMU0BhtNofSmXHRW3sVWZi7EnaPyJ3gob0dBy69Q8 X-Received: by 2002:ac8:554c:0:b0:3a5:25d4:2f2d with SMTP id o12-20020ac8554c000000b003a525d42f2dmr78749924qtr.65.1673373463193; Tue, 10 Jan 2023 09:57:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673373463; cv=none; d=google.com; s=arc-20160816; b=z56KNvMmjRK5CeRz/cjplKH237Ify4T6RFZ5dqJm0C0YBxk+bYrRmWGlrzIpCMx7/G DOr6KMM8Xrf4rv7x5/eTJGtY5dt42WgCx0fHmSpyE0uQxEmKpTK5pxR+S2ZMzqoU/Ubf DpfD2KSV4VjVcVCRh/p9+d29Wg60aK9z9roIPJpibi2NW/yamrhtLHQ6nxjjVQTGM4Gq 9WiB0n9LwauGBkIY4gWQQfF6O3YNuL9M3ByITWz+AtiD4TCx/ILYxXcGUQXEANgYvnoB HUBLVqLE6643BpgNGaK5kiKHstowDuNPTrOtXAuvjmPFAYGXMGbcu9VnS3Hp5FwG29T/ hZVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=djWjHp1PKVzuHPGY/PIVLhSBEcAmWoL71xzvCOJIpjc=; b=JRGs8tKD0e5m1z7jXIq1/go1g3kZcaskqtbKO9tS4R/sK0NuDe08rsxy5AiGLA+mGP 4wovmj7H4ZFQEsOKoYy7GFxYZsJ+X1h91edFur/gPUFcQ6wHOwzzctgZA0f+hlNK5NPd l65hlM4gjZXydCW83pZJiNs4Mr5PKDaQJjlm6+IM8uhf7Nh8HIWOhVAS3hO8G+lz6BeM /4/S/5jriAba+g4gcOWX7wzqOTQoNXzut+wFlZkqTkjt/rPm4R5XEdSUUpX1iio6D4zQ E+ltCrPIarcUZRA71aMW0niu0sHMGe+qzZWPbqoXXhHLob8i5nl9/CS/iVY0A7xw2QWv 4eaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TuKlboWP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use the full path to "cpu.h": "target/arm/cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/arm/digic.h | 2 +- include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h | 2 +- include/hw/arm/fsl-imx7.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h index 8f2735c284..646802806e 100644 --- a/include/hw/arm/digic.h +++ b/include/hw/arm/digic.h @@ -18,7 +18,7 @@ #ifndef HW_ARM_DIGIC_H #define HW_ARM_DIGIC_H -#include "cpu.h" +#include "target/arm/cpu.h" #include "hw/timer/digic-timer.h" #include "hw/char/digic-uart.h" #include "qom/object.h" diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 83291457cf..9d24d98189 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -33,7 +33,7 @@ #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" #include "exec/memory.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX6 "fsl-imx6" diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 7812e516a5..4f42fe4192 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -37,7 +37,7 @@ #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" #include "exec/memory.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX6UL "fsl-imx6ul" diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 4e5e071864..ed8c1ec813 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -38,7 +38,7 @@ #include "hw/net/imx_fec.h" #include "hw/pci-host/designware.h" #include "hw/usb/chipidea.h" -#include "cpu.h" +#include "target/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX7 "fsl-imx7" From patchwork Tue Jan 10 16:43:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640874 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2858616pvb; Tue, 10 Jan 2023 10:36:18 -0800 (PST) X-Google-Smtp-Source: AMrXdXsJ69yjYdSkVeOeb/VzyPysTiiODp7im7VK5lbcyXZpAoFUP40YYNg99ZYb10HMc96ZsUQy X-Received: by 2002:a67:fa89:0:b0:3b3:682d:83f4 with SMTP id f9-20020a67fa89000000b003b3682d83f4mr31054677vsq.5.1673375778196; Tue, 10 Jan 2023 10:36:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673375778; cv=none; d=google.com; s=arc-20160816; b=Q12FkG3ISCZWOR6ViiNFXdIytiDg2OoABW/2Dcl5uw0Bp8muFIXJHkNKrXlxIyb91T q1vmGFCQ8FxX6RA5MvzZbQEbThFXnWw6j2zWuxaZxLnefLg+sxHtYw5r4CvSFS6yYy8z 7aijxowKzyS8bghGdSyiTEGqXFeq8i6MupwjKmcAbCbfdGy7oHIdeGERqsGk0Y6D8cuM k7AfXmnI0NvgH5/CZuyOvP4hH7HdoCOCmBbuZh9lcycp5+HdifiZdW6SfUlM7CS0snBc 5RURHbfhFuuvhO1xdq7yS5e3F06EmOvoFvxrkbVLzqYd196q4WAMeRJB4Rz2gzs8zm94 ciSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KPo282/uew3iuzImHfNxHuSGZYMfkFiyRCBHN2R+reg=; b=A7/Tgm49fzEZQfb7FUW4Gizw8ebeSlpWUvxl/zh4BQ8wxym1lGXT9ikFYSL2Pmp/Cd j78eMvlio5jRbY6cLBaKzfweJTKtkK86Yj9JVFyTQ6/pDp473MdO1usVp+t/wwEt06fT /0abN5X+EFxX5OtUUBqh6s10jA1xxz7a9XAK3dXuPDbds0Sijw580tHpfSSY9hbe6Fhh 9rgGX+zqMNLI53nMyU/7TEBay8/KMlvilN5LHZkVQUlbrs+TpKlrRrtGFw4qIfZ/VlGE 5ngLfI4zZ9/b/NJogxxb7r7uhFZKgSIztEXN+MINAek78YBmPWZmhia73Q+68u2kS4uG UqWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qrhy6Iw7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Since this header depends on specific definitions such the word size (32 or 64-bit), for ARM such units must go to the per-target arm_ss[]. We want to expose few architectural definitions to hardware models. Start by exposing the ARM CPU QOM types to files under hw/ via the new "hw/arm/cpu.h" header. Doing so, less HW models will require access to "target/arm/cpu.h". Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/cpu.h | 28 ++++++++++++++++++++++++++++ target/arm/cpu-qom.h | 13 +------------ target/arm/cpu.h | 8 ++++---- 3 files changed, 33 insertions(+), 16 deletions(-) create mode 100644 include/hw/arm/cpu.h diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h new file mode 100644 index 0000000000..0c5d6ca2a8 --- /dev/null +++ b/include/hw/arm/cpu.h @@ -0,0 +1,28 @@ +/* + * ARM / Aarch64 CPU definitions + * + * This file contains architectural definitions consumed by hardware models + * implementations (files under hw/). + * Definitions not required to be exposed to hardware has to go in the + * architecture specific "target/arm/cpu.h" header. + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef HW_ARM_CPU_H +#define HW_ARM_CPU_H + +#include "hw/core/cpu.h" + +#define TYPE_ARM_CPU "arm-cpu" +OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) + +#define TYPE_AARCH64_CPU "aarch64-cpu" +typedef struct AArch64CPUClass AArch64CPUClass; +DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) + +#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) + +#endif diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 514c22ced9..b98904b6bc 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -21,16 +21,11 @@ #define QEMU_ARM_CPU_QOM_H #include "hw/core/cpu.h" +#include "hw/arm/cpu.h" #include "qom/object.h" struct arm_boot_info; -#define TYPE_ARM_CPU "arm-cpu" - -OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) - -#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU - typedef struct ARMCPUInfo { const char *name; void (*initfn)(Object *obj); @@ -57,12 +52,6 @@ struct ARMCPUClass { ResettablePhases parent_phases; }; - -#define TYPE_AARCH64_CPU "aarch64-cpu" -typedef struct AArch64CPUClass AArch64CPUClass; -DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, - TYPE_AARCH64_CPU) - struct AArch64CPUClass { /*< private >*/ ARMCPUClass parent_class; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bf2bce046d..52ac99cad3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -17,8 +17,8 @@ * License along with this library; if not, see . */ -#ifndef ARM_CPU_H -#define ARM_CPU_H +#ifndef TARGET_ARM_CPU_H +#define TARGET_ARM_CPU_H #include "kvm-consts.h" #include "qemu/cpu-float.h" @@ -26,6 +26,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#include "hw/arm/cpu.h" /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -2853,11 +2854,10 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU -#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU +#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU #define cpu_list arm_cpu_list From patchwork Tue Jan 10 16:43:54 2023 Content-Type: text/plain; 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Since this header depends on specific definitions such the word size (32 or 64-bit), for ARM such units must go to the per-target arm_ss[]. We want to expose few architectural definitions to hardware models. Expose the ARM architectural definitions used by hardware models, in order to reduce the inclusion of "target/arm/cpu.h". Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu-qom.h | 15 -------------- target/arm/cpu.h | 34 ------------------------------ 3 files changed, 49 insertions(+), 49 deletions(-) diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h index 0c5d6ca2a8..6758bffe34 100644 --- a/include/hw/arm/cpu.h +++ b/include/hw/arm/cpu.h @@ -25,4 +25,53 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +enum QemuPsciConduit { + QEMU_PSCI_CONDUIT_DISABLED = 0, + QEMU_PSCI_CONDUIT_SMC = 1, + QEMU_PSCI_CONDUIT_HVC = 2, +}; + +/* Meanings of the ARMCPU object's four inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 + +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; + +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + #endif diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b98904b6bc..d37037e214 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -68,19 +68,4 @@ void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); void arm_gt_hvtimer_cb(void *opaque); -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 52ac99cad3..ab6fdecf48 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -72,21 +72,6 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 -/* For M profile, some registers are banked secure vs non-secure; - * these are represented as a 2-element array where the first element - * is the non-secure copy and the second is the secure copy. - * When the CPU does not have implement the security extension then - * only the first element is used. - * This means that the copy for the current security state can be - * accessed via env->registerfield[env->v7m.secure] (whether the security - * extension is implemented or not). - */ -enum { - M_REG_NS = 0, - M_REG_S = 1, - M_REG_NUM_BANKS = 2, -}; - /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 @@ -107,12 +92,6 @@ enum { #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's four inbound GPIO lines */ -#define ARM_CPU_IRQ 0 -#define ARM_CPU_FIQ 1 -#define ARM_CPU_VIRQ 2 -#define ARM_CPU_VFIQ 3 - /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts @@ -160,13 +139,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define GTIMER_HYPVIRT 4 -#define NUM_GTIMERS 5 - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW @@ -3323,12 +3295,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); 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Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/collie.c | 1 - hw/arm/gumstix.c | 1 - hw/arm/meson.build | 8 ++++---- hw/arm/omap_sx1.c | 1 - hw/arm/z2.c | 1 - 5 files changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 9edff59370..a4576feff0 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -17,7 +17,6 @@ #include "hw/arm/boot.h" #include "hw/block/flash.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #define RAM_SIZE (512 * MiB) diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 2ca4140c9f..3f2bcaa24e 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -44,7 +44,6 @@ #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" -#include "cpu.h" #define CONNEX_FLASH_SIZE (16 * MiB) #define CONNEX_RAM_SIZE (64 * MiB) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 4babaa8dfc..7c71798661 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -13,16 +13,12 @@ arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) -arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) -arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) -arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) -arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) @@ -62,8 +58,12 @@ arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-e arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) +softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) +softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) +softmmu_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) +softmmu_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) hw_arch += {'arm': arm_ss} diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 1d156bc344..c7ddc90d02 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -35,7 +35,6 @@ #include "hw/block/flash.h" #include "sysemu/qtest.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qemu/cutils.h" /*****************************************************************************/ diff --git a/hw/arm/z2.c b/hw/arm/z2.c index dc25304290..610f3b5a0f 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -25,7 +25,6 @@ #include "hw/audio/wm8750.h" #include "audio/audio.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #ifdef DEBUG_Z2 From patchwork Tue Jan 10 16:43:56 2023 Content-Type: text/plain; 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Tue, 10 Jan 2023 08:44:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 08/18] hw/arm: Move units to softmmu[] by replacing "{target -> hw}/arm/cpu.h" Date: Tue, 10 Jan 2023 17:43:56 +0100 Message-Id: <20230110164406.94366-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230110164406.94366-1-philmd@linaro.org> References: <20230110164406.94366-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The following units only require the definitions exposed by "hw/arm/cpu.", not "target/arm/cpu.h": - highbank.c - integratorcp.c - mainstone.c - musicpal.c - palm.c - spitz.c - strongarm.c Once the "target/arm/cpu.h" replaced, we can move the units from meson's arm_ss[] to softmmu_ss[] to build them once. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/highbank.c | 2 +- hw/arm/integratorcp.c | 2 +- hw/arm/mainstone.c | 2 +- hw/arm/meson.build | 14 +++++++------- hw/arm/musicpal.c | 2 +- hw/arm/palm.c | 2 +- hw/arm/spitz.c | 2 +- hw/arm/strongarm.c | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index f12aacea6b..5aaf2876e9 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" +#include "hw/arm/cpu.h" #include "hw/loader.h" #include "net/net.h" #include "sysemu/runstate.h" @@ -35,7 +36,6 @@ #include "hw/cpu/a15mpcore.h" #include "qemu/log.h" #include "qom/object.h" -#include "cpu.h" #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index b109ece3ae..457db610dc 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -9,7 +9,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" +#include "hw/arm/cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/boards.h" diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 68329c4617..cb8ee05d0d 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -15,6 +15,7 @@ #include "qemu/units.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "hw/arm/cpu.h" #include "hw/arm/pxa.h" #include "hw/arm/boot.h" #include "net/net.h" @@ -23,7 +24,6 @@ #include "hw/block/flash.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" -#include "cpu.h" /* Device addresses */ #define MST_FPGA_PHYS 0x08000000 diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 7c71798661..f742107847 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -4,17 +4,11 @@ arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) -arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) -arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) -arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) -arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) -arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) -arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) @@ -29,7 +23,6 @@ arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) -arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) @@ -58,10 +51,17 @@ arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-e arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) +softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) +softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) +softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) +softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) +softmmu_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) +softmmu_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) +softmmu_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) softmmu_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) softmmu_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 73e2b7e4ce..07cd80bc13 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" +#include "hw/arm/cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 68e11dd1ec..6d637d7079 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -29,7 +29,7 @@ #include "hw/input/tsc2xxx.h" #include "hw/irq.h" #include "hw/loader.h" -#include "cpu.h" +#include "hw/arm/cpu.h" #include "qemu/cutils.h" #include "qom/object.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index f732fe0acf..4628b60792 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -33,7 +33,7 @@ #include "hw/adc/max111x.h" #include "migration/vmstate.h" #include "exec/address-spaces.h" -#include "cpu.h" +#include "hw/arm/cpu.h" #include "qom/object.h" enum spitz_model_e { spitz, akita, borzoi, terrier }; diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 39b8f01ac4..025bd38dc7 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -28,7 +28,7 @@ */ #include "qemu/osdep.h" -#include "cpu.h" +#include "hw/arm/cpu.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" From patchwork Tue Jan 10 16:43:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640846 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2804248pvb; Tue, 10 Jan 2023 08:47:58 -0800 (PST) X-Google-Smtp-Source: AMrXdXsg1nuhLwKnsrpr/QNOqJxvq4QZohlYz53whgKyctzQraEUPNW0x9LYlQMZXwymIyl4vKxK X-Received: by 2002:a67:c919:0:b0:3d0:c4f8:d437 with SMTP id w25-20020a67c919000000b003d0c4f8d437mr1572668vsk.30.1673369277764; Tue, 10 Jan 2023 08:47:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673369277; cv=none; d=google.com; s=arc-20160816; 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[209.51.188.17]) by mx.google.com with ESMTP id bj3-20020a05620a190300b006faa9dcae3bsi7040088qkb.11.2023.01.10.08.47.57 for ; Tue, 10 Jan 2023 08:47:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G1yQhukD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFHkY-0004Dj-H3; Tue, 10 Jan 2023 11:45:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFHkH-000486-FH for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:45:11 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFHkF-0006FC-8x for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:45:05 -0500 Received: by mail-wr1-x432.google.com with SMTP id v2so1426711wrw.10 for ; Tue, 10 Jan 2023 08:45:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z+m8L9ejC6qlw4tOENu9F3qOBbscmRJfWRVLTYz7u+s=; b=G1yQhukDyIZYsrGkdRZQifpF9SUe82x8HpGVCgxxC+ASBvF3AWC5fphfWGs6UZwvJU fLKm3wKqZ5Whd8ZG6Gj0uGg8wjg2JznC4rfyphJc1wm7FuBjVRHGm8+i4V4tfb5xsDhI GleHthtwu1Xcg4Y97HxGg2noxeXowlO4d4FMpC3xnrvXQ2cZXbq6Jriv5/E7ueQGJtPW JZanF8pQGweYyXbbZTUjEhaMvwuQur/sWAyY+JL4YQiGOwCsh+Vr42HMju9CSX8b72P7 RmG/BxEEpvGwLQvKEMEnVRnvtYAhLaANArcdgWhwNAvx8ntMEgsaUwq7H9vbTobxwNGb ObJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z+m8L9ejC6qlw4tOENu9F3qOBbscmRJfWRVLTYz7u+s=; b=258DDmnGTeVW1X1/bzEhTzwK6smri/QxXA0VGGKFzLW7dAM5yLOCZoR2I0B4n6Xrnw /1knnpe5B+K/sYuuNOrn4Z9aibqZqzmqR6A3k/hU44DxXpCReWQYx2oKlDfJDTD5vOTf JpvpldygmLPXG9Lc/g0pfX9fsrM/U9iIFVpoj8OeTEnokVsezbdKM/RBWAdTD0dzwv4H SY606U3idOjuak3ZGIa+Ji+eZjwE7au3aZtwk2xtWm84PiN7tSVgxREXev0QkKAJYrNP +VN0M3K0+YwOH523HymSH7FsZ8T/G2c8Igm6lU/7zQKhbIHTAe+fa/qmrF77m16LwyKZ IiHA== X-Gm-Message-State: AFqh2krXyjFvmMmn8vN6zb2tf3aVDe0GVXbR4zTwjm6W+vHMHD8caKrn PjwXqG/Ksidh0WLB+YOSfllIEvanpr5E0aRZ X-Received: by 2002:a05:6000:12c6:b0:2bc:6f72:93cf with SMTP id l6-20020a05600012c600b002bc6f7293cfmr4784588wrx.64.1673369099664; Tue, 10 Jan 2023 08:44:59 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id n6-20020adfe786000000b002bdbde1d3absm1333824wrm.78.2023.01.10.08.44.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jan 2023 08:44:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 09/18] hw/arm/armv7m: Remove 'target/arm/cpu.h' from NVIC header Date: Tue, 10 Jan 2023 17:43:57 +0100 Message-Id: <20230110164406.94366-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230110164406.94366-1-philmd@linaro.org> References: <20230110164406.94366-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "hw/intc/armv7m_nvic.h" only requires the HW definitions exposed by the "hw/arm/cpu.h" header. Move the "target/arm/cpu.h" header inclusion to armv7m.c which is the single unit requiring it. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 2 ++ include/hw/intc/armv7m_nvic.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 50a9507c0b..1e9ed1e7af 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -8,6 +8,7 @@ */ #include "qemu/osdep.h" +#include "hw/arm/cpu.h" #include "hw/arm/armv7m.h" #include "qapi/error.h" #include "hw/sysbus.h" @@ -20,6 +21,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/log.h" +#include "target/arm/cpu.h" #include "target/arm/idau.h" #include "migration/vmstate.h" diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 0180c7b0ca..c0c514af63 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -10,7 +10,7 @@ #ifndef HW_ARM_ARMV7M_NVIC_H #define HW_ARM_ARMV7M_NVIC_H -#include "target/arm/cpu.h" +#include "hw/arm/cpu.h" #include "hw/sysbus.h" #include "hw/timer/armv7m_systick.h" #include "qom/object.h" From patchwork Tue Jan 10 16:43:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640858 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2839625pvb; Tue, 10 Jan 2023 09:58:00 -0800 (PST) X-Google-Smtp-Source: AMrXdXuveyNQ/BYp4cvgY72VKWS0TGvZ1PLBc8krid7sZHWDtle28s0ZEPa8fPjvLv/Di3gzXdhF X-Received: by 2002:ac8:7ed8:0:b0:3a7:ed21:ac47 with SMTP id x24-20020ac87ed8000000b003a7ed21ac47mr95142464qtj.18.1673373480489; Tue, 10 Jan 2023 09:58:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673373480; cv=none; d=google.com; s=arc-20160816; b=DPRhCJII8czo91nALWjbgfvrdRmIkgM+QqZJQ1IkqMLCDj2LcVYUpkvvQ7pWGk1V3D GrJJltscC/QSGdHqclDlKiE6HaU7XqItKDQ/tqqV0brItj1f5GqWCzxJpNF+YJsfcod3 /hE4/zcEIYZ6Ugp84Z3ghRRN4GeZ5S4oK0JF/AENxwSAFkOIrHCuC9+sS1uk/NZcSycX bkUIVZ21yIEZ19pRwAHi7UA1ofMc3rJ7OdvuixZPdft3IVqUkomggUPQfjavi3kNMAB8 ASYztN/uo9eFL/Lnym2FSGTP9U9kvrtXD0cUQjlV3vvyqHk7o44oKq5hta5RdOMvJJGo SkBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Fiw9Fg+p/b/j5dB2Y7ot3w6ih2sYibESUE4ugSZG2HU=; b=j1xC317bOco0hfpI8L4toQjPWR9X2HG1Ug8qFdNmI9q6DUCjfwKyYKDim5glMQMW0Z ZCHt+AxGjrjMs1HYq4o2WV5o9sRwALmA3pssa87dDkPJs24xrrErtf7MIKNxttrnBHBm 640mf8VWmsndK0rlXvYj8c9Ce9i0mpgRMl6IEfuVNYiF6HpjDM3JSg4ON+mqBpneptWo WcV8KVqCJib61fBtJENavUEy2xtbxLBgoACgM1ixP6+4TyDtbIBtVM/dxajewWRBR0IB n6X+FOLXAfl59cq3v0p+eOOPnPVORhprIN4vDHefPXxo7T1jDpiJ/VQmfagbstAUVW2V CPHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lvZKso0O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 10 Jan 2023 08:45:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 10/18] hw/arm: Move various armv7m-related units to softmmu_ss[] Date: Tue, 10 Jan 2023 17:43:58 +0100 Message-Id: <20230110164406.94366-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230110164406.94366-1-philmd@linaro.org> References: <20230110164406.94366-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the previous commit we remove the indirect dependency on "target/arm/cpu.h" from all these ARMv7-M units: - armsse.c - msf2-som.c - microbit.c - mps2-tz.c - mps2.c - msf2-soc.c - musca.c - netduino2.c - netduinoplus2.c - nrf51_soc.c - stellaris.c - stm32f100_soc.c - stm32f205_soc.c - stm32f405_soc.c - stm32vldiscovery.c We can now move them to meson's softmmu_ss[] source set to buid them once. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/meson.build | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f742107847..f7e1d4add6 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -3,7 +3,6 @@ arm_ss.add(files('boot.c'), fdt) arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) -arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) @@ -11,8 +10,6 @@ arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) -arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) -arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) @@ -26,9 +23,6 @@ arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) -arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) -arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) @@ -40,27 +34,36 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2600.c', 'aspeed_ast10x0.c', 'fby35.c')) -arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) -arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) -arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) -arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) -arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) -arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) +softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) +softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) +softmmu_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) +softmmu_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) +softmmu_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) +softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) +softmmu_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) softmmu_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) +softmmu_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) +softmmu_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) +softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) softmmu_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) +softmmu_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) +softmmu_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) +softmmu_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) +softmmu_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) +softmmu_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) softmmu_ss.add(when: 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Remove the 'target_long' type which size changes per target. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/digic_boards.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 4093af09cb..529d44e4e7 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -80,7 +80,7 @@ static void digic4_board_init(MachineState *machine, DigicBoard *board) static void digic_load_rom(DigicState *s, hwaddr addr, hwaddr max_size, const char *filename) { - target_long rom_size; + ssize_t rom_size; if (qtest_enabled()) { /* qtest runs no code so don't attempt a ROM load which From patchwork Tue Jan 10 16:44:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640878 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2864859pvb; Tue, 10 Jan 2023 10:50:50 -0800 (PST) X-Google-Smtp-Source: AMrXdXsam6BWXgc+jSTzgls6mvi0w28ntUYmUZHAY07lao+RlN+P3KSFS7MXOKAhJLwNVaheM3PR X-Received: by 2002:a05:622a:1c06:b0:39c:da20:f7af with SMTP id bq6-20020a05622a1c0600b0039cda20f7afmr92236928qtb.12.1673376649132; Tue, 10 Jan 2023 10:50:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673376649; cv=none; d=google.com; s=arc-20160816; b=iMLI2skGVKFGcfE0NpABKDXyDATxsfZDm/wXqzOhBE8kDVP1+w5TagLxrphRSLXrGW wASfJ/nl4HCo0g20OvLmdPa3hf9+62VxsjhgueLxFFjCgLR/0MJUlPVX3l4SiMpXlNYk TT/X67MpJ8KxEnxcB8hn9LZwM9Rx9nEXf3CN0Y7nzw/sycJPo8t2bH6o0aItL4xoZfL8 AAMLTIT4QGc3sFtnco3hEuR0YxvFxq0VnDlwKkJ289iAk9UMqtLzF66bwf3LL10MHOia YYuZ3+kO1v85hRrr9DUTvXCwEmuPbmFmbel9UmeqQK3GJ5pTTRB6qX1azgEq+aUWE0nd EgdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=K3l0Ynfg0AmbqqJf0HR+g3W0vw/8lhngqGaDSaJXNM0=; b=yCy4X/dHDDOztZtQ5/wa/s8apOjg3CuQb7Eu6KUCGeNIYdQS+6l/P+RUB5YliYTtrh Lxa6Hf8XrLvJHTtCaDSoghakfJafgyZBM/kMaff8VnN07E2IRkDMuM+EBkQMjsqnmgHH oc2v+k4Z3mmUgh0+jEXNXGusR0+H/IFhKWD2GYMOmVHb5c0h9QJXA5Bqbjg9kEric3Bu d43QwIOhqz6NM6+H6QOkN03Vow1ovfOFfo9nzIhGkdhR7Znc14KtE7OgTuEC/Bnonw6l TA/jTdFcDQi01cBR43C8aCwAgvATJvBjF0Zl6Aqu/Ycqg8AoU8DvBCrHCLfwRqqi1jCh z0nA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qAHQ6YqD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f4-20020a05622a114400b003a51d524221si7227021qty.300.2023.01.10.10.50.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Jan 2023 10:50:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qAHQ6YqD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFHkv-0004ZZ-Is; Tue, 10 Jan 2023 11:45:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFHkY-0004FR-FT for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:45:22 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFHkV-0006TC-FO for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:45:22 -0500 Received: by mail-wr1-x436.google.com with SMTP id e3so3214544wru.13 for ; Tue, 10 Jan 2023 08:45:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K3l0Ynfg0AmbqqJf0HR+g3W0vw/8lhngqGaDSaJXNM0=; b=qAHQ6YqDzVjo6VtREvLTuK2lE4b/rDxmTZFAYzRJWGjZYTFRPhlmDtijmGvdWAR3lu zmRJkbiBE8CLjnsL86+gcVzA89BS5jLqowasItgajTLo8fgMOQHYodAEzddZhY+2hEDq m36H0aPSPMSJw9BXCLRMFMsTMfVSuCc2o4G1uKTL1rIKobUxXg1wNzyu2XHC0P69ip+h 2B+Dgt0lMWG+G87bCsHdBQdf+E4qDTjKGDi2HQJzZIRPsLzeCSjw04dauAECwDNyBekk yEsGpVWNamUoBgRZHJbgZqpOrBcm5ywXC7N6KzS6pMgzGtDQ8Qcuoxww1BK+Il3W5rc0 y31Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K3l0Ynfg0AmbqqJf0HR+g3W0vw/8lhngqGaDSaJXNM0=; b=WVgk2Xm9UlQpUEcSC282oDRBcpfqDOYoEDweFFtsMUKx8QT1VaQ2Hb8VKi/G9G06xN iSbCsLr2yoFgvUWgC+snhzYgRdChshqXvcguByViWAWtvHr3etrypTe9Csi7C1oZaqx4 Sv+ueki9MzCw44qH8ci3+JURD1DPAUZwg0Oo1XPW9qNBwoBdfpONox2VLsU85l/ew+gl dt0UPg5RlXanlTUnUVZmsKtsUMafm5SP9wmH3pXVfOGb2mr23zzoXVnGYfKZ5MUyRnhN pkJQWAa+fd9U+IlzlX0YuXhUGzWcZd1MskAQjFu9rTcQ1f++M/+/ednbraARwRi4tewZ Jx4g== X-Gm-Message-State: AFqh2ko25p27B+02U6wKXY2Xo2ZUPevOSfDBPaYYVgR9BYK1z/2wrvAL pyPcuIscHKYpk2n8BQ7Qtd5/xU1bUrvcq2Gb X-Received: by 2002:a05:6000:1f14:b0:242:5a34:fb7b with SMTP id bv20-20020a0560001f1400b002425a34fb7bmr44629557wrb.70.1673369116060; Tue, 10 Jan 2023 08:45:16 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id e35-20020a5d5963000000b00276d8c2332fsm13010729wri.108.2023.01.10.08.45.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jan 2023 08:45:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 12/18] hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU) Date: Tue, 10 Jan 2023 17:44:00 +0100 Message-Id: <20230110164406.94366-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230110164406.94366-1-philmd@linaro.org> References: <20230110164406.94366-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the ARMCPU field in DigicState by a reference to an allocated ARMCPU. Instead of initializing the field with object_initialize(), allocate it with object_new(). As we don't access ARMCPU internal fields or size, we can move digic.c from arm_ss[] to the more generic softmmu_ss[]. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/digic.c | 7 ++++--- hw/arm/meson.build | 7 ++----- include/hw/arm/digic.h | 4 ++-- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 6df5547977..fe24b91db6 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -36,7 +36,8 @@ static void digic_init(Object *obj) DigicState *s = DIGIC(obj); int i; - object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946")); + s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("arm946"))); + object_property_add_child(obj, "cpu", OBJECT(s->cpu)); for (i = 0; i < DIGIC4_NB_TIMERS; i++) { g_autofree char *name = g_strdup_printf("timer[%d]", i); @@ -52,12 +53,12 @@ static void digic_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd; int i; - if (!object_property_set_bool(OBJECT(&s->cpu), "reset-hivecs", true, + if (!object_property_set_bool(OBJECT(s->cpu), "reset-hivecs", true, errp)) { return; } - if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { return; } diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f7e1d4add6..0c7554b763 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -2,10 +2,6 @@ arm_ss = ss.source_set() arm_ss.add(files('boot.c'), fdt) arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) -arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) -arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) -arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) @@ -18,7 +14,6 @@ arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c')) -arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) @@ -42,6 +37,8 @@ softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) softmmu_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) +softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) +softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h index 646802806e..1bfd6788c9 100644 --- a/include/hw/arm/digic.h +++ b/include/hw/arm/digic.h @@ -18,7 +18,7 @@ #ifndef HW_ARM_DIGIC_H #define HW_ARM_DIGIC_H -#include "target/arm/cpu.h" +#include "hw/arm/cpu.h" #include "hw/timer/digic-timer.h" #include "hw/char/digic-uart.h" #include "qom/object.h" @@ -34,7 +34,7 @@ struct DigicState { DeviceState parent_obj; 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Fixes: 757282ada8 ("i.MX: Add i.MX7 SOC.") Fixes: 31cbf933f0 ("i.MX: Add i.MX6UL SOC") Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/fsl-imx6ul.c | 4 ++-- hw/arm/fsl-imx7.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index d88d6cc1c5..568317117c 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -72,7 +72,7 @@ static void fsl_imx6ul_init(Object *obj) * GPIOs 1 to 5 */ for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { - snprintf(name, NAME_SIZE, "gpio%d", i); + snprintf(name, NAME_SIZE, "gpio%d", i + 1); object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); } @@ -80,7 +80,7 @@ static void fsl_imx6ul_init(Object *obj) * GPT 1, 2 */ for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { - snprintf(name, NAME_SIZE, "gpt%d", i); + snprintf(name, NAME_SIZE, "gpt%d", i + 1); object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT); } diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index afc7480799..6115677d43 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -52,7 +52,7 @@ static void fsl_imx7_init(Object *obj) * GPIOs 1 to 7 */ for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { - snprintf(name, NAME_SIZE, "gpio%d", i); + snprintf(name, NAME_SIZE, "gpio%d", i + 1); object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); } @@ -60,7 +60,7 @@ static void fsl_imx7_init(Object *obj) * GPT1, 2, 3, 4 */ for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { - snprintf(name, NAME_SIZE, "gpt%d", i); + snprintf(name, NAME_SIZE, "gpt%d", i + 1); object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT); } From patchwork Tue Jan 10 16:44:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640880 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2868467pvb; Tue, 10 Jan 2023 10:59:40 -0800 (PST) X-Google-Smtp-Source: AMrXdXunfpPEcXBBp8cMQpvEL8vSWJ9quBrVisz4oBBKgGg1W+J/R+eknnx6Ry6T3mEnDlkOIo8T X-Received: by 2002:ac8:43d2:0:b0:3a8:137e:2963 with SMTP id w18-20020ac843d2000000b003a8137e2963mr5525813qtn.20.1673377180173; Tue, 10 Jan 2023 10:59:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673377180; cv=none; d=google.com; s=arc-20160816; b=FkdF1xNEI06QWDK+blhfZ51YL4Hdqp4tzTppVZmzgvnPY2QfOCrvQmByLeLDf/LZ08 T7itkG8YZm0eOFsK5jTnSApu1AJONA1Jzjs46cZdQIlAm+4u0Uf12B5wQW8CIduu55A3 NEz0+QwUpOqH8u30LhWKDmoC26jTi/VSUtyx8+nW7rIDlCbtO1W7/MF3U8K+H3s3Jwa5 9HMpiJyW4nhiQm1n1f7zyKcoy7a9SdbuD/QZIvJwJAqLiP3MIouPoMMZDf4nn9cWK71I QfndRveJ4ChlxBmei7xaWSFfH02pUq/BC2o871Jbnsp/yXXwOqQzOVExU/95q0ZqYAHR Av8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Jw5bJZJ8xtvZB9vBJ7QEumcG+hXUdxVdMxAlu6Wbtrc=; b=qLfDHfovAlgVkitgWu2eGcvTm2SuiDwZIDjOo4WHadeNNlU2gND13XZEE9X0s7jXjK 9TRiFvnxnaWizVGYU8vothN+YsXiX2/IvgIoRTEEDQAIuiJffHRG9twBPhgrgT96YcCp ppGhcfhoyPSXoysWTQI6FP8vIZLoOwzNls3uc8Oh8og0KxarAXy8xdESfMWtXRARg6Xu NCEbGIiZML5s4rzodzuWzAv10NmnrOJOFuv1HSl5GX8kFMlzEd0LEXhlbWhqN+Vl+Czc J46deGDl2fEkWAbK0O0NGeJ4jpSpA9w3l5QyEfGNlUrGEM+2FZ7WnPAlZcpu8pMhMngi S1lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hl8jOjdb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Instead of initializing the field with object_initialize(), allocate it with object_new(). As we don't access ARMCPU internal fields or size, we can move from arm_ss[] to the more generic softmmu_ss[] the followin units: - fsl-imx25.c - imx25_pdk.c Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/fsl-imx25.c | 9 +++++---- hw/arm/imx25_pdk.c | 2 +- hw/arm/meson.build | 2 +- include/hw/arm/fsl-imx25.h | 4 ++-- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 24c4374590..5213c1ac23 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -36,7 +36,8 @@ static void fsl_imx25_init(Object *obj) FslIMX25State *s = FSL_IMX25(obj); int i; - object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926")); + s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("arm926"))); + object_property_add_child(obj, "cpu", OBJECT(s->cpu)); object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC); @@ -83,7 +84,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) uint8_t i; Error *err = NULL; - if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { return; } @@ -92,9 +93,9 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { return; diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index b4f7f4e8a7..26fc0ef5ae 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -136,7 +136,7 @@ static void imx25_pdk_init(MachineState *machine) * fail. */ if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu, machine, &imx25_pdk_binfo); + arm_load_kernel(s->soc.cpu, machine, &imx25_pdk_binfo); } } diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 0c7554b763..ccda1f5149 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -20,7 +20,6 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orange arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( @@ -41,6 +40,7 @@ softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) +softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 1b1086e945..9ad95073c2 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -31,7 +31,7 @@ #include "hw/usb/chipidea.h" #include "hw/watchdog/wdt_imx2.h" #include "exec/memory.h" -#include "target/arm/cpu.h" +#include "hw/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX25 "fsl-imx25" @@ -50,7 +50,7 @@ struct FslIMX25State { DeviceState parent_obj; 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Instead of initializing the field with object_initialize(), allocate it with object_new(). As we don't access ARMCPU internal fields or size, we can move from arm_ss[] to the more generic softmmu_ss[] the followin units: - fsl-imx31.c - kzm.c Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/fsl-imx31.c | 9 +++++---- hw/arm/kzm.c | 2 +- hw/arm/meson.build | 2 +- include/hw/arm/fsl-imx31.h | 4 ++-- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index def27bb913..26c6bb67f0 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -32,7 +32,8 @@ static void fsl_imx31_init(Object *obj) FslIMX31State *s = FSL_IMX31(obj); int i; - object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm1136")); + s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("arm1136"))); + object_property_add_child(obj, "cpu", OBJECT(s->cpu)); object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC); @@ -65,7 +66,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) uint16_t i; Error *err = NULL; - if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { return; } @@ -74,9 +75,9 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { return; diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index b1b281c9ac..8c6cdb06f5 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -126,7 +126,7 @@ static void kzm_init(MachineState *machine) kzm_binfo.ram_size = machine->ram_size; if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu, machine, &kzm_binfo); + arm_load_kernel(s->soc.cpu, machine, &kzm_binfo); } } diff --git a/hw/arm/meson.build b/hw/arm/meson.build index ccda1f5149..b244db5962 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -20,7 +20,6 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orange arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_soc.c', @@ -41,6 +40,7 @@ softmmu_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) +softmmu_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index c116a73e0b..c117136901 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -27,7 +27,7 @@ #include "hw/gpio/imx_gpio.h" #include "hw/watchdog/wdt_imx2.h" #include "exec/memory.h" -#include "target/arm/cpu.h" +#include "hw/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX31 "fsl-imx31" @@ -43,7 +43,7 @@ struct FslIMX31State { DeviceState parent_obj; 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Instead of initializing the field with object_initialize(), allocate it with object_new(). As we don't access ARMCPU internal fields or size, we can move from arm_ss[] to the more generic softmmu_ss[] the followin units: - fsl-imx7.c - mcimx7d-sabre.c Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/fsl-imx7.c | 6 +++--- hw/arm/mcimx7d-sabre.c | 2 +- hw/arm/meson.build | 2 +- include/hw/arm/fsl-imx7.h | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 6115677d43..634ed299cc 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -38,8 +38,8 @@ static void fsl_imx7_init(Object *obj) for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { snprintf(name, NAME_SIZE, "cpu%d", i); - object_initialize_child(obj, name, &s->cpu[i], - ARM_CPU_TYPE_NAME("cortex-a7")); + s->cpu[i] = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a7"))); + object_property_add_child(obj, name, OBJECT(s->cpu[i])); } /* @@ -157,7 +157,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) } for (i = 0; i < smp_cpus; i++) { - o = OBJECT(&s->cpu[i]); + o = OBJECT(s->cpu[i]); /* On uniprocessor, the CBAR is set to 0 */ if (smp_cpus > 1) { diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 6182b15f19..ad46bf79c6 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -61,7 +61,7 @@ static void mcimx7d_sabre_init(MachineState *machine) } if (!qtest_enabled()) { - arm_load_kernel(&s->cpu[0], machine, &boot_info); + arm_load_kernel(s->cpu[0], machine, &boot_info); } } diff --git a/hw/arm/meson.build b/hw/arm/meson.build index b244db5962..53ce301cbe 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,7 +27,6 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2600.c', 'aspeed_ast10x0.c', 'fby35.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) @@ -41,6 +40,7 @@ softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) softmmu_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) +softmmu_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) softmmu_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index ed8c1ec813..97c9731db3 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -38,7 +38,7 @@ #include "hw/net/imx_fec.h" #include "hw/pci-host/designware.h" #include "hw/usb/chipidea.h" -#include "target/arm/cpu.h" +#include "hw/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX7 "fsl-imx7" @@ -65,7 +65,7 @@ struct FslIMX7State { DeviceState parent_obj; /*< public >*/ - ARMCPU cpu[FSL_IMX7_NUM_CPUS]; + ARMCPU *cpu[FSL_IMX7_NUM_CPUS]; A15MPPrivState a7mpcore; IMXGPTState gpt[FSL_IMX7_NUM_GPTS]; IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS]; From patchwork Tue Jan 10 16:44:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640867 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2852142pvb; Tue, 10 Jan 2023 10:21:30 -0800 (PST) X-Google-Smtp-Source: AMrXdXuDl5SFty1UlLvSHGNYR9vVwLxX3kbwqRLjBo5L368rLNLBj/c+PE+chxlRRs4Pf8svonl8 X-Received: by 2002:ac8:1249:0:b0:3a8:270:c0b8 with SMTP id g9-20020ac81249000000b003a80270c0b8mr4773550qtj.15.1673374890511; Tue, 10 Jan 2023 10:21:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673374890; cv=none; d=google.com; s=arc-20160816; b=E9MUMsh/CUfHwHFdSDBjQXTVqha52a+OW0mdtuBywLP5zMN4cK93EsGsTN0ENGvwat znvx7HISXQ2w8JLXMF0q15cYT5TIUnKCRyAMyEtDuLYRDZ+f10GW3DYEdz7x41EdJARr 3TXuueoZKMu0dxEpytWj6+ziRcfKoe2C+lUcjwNyveRs8aMDVMLEHh9cDxf53Kg2EDqu A1Fg2byo5U7E5Pv+Wk1Z2lpTICsgmFe572ydYcx+1yjMpk/2Rq7D/wpZ3zzryRL4K2/x xBxf/rApLeuRvf/ZXKV+WlMbmTlugGkeeUoHXzCCpZ2Sj7Nvhm64EtqWXxC7pmZpAL5U l7cw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id ef5-20020a05620a808500b00705b1d5b036si4200770qkb.641.2023.01.10.10.21.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Jan 2023 10:21:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XFoA25AF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFHl1-0004dk-Re; Tue, 10 Jan 2023 11:45:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFHkw-0004am-Qe for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:45:46 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFHku-0006Rp-I1 for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:45:46 -0500 Received: by mail-wr1-x42b.google.com with SMTP id z5so11374621wrt.6 for ; Tue, 10 Jan 2023 08:45:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KlIENfxWIvMy7wAsOeIIVwXs5j0fqcu2I9CG7fH4FsA=; b=XFoA25AFQNh3XcyQ5WsxQthXlIJZSkkHXnUhiCizmCZitac3oUgajjdv3doVfLbaQl iu9FnmlYQulIvoxere8d3r3kDw4sOl5y3B4xdeZOTbLD2Bdd18OAYNBW/zMkKJbaSVAN QALwi0iLaVhrsf/rjwZimt/1n2qVG51Zt2S4IL8c+N896jS5pUvv/8JV5qNGV7v5xiX/ /AKszZ3sCbT3kDmkJM+dn40lNnG5zSkB4CWjWWcYVrhibeTQuOp0KCtVNjgvTjBCdrRr JpCsB/Kw9IZzAphlXPdW35k/DmlNnU1Fy9sYzIPDXdkmZQhxv0Drmp79PeA6WtL+R/OF 9FoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KlIENfxWIvMy7wAsOeIIVwXs5j0fqcu2I9CG7fH4FsA=; b=mT0MmrcOLLXGp4QSeDA4UPGKevVZk2UuoPMDOCJLM0rxZ/m/7E+UIcdV1aJeh4zQWy hWG4EQnhDitXZrVcT9JZrH4bvYIWhfkVSe9VQXaCqpDdVKyzhtKZewxzxfsth3ChHDFR aUEUP5LhwVcCaFCkyxZ/+zm8evw9GyP9XQo2NrRb44eX7SCL4y8kkEb1UGJ4gZP54knt 05ojOzLn+B+7JF06ErA89jGpj8/1bzrX5lbzcqTZyxOYKBpcpJYOq7vNpHIW71uykLCO cagS/OB718wROhgaKZc4p1lxfp7ZwKnUxrRv9OVS8CvJcK1ctXo3XQ9NLOXQTk71KLQ9 9ztw== X-Gm-Message-State: AFqh2kozZgUP4N1/zNCC9RBdogTbfbc18u+fEF5XKbW9SGLMKMOvomas pQ8MEXL0u53vHBUF6fJOrJV17jN8hZXuEHjI X-Received: by 2002:a5d:4150:0:b0:286:2b9e:f549 with SMTP id c16-20020a5d4150000000b002862b9ef549mr29669219wrq.66.1673369143506; Tue, 10 Jan 2023 08:45:43 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id w10-20020a5d608a000000b0027cfd9463d7sm11722252wrt.110.2023.01.10.08.45.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jan 2023 08:45:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 17/18] hw/arm/fsl-imx6: Replace object_initialize(ARMCPU) by object_new() Date: Tue, 10 Jan 2023 17:44:05 +0100 Message-Id: <20230110164406.94366-18-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230110164406.94366-1-philmd@linaro.org> References: <20230110164406.94366-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the ARMCPU field in FslIMX6[UL]State by a reference to an allocated ARMCPU. Instead of initializing the field with object_initialize(), allocate it with object_new(). As we don't access ARMCPU internal fields or size, we can move from arm_ss[] to the more generic softmmu_ss[] the followin units: - fsl-imx6.c - fsl-imx6ul.c - mcimx6ul-evk.c - sabrelite.c Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/fsl-imx6.c | 14 +++++++------- hw/arm/fsl-imx6ul.c | 8 ++++---- hw/arm/mcimx6ul-evk.c | 2 +- hw/arm/meson.build | 6 +++--- hw/arm/sabrelite.c | 2 +- include/hw/arm/fsl-imx6.h | 4 ++-- include/hw/arm/fsl-imx6ul.h | 4 ++-- 7 files changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 00dafe3f62..085cd3b1c8 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -43,8 +43,8 @@ static void fsl_imx6_init(Object *obj) for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { snprintf(name, NAME_SIZE, "cpu%d", i); - object_initialize_child(obj, name, &s->cpu[i], - ARM_CPU_TYPE_NAME("cortex-a9")); + s->cpu[i] = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a9"))); + object_property_add_child(obj, name, OBJECT(s->cpu[i])); } object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); @@ -120,17 +120,17 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) /* On uniprocessor, the CBAR is set to 0 */ if (smp_cpus > 1) { - object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", + object_property_set_int(OBJECT(s->cpu[i]), "reset-cbar", FSL_IMX6_A9MPCORE_ADDR, &error_abort); } /* All CPU but CPU 0 start in power off mode */ if (i) { - object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", + object_property_set_bool(OBJECT(s->cpu[i]), "start-powered-off", true, &error_abort); } - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu[i]), NULL, errp)) { return; } } @@ -148,9 +148,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) for (i = 0; i < smp_cpus; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_FIQ)); } if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 568317117c..be0573a243 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -34,8 +34,8 @@ static void fsl_imx6ul_init(Object *obj) char name[NAME_SIZE]; int i; - object_initialize_child(obj, "cpu0", &s->cpu, - ARM_CPU_TYPE_NAME("cortex-a7")); + s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a7"))); + object_property_add_child(obj, "cpu0", OBJECT(s->cpu)); /* * A7MPCORE @@ -166,7 +166,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) return; } - qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); + qdev_realize(DEVICE(s->cpu), NULL, &error_abort); /* * A7MPCORE @@ -178,7 +178,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); sbd = SYS_BUS_DEVICE(&s->a7mpcore); - d = DEVICE(&s->cpu); + d = DEVICE(s->cpu); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index d83c3c380e..89a65e4c4b 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -61,7 +61,7 @@ static void mcimx6ul_evk_init(MachineState *machine) } if (!qtest_enabled()) { - arm_load_kernel(&s->cpu, machine, &boot_info); + arm_load_kernel(s->cpu, machine, &boot_info); } } diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 53ce301cbe..a7ee21e32f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -9,7 +9,6 @@ arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) -arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) @@ -20,7 +19,6 @@ arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orange arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_soc.c', 'aspeed.c', @@ -28,7 +26,6 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast10x0.c', 'fby35.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) @@ -40,6 +37,8 @@ softmmu_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) softmmu_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c')) softmmu_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c')) +softmmu_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) +softmmu_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) softmmu_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) softmmu_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) softmmu_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) @@ -55,6 +54,7 @@ softmmu_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) softmmu_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) +softmmu_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) softmmu_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) softmmu_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) softmmu_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 41191245b8..acd1d344b9 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -98,7 +98,7 @@ static void sabrelite_init(MachineState *machine) sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary; if (!qtest_enabled()) { - arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo); + arm_load_kernel(s->cpu[0], machine, &sabrelite_binfo); } } diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 9d24d98189..ba42047b21 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -32,8 +32,8 @@ #include "hw/net/imx_fec.h" #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" +#include "hw/arm/cpu.h" #include "exec/memory.h" -#include "target/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX6 "fsl-imx6" @@ -55,7 +55,7 @@ struct FslIMX6State { DeviceState parent_obj; /*< public >*/ - ARMCPU cpu[FSL_IMX6_NUM_CPUS]; + ARMCPU *cpu[FSL_IMX6_NUM_CPUS]; A9MPPrivState a9mpcore; IMX6CCMState ccm; IMX6SRCState src; diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 4f42fe4192..f49d0c9b83 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -37,7 +37,7 @@ #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" #include "exec/memory.h" -#include "target/arm/cpu.h" +#include "hw/arm/cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX6UL "fsl-imx6ul" @@ -66,7 +66,7 @@ struct FslIMX6ULState { DeviceState parent_obj; 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Instead of initializing the field with object_initialize(), allocate it with object_new(). As we don't access ARMCPU internal fields or size, we can move from arm_ss[] to the more generic softmmu_ss[] the followin units: - allwinner-a10.c - allwinner-h3.c - cubieboard.c - orangepi.c Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/allwinner-a10.c | 10 +++++----- hw/arm/allwinner-h3.c | 14 +++++++------- hw/arm/cubieboard.c | 2 +- hw/arm/meson.build | 4 ++-- include/hw/arm/allwinner-a10.h | 4 ++-- include/hw/arm/allwinner-h3.h | 4 ++-- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 79082289ea..685673e7bd 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -39,8 +39,8 @@ static void aw_a10_init(Object *obj) { AwA10State *s = AW_A10(obj); - object_initialize_child(obj, "cpu", &s->cpu, - ARM_CPU_TYPE_NAME("cortex-a8")); + s->cpu = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a8"))); + object_property_add_child(obj, "cpu", OBJECT(s->cpu)); object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC); @@ -71,7 +71,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) AwA10State *s = AW_A10(dev); SysBusDevice *sysbusdev; - if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { return; } @@ -81,9 +81,9 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbusdev = SYS_BUS_DEVICE(&s->intc); sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); sysbus_connect_irq(sysbusdev, 0, - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(sysbusdev, 1, - qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 308ed15552..1409101b3a 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -192,8 +192,8 @@ static void allwinner_h3_init(Object *obj) s->memmap = allwinner_h3_memmap; for (int i = 0; i < AW_H3_NUM_CPUS; i++) { - object_initialize_child(obj, "cpu[*]", &s->cpus[i], - ARM_CPU_TYPE_NAME("cortex-a7")); + s->cpus[i] = ARM_CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a7"))); + object_property_add_child(obj, "cpu[*]", OBJECT(s->cpus[i])); } object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); @@ -239,15 +239,15 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) * Disable secondary CPUs. Guest EL3 firmware will start * them via CPU reset control registers. */ - qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", + qdev_prop_set_bit(DEVICE(s->cpus[i]), "start-powered-off", i > 0); /* All exception levels required */ - qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); - qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); + qdev_prop_set_bit(DEVICE(s->cpus[i]), "has_el3", true); + qdev_prop_set_bit(DEVICE(s->cpus[i]), "has_el2", true); /* Mark realized */ - qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal); + qdev_realize(DEVICE(s->cpus[i]), NULL, &error_fatal); } /* Generic Interrupt Controller */ @@ -270,7 +270,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. */ for (i = 0; i < AW_H3_NUM_CPUS; i++) { - DeviceState *cpudev = DEVICE(&s->cpus[i]); + DeviceState *cpudev = DEVICE(s->cpus[i]); int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; int irq; /* diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 5e3372a3c7..fcb366d4ac 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -96,7 +96,7 @@ static void cubieboard_init(MachineState *machine) /* TODO create and connect IDE devices for ide_drive_get() */ cubieboard_binfo.ram_size = machine->ram_size; - arm_load_kernel(&a10->cpu, machine, &cubieboard_binfo); + arm_load_kernel(a10->cpu, machine, &cubieboard_binfo); } static void cubieboard_machine_init(MachineClass *mc) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index a7ee21e32f..06c9f1c86b 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -14,8 +14,6 @@ arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c')) arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) -arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) -arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xlnx-versal-virt.c')) @@ -27,6 +25,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'fby35.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) softmmu_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) softmmu_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index f9240ffa64..3a3ccc390f 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -13,8 +13,8 @@ #include "hw/usb/hcd-ohci.h" #include "hw/usb/hcd-ehci.h" #include "hw/rtc/allwinner-rtc.h" +#include "hw/arm/cpu.h" -#include "target/arm/cpu.h" #include "qom/object.h" @@ -30,7 +30,7 @@ struct AwA10State { DeviceState parent_obj; /*< public >*/ - ARMCPU cpu; + ARMCPU *cpu; AwA10PITState timer; AwA10PICState intc; AwEmacState emac; diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 63025fb27c..5e8be4392e 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -47,7 +47,7 @@ #include "hw/sd/allwinner-sdhost.h" #include "hw/net/allwinner-sun8i-emac.h" #include "hw/rtc/allwinner-rtc.h" -#include "target/arm/cpu.h" +#include "hw/arm/cpu.h" #include "sysemu/block-backend.h" /** @@ -121,7 +121,7 @@ struct AwH3State { DeviceState parent_obj; /*< public >*/ - ARMCPU cpus[AW_H3_NUM_CPUS]; + ARMCPU *cpus[AW_H3_NUM_CPUS]; const hwaddr *memmap; AwA10PITState timer; AwH3ClockCtlState ccu;